Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14623565

1

T1

245

T2

7248

T4

8

full_word

123265991

1

T1

2894

T2

72481

T4

145

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	137889256	1			T1	3139		T2	79729		T4	153
auto[TlIntgErrCmd]	88	1			T42	2		T43	6		T47	4
auto[TlIntgErrData]	102	1			T42	10		T43	1		T47	3
auto[TlIntgErrBoth]	110	1			T42	8		T43	3		T47	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66553350

1

T1

1582

T2

39686

T4

82

auto[1]

71336206

1

T1

1557

T2

40043

T4

71

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7202653	1			T1	111		T2	3658		T4	4
auto[TlIntgErrNone]	partial	auto[1]	7420639	1			T1	134		T2	3590		T4	4
auto[TlIntgErrNone]	full_word	auto[0]	59350563	1			T1	1471		T2	36028		T4	78
auto[TlIntgErrNone]	full_word	auto[1]	63915401	1			T1	1423		T2	36453		T4	67
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T43	4		T47	1		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T42	2		T43	2		T47	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T47	1		T125	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T120	1		T125	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T42	1		T47	2		T117	1
auto[TlIntgErrData]	partial	auto[1]	45	1			T42	8		T43	1		T47	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T127	1		T119	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T42	1		T127	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T42	2		T43	2		T117	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T42	6		T43	1		T47	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T130	1		T128	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T124	1		T125	1		T94	2