Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	757012	1			T4	15		T14	87		T6	8503
auto[1]	10322381	1			T1	1570		T2	17045		T4	3
auto[2]	582854	1			T4	10		T14	71		T6	5149
auto[3]	10160667	1			T1	1546		T2	17039		T4	1

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12889044	1			T1	2631		T2	28312		T4	27
auto[1]	2071544	1			T1	250		T2	2686		T4	1
auto[2]	2097750	1			T1	220		T2	2848		T4	1
auto[3]	4764576	1			T1	15		T2	238		T5	16

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8073988

1

T1

3116

T2

34081

T4

29

auto[1]

13748926

1

T2

3

T16

87693

T17

262205

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	314708	1			T4	14		T14	75		T6	6971
auto[0]	auto[0]	auto[1]	33634	1			T14	4		T6	709		T22	119
auto[0]	auto[0]	auto[2]	33425	1			T4	1		T14	7		T6	733
auto[0]	auto[0]	auto[3]	125514	1			T14	1		T6	89		T22	7
auto[0]	auto[1]	auto[0]	2539205	1			T1	1334		T2	14161		T4	2
auto[0]	auto[1]	auto[1]	277978	1			T1	126		T2	1300		T4	1
auto[0]	auto[1]	auto[2]	296948	1			T1	103		T2	1467		T5	37
auto[0]	auto[1]	auto[3]	539104	1			T1	7		T2	115		T5	12
auto[0]	auto[2]	auto[0]	231012	1			T4	10		T14	59		T6	4088
auto[0]	auto[2]	auto[1]	32935	1			T14	7		T6	387		T22	53
auto[0]	auto[2]	auto[2]	23156	1			T14	5		T6	602		T22	73
auto[0]	auto[2]	auto[3]	87837	1			T6	72		T22	10		T109	6
auto[0]	auto[3]	auto[0]	2469439	1			T1	1297		T2	14148		T4	1
auto[0]	auto[3]	auto[1]	283931	1			T1	124		T2	1386		T5	18
auto[0]	auto[3]	auto[2]	305648	1			T1	117		T2	1381		T5	60
auto[0]	auto[3]	auto[3]	479514	1			T1	8		T2	123		T5	4
auto[1]	auto[0]	auto[0]	8260	1			T6	1		T109	569		T113	1009
auto[1]	auto[0]	auto[1]	37454	1			T109	2424		T113	4807		T136	1126
auto[1]	auto[0]	auto[2]	37208	1			T109	2497		T113	4786		T136	1055
auto[1]	auto[0]	auto[3]	166809	1			T109	11375		T113	21028		T136	4812
auto[1]	auto[1]	auto[0]	3661437	1			T2	2		T16	36510		T17	4749
auto[1]	auto[1]	auto[1]	690074	1			T16	3537		T17	18930		T64	10426
auto[1]	auto[1]	auto[2]	688327	1			T16	3782		T17	20979		T64	11611
auto[1]	auto[1]	auto[3]	1629308	1			T16	353		T17	86036		T64	46756
auto[1]	auto[2]	auto[0]	7175	1			T109	537		T113	970		T136	155
auto[1]	auto[2]	auto[1]	32018	1			T109	2270		T113	4412		T136	620
auto[1]	auto[2]	auto[2]	30518	1			T109	2079		T113	3999		T136	1087
auto[1]	auto[2]	auto[3]	138203	1			T109	9590		T113	18009		T136	4671
auto[1]	auto[3]	auto[0]	3657808	1			T2	1		T16	36142		T17	4721
auto[1]	auto[3]	auto[1]	683520	1			T16	3676		T17	21383		T64	11560
auto[1]	auto[3]	auto[2]	682520	1			T16	3372		T17	19362		T64	10369
auto[1]	auto[3]	auto[3]	1598287	1			T16	321		T17	86045		T64	46219