Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	964301642	133632	0	0
ctrl_regwen_rd_A	964301642	7618	0	0
exec_rd_A	964301642	7044	0	0
exec_regwen_rd_A	964301642	7929	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	964301642	133632	0	0
T27	54168	1135	0	0
T28	0	3706	0	0
T29	0	10	0	0
T37	282375	0	0	0
T38	173907	0	0	0
T39	311757	0	0	0
T40	0	123	0	0
T41	0	519	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	374	0	0
T45	0	154	0	0
T50	109797	0	0	0
T51	76734	0	0	0
T52	112910	0	0	0
T53	117332	0	0	0
T54	490875	0	0	0
T55	48293	0	0	0
T56	0	1	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	964301642	7618	0	0
T42	24885	56	0	0
T47	10476	35	0	0
T48	3430	0	0	0
T49	7073	0	0	0
T58	1600	2	0	0
T60	1354	3	0	0
T61	1492	0	0	0
T62	963	0	0	0
T63	934	0	0	0
T68	0	10	0	0
T117	10988	19	0	0
T118	0	50	0	0
T119	0	66	0	0
T120	0	12	0	0
T121	0	50	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	964301642	7044	0	0
T42	24885	75	0	0
T46	34781	0	0	0
T47	10476	28	0	0
T48	3430	0	0	0
T56	33705	9	0	0
T58	1600	8	0	0
T60	1354	4	0	0
T61	1492	0	0	0
T107	1264	0	0	0
T108	1023	0	0	0
T117	0	45	0	0
T118	0	11	0	0
T119	0	76	0	0
T120	0	11	0	0
T121	0	98	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	964301642	7929	0	0
T42	24885	95	0	0
T47	10476	32	0	0
T48	3430	0	0	0
T49	7073	0	0	0
T58	1600	7	0	0
T60	1354	3	0	0
T61	1492	0	0	0
T62	963	0	0	0
T63	934	0	0	0
T68	0	5	0	0
T117	10988	46	0	0
T118	0	47	0	0
T119	0	77	0	0
T120	0	28	0	0
T121	0	68	0	0