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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.52 100.00 98.32 100.00 100.00 99.72 99.70 98.89


Total test records in report: 964
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T753 /workspace/coverage/default/4.sram_ctrl_multiple_keys.3040607989 Jan 21 12:32:06 PM PST 24 Jan 21 12:32:57 PM PST 24 1686501914 ps
T754 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.962045948 Jan 21 12:35:01 PM PST 24 Jan 21 12:53:48 PM PST 24 10038068399 ps
T755 /workspace/coverage/default/25.sram_ctrl_alert_test.951843982 Jan 21 12:56:27 PM PST 24 Jan 21 12:56:28 PM PST 24 11347455 ps
T756 /workspace/coverage/default/21.sram_ctrl_smoke.4275429766 Jan 21 12:37:36 PM PST 24 Jan 21 12:37:53 PM PST 24 1575953148 ps
T757 /workspace/coverage/default/33.sram_ctrl_stress_all.3266523242 Jan 21 01:33:18 PM PST 24 Jan 21 03:31:51 PM PST 24 268204556039 ps
T758 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.268925763 Jan 21 12:57:00 PM PST 24 Jan 21 01:18:01 PM PST 24 113175663825 ps
T759 /workspace/coverage/default/40.sram_ctrl_alert_test.3837346954 Jan 21 12:47:42 PM PST 24 Jan 21 12:47:45 PM PST 24 13190972 ps
T760 /workspace/coverage/default/14.sram_ctrl_max_throughput.2512135605 Jan 21 12:34:55 PM PST 24 Jan 21 12:35:31 PM PST 24 2882570877 ps
T761 /workspace/coverage/default/36.sram_ctrl_alert_test.257281205 Jan 21 12:44:37 PM PST 24 Jan 21 12:44:39 PM PST 24 21564767 ps
T762 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2055332939 Jan 21 01:10:16 PM PST 24 Jan 21 01:21:31 PM PST 24 28506290239 ps
T763 /workspace/coverage/default/30.sram_ctrl_executable.3392291383 Jan 21 03:05:05 PM PST 24 Jan 21 03:24:09 PM PST 24 26434345562 ps
T764 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.106351022 Jan 21 12:41:58 PM PST 24 Jan 21 12:49:51 PM PST 24 7313825991 ps
T765 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1830358138 Jan 21 01:45:50 PM PST 24 Jan 21 01:48:18 PM PST 24 13873859629 ps
T766 /workspace/coverage/default/37.sram_ctrl_max_throughput.3468490074 Jan 21 12:44:45 PM PST 24 Jan 21 12:46:47 PM PST 24 3598230758 ps
T767 /workspace/coverage/default/34.sram_ctrl_smoke.1309335511 Jan 21 12:42:41 PM PST 24 Jan 21 12:43:12 PM PST 24 13966095721 ps
T768 /workspace/coverage/default/33.sram_ctrl_smoke.1471130227 Jan 21 01:39:32 PM PST 24 Jan 21 01:39:49 PM PST 24 1739742064 ps
T769 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3418913635 Jan 21 12:40:44 PM PST 24 Jan 21 12:42:00 PM PST 24 988336227 ps
T34 /workspace/coverage/default/0.sram_ctrl_sec_cm.2894688681 Jan 21 12:31:58 PM PST 24 Jan 21 12:32:22 PM PST 24 974875414 ps
T770 /workspace/coverage/default/13.sram_ctrl_smoke.1366911487 Jan 21 12:34:28 PM PST 24 Jan 21 12:36:41 PM PST 24 1979377508 ps
T771 /workspace/coverage/default/36.sram_ctrl_regwen.937284366 Jan 21 12:44:05 PM PST 24 Jan 21 01:15:58 PM PST 24 3133059332 ps
T772 /workspace/coverage/default/28.sram_ctrl_partial_access.4078317287 Jan 21 12:40:18 PM PST 24 Jan 21 12:40:38 PM PST 24 1034740539 ps
T773 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1698178549 Jan 21 12:40:22 PM PST 24 Jan 21 12:44:37 PM PST 24 15112540961 ps
T774 /workspace/coverage/default/5.sram_ctrl_smoke.383087169 Jan 21 12:32:17 PM PST 24 Jan 21 12:33:03 PM PST 24 1032077946 ps
T775 /workspace/coverage/default/33.sram_ctrl_multiple_keys.2719446322 Jan 21 01:10:47 PM PST 24 Jan 21 01:31:49 PM PST 24 58066726730 ps
T776 /workspace/coverage/default/26.sram_ctrl_mem_walk.2763664369 Jan 21 01:03:44 PM PST 24 Jan 21 01:09:50 PM PST 24 229632941824 ps
T777 /workspace/coverage/default/7.sram_ctrl_lc_escalation.2315406292 Jan 21 12:32:54 PM PST 24 Jan 21 12:35:20 PM PST 24 29043988079 ps
T778 /workspace/coverage/default/28.sram_ctrl_max_throughput.3875740765 Jan 21 12:40:22 PM PST 24 Jan 21 12:40:50 PM PST 24 977213188 ps
T779 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4213894604 Jan 21 12:49:57 PM PST 24 Jan 21 12:56:15 PM PST 24 34958917127 ps
T780 /workspace/coverage/default/1.sram_ctrl_multiple_keys.867710262 Jan 21 12:31:55 PM PST 24 Jan 21 12:44:00 PM PST 24 5968320707 ps
T781 /workspace/coverage/default/28.sram_ctrl_alert_test.869753308 Jan 21 12:40:33 PM PST 24 Jan 21 12:40:34 PM PST 24 41549008 ps
T782 /workspace/coverage/default/24.sram_ctrl_mem_walk.684728323 Jan 21 12:38:55 PM PST 24 Jan 21 12:41:24 PM PST 24 28718899198 ps
T783 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2307891626 Jan 21 12:49:17 PM PST 24 Jan 21 12:52:47 PM PST 24 3776174031 ps
T784 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1558811864 Jan 21 12:50:06 PM PST 24 Jan 21 12:51:18 PM PST 24 1971173128 ps
T785 /workspace/coverage/default/11.sram_ctrl_multiple_keys.784154731 Jan 21 12:33:53 PM PST 24 Jan 21 12:58:13 PM PST 24 22563150211 ps
T786 /workspace/coverage/default/48.sram_ctrl_bijection.2188265965 Jan 21 12:49:57 PM PST 24 Jan 21 01:35:10 PM PST 24 719553523516 ps
T787 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3751119008 Jan 21 12:33:23 PM PST 24 Jan 21 12:34:28 PM PST 24 773523960 ps
T788 /workspace/coverage/default/16.sram_ctrl_alert_test.595596685 Jan 21 12:35:46 PM PST 24 Jan 21 12:35:55 PM PST 24 17891205 ps
T789 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1327250559 Jan 21 12:48:39 PM PST 24 Jan 21 01:44:53 PM PST 24 2038170342 ps
T790 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1702894824 Jan 21 12:37:36 PM PST 24 Jan 21 12:40:32 PM PST 24 10090435429 ps
T791 /workspace/coverage/default/49.sram_ctrl_mem_walk.3295399180 Jan 21 01:50:53 PM PST 24 Jan 21 01:52:55 PM PST 24 2059650240 ps
T792 /workspace/coverage/default/23.sram_ctrl_executable.3594981348 Jan 21 12:38:24 PM PST 24 Jan 21 12:59:00 PM PST 24 95097275850 ps
T793 /workspace/coverage/default/38.sram_ctrl_alert_test.2371456314 Jan 21 12:45:38 PM PST 24 Jan 21 12:45:43 PM PST 24 171477972 ps
T794 /workspace/coverage/default/24.sram_ctrl_ram_cfg.2896384944 Jan 21 12:38:55 PM PST 24 Jan 21 12:39:03 PM PST 24 1993655085 ps
T795 /workspace/coverage/default/43.sram_ctrl_regwen.402227632 Jan 21 01:21:14 PM PST 24 Jan 21 01:33:29 PM PST 24 30110664581 ps
T796 /workspace/coverage/default/12.sram_ctrl_mem_walk.3958384640 Jan 21 12:34:24 PM PST 24 Jan 21 12:36:56 PM PST 24 20681947707 ps
T797 /workspace/coverage/default/46.sram_ctrl_max_throughput.1596424782 Jan 21 12:49:14 PM PST 24 Jan 21 12:49:42 PM PST 24 699185107 ps
T798 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.624539790 Jan 21 12:33:38 PM PST 24 Jan 21 12:39:41 PM PST 24 55523683059 ps
T799 /workspace/coverage/default/9.sram_ctrl_alert_test.2163191409 Jan 21 12:33:30 PM PST 24 Jan 21 12:33:32 PM PST 24 23109785 ps
T800 /workspace/coverage/default/21.sram_ctrl_bijection.346460617 Jan 21 12:37:40 PM PST 24 Jan 21 01:13:12 PM PST 24 32116589374 ps
T801 /workspace/coverage/default/45.sram_ctrl_lc_escalation.1146422530 Jan 21 12:48:48 PM PST 24 Jan 21 12:49:13 PM PST 24 6550642808 ps
T802 /workspace/coverage/default/6.sram_ctrl_bijection.1637066809 Jan 21 12:32:30 PM PST 24 Jan 21 12:40:10 PM PST 24 28711429141 ps
T803 /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1131825530 Jan 21 12:49:47 PM PST 24 Jan 21 02:35:43 PM PST 24 1444502523 ps
T804 /workspace/coverage/default/49.sram_ctrl_regwen.176220343 Jan 21 12:50:30 PM PST 24 Jan 21 01:14:25 PM PST 24 17702073741 ps
T805 /workspace/coverage/default/7.sram_ctrl_regwen.3983563413 Jan 21 12:33:00 PM PST 24 Jan 21 12:49:38 PM PST 24 18891255179 ps
T806 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3307821608 Jan 21 12:38:54 PM PST 24 Jan 21 12:40:12 PM PST 24 2695792795 ps
T90 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2883286627 Jan 21 12:33:45 PM PST 24 Jan 21 12:35:02 PM PST 24 4031629339 ps
T807 /workspace/coverage/default/33.sram_ctrl_partial_access.2055693522 Jan 21 01:04:06 PM PST 24 Jan 21 01:04:42 PM PST 24 3773172311 ps
T808 /workspace/coverage/default/42.sram_ctrl_alert_test.3071821761 Jan 21 12:47:39 PM PST 24 Jan 21 12:47:40 PM PST 24 22261082 ps
T809 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2965464900 Jan 21 12:38:15 PM PST 24 Jan 21 12:39:35 PM PST 24 3195982126 ps
T810 /workspace/coverage/default/5.sram_ctrl_partial_access.2244580980 Jan 21 12:32:22 PM PST 24 Jan 21 12:33:46 PM PST 24 1009832372 ps
T811 /workspace/coverage/default/9.sram_ctrl_multiple_keys.4071888574 Jan 21 12:33:14 PM PST 24 Jan 21 12:41:36 PM PST 24 7598748624 ps
T812 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1444653001 Jan 21 01:20:09 PM PST 24 Jan 21 01:31:37 PM PST 24 16848873692 ps
T813 /workspace/coverage/default/1.sram_ctrl_smoke.498695313 Jan 21 12:32:03 PM PST 24 Jan 21 12:32:54 PM PST 24 7357519573 ps
T814 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.578520661 Jan 21 01:01:46 PM PST 24 Jan 21 01:04:11 PM PST 24 4421767676 ps
T815 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2601685506 Jan 21 12:32:05 PM PST 24 Jan 21 12:36:30 PM PST 24 7097861720 ps
T816 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2432970917 Jan 21 12:37:48 PM PST 24 Jan 21 12:39:16 PM PST 24 1304187396 ps
T817 /workspace/coverage/default/45.sram_ctrl_smoke.3266532079 Jan 21 12:48:51 PM PST 24 Jan 21 12:49:28 PM PST 24 707663687 ps
T818 /workspace/coverage/default/45.sram_ctrl_stress_all.4023379562 Jan 21 12:49:00 PM PST 24 Jan 21 01:36:54 PM PST 24 112233972887 ps
T819 /workspace/coverage/default/10.sram_ctrl_bijection.1520105094 Jan 21 12:33:33 PM PST 24 Jan 21 12:52:15 PM PST 24 32799170997 ps
T820 /workspace/coverage/default/13.sram_ctrl_multiple_keys.1500038034 Jan 21 12:34:25 PM PST 24 Jan 21 12:58:10 PM PST 24 14055574217 ps
T821 /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1196474095 Jan 21 12:32:03 PM PST 24 Jan 21 12:33:51 PM PST 24 1568179646 ps
T822 /workspace/coverage/default/13.sram_ctrl_stress_all.4035865178 Jan 21 12:34:48 PM PST 24 Jan 21 02:42:47 PM PST 24 520033502470 ps
T823 /workspace/coverage/default/19.sram_ctrl_regwen.4202212232 Jan 21 02:30:28 PM PST 24 Jan 21 02:53:10 PM PST 24 9220559278 ps
T824 /workspace/coverage/default/15.sram_ctrl_alert_test.1703188759 Jan 21 12:35:25 PM PST 24 Jan 21 12:35:46 PM PST 24 56092893 ps
T825 /workspace/coverage/default/5.sram_ctrl_regwen.680810500 Jan 21 12:32:14 PM PST 24 Jan 21 12:35:39 PM PST 24 10104925309 ps
T826 /workspace/coverage/default/41.sram_ctrl_bijection.2439570878 Jan 21 12:46:45 PM PST 24 Jan 21 12:59:38 PM PST 24 48505216456 ps
T827 /workspace/coverage/default/49.sram_ctrl_executable.3387979246 Jan 21 12:50:35 PM PST 24 Jan 21 01:06:27 PM PST 24 16928514883 ps
T828 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1938557149 Jan 21 12:43:59 PM PST 24 Jan 21 12:49:54 PM PST 24 6232991795 ps
T829 /workspace/coverage/default/26.sram_ctrl_max_throughput.747230758 Jan 21 12:39:35 PM PST 24 Jan 21 12:41:13 PM PST 24 1548824117 ps
T830 /workspace/coverage/default/21.sram_ctrl_partial_access.640955742 Jan 21 12:37:37 PM PST 24 Jan 21 12:37:52 PM PST 24 2115172068 ps
T831 /workspace/coverage/default/11.sram_ctrl_bijection.1599668056 Jan 21 02:33:40 PM PST 24 Jan 21 03:08:12 PM PST 24 121563707109 ps
T832 /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2355126112 Jan 21 12:31:56 PM PST 24 Jan 21 12:37:07 PM PST 24 47988041328 ps
T833 /workspace/coverage/default/17.sram_ctrl_partial_access.180482964 Jan 21 12:35:54 PM PST 24 Jan 21 12:36:54 PM PST 24 1086165714 ps
T834 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3877924006 Jan 21 12:33:10 PM PST 24 Jan 21 12:52:36 PM PST 24 16848266635 ps
T835 /workspace/coverage/default/35.sram_ctrl_stress_all.3882566780 Jan 21 12:43:47 PM PST 24 Jan 21 01:36:27 PM PST 24 60329228053 ps
T836 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4238832419 Jan 21 12:37:33 PM PST 24 Jan 21 02:13:56 PM PST 24 7721067730 ps
T837 /workspace/coverage/default/38.sram_ctrl_lc_escalation.304116897 Jan 21 12:45:22 PM PST 24 Jan 21 12:46:40 PM PST 24 23835875937 ps
T838 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1479995582 Jan 21 12:38:32 PM PST 24 Jan 21 12:39:51 PM PST 24 12097052896 ps
T839 /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1887392561 Jan 21 12:33:52 PM PST 24 Jan 21 12:40:07 PM PST 24 4706763784 ps
T840 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1335605367 Jan 21 12:35:27 PM PST 24 Jan 21 12:37:05 PM PST 24 2667805748 ps
T841 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.465702096 Jan 21 12:45:23 PM PST 24 Jan 21 12:45:52 PM PST 24 699880676 ps
T842 /workspace/coverage/default/22.sram_ctrl_max_throughput.2883641584 Jan 21 12:53:30 PM PST 24 Jan 21 12:54:17 PM PST 24 776606999 ps
T843 /workspace/coverage/default/31.sram_ctrl_max_throughput.3768433116 Jan 21 12:41:27 PM PST 24 Jan 21 12:43:20 PM PST 24 883709233 ps
T844 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.899106938 Jan 21 12:34:13 PM PST 24 Jan 21 12:37:11 PM PST 24 7742761470 ps
T845 /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2087583729 Jan 21 12:32:03 PM PST 24 Jan 21 12:40:39 PM PST 24 76823985281 ps
T846 /workspace/coverage/default/14.sram_ctrl_mem_walk.2101607253 Jan 21 12:35:04 PM PST 24 Jan 21 12:38:55 PM PST 24 4108802444 ps
T847 /workspace/coverage/default/11.sram_ctrl_max_throughput.3441590971 Jan 21 12:33:52 PM PST 24 Jan 21 12:35:58 PM PST 24 1531938486 ps
T848 /workspace/coverage/default/16.sram_ctrl_stress_all.2348597320 Jan 21 12:35:49 PM PST 24 Jan 21 02:05:37 PM PST 24 584493790606 ps
T849 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2124686929 Jan 21 12:50:27 PM PST 24 Jan 21 01:18:48 PM PST 24 51947003266 ps
T850 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1629678686 Jan 21 12:47:39 PM PST 24 Jan 21 12:50:31 PM PST 24 10076735834 ps
T851 /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1132805091 Jan 21 12:35:10 PM PST 24 Jan 21 12:39:26 PM PST 24 20082866950 ps
T852 /workspace/coverage/default/7.sram_ctrl_mem_walk.616516270 Jan 21 12:33:08 PM PST 24 Jan 21 12:35:28 PM PST 24 6903443426 ps
T853 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2109694759 Jan 21 12:54:48 PM PST 24 Jan 21 12:59:44 PM PST 24 101329197235 ps
T854 /workspace/coverage/default/39.sram_ctrl_regwen.4037537191 Jan 21 01:07:35 PM PST 24 Jan 21 01:27:26 PM PST 24 4919563578 ps
T855 /workspace/coverage/default/19.sram_ctrl_max_throughput.3056352936 Jan 21 12:36:50 PM PST 24 Jan 21 12:39:25 PM PST 24 1568639461 ps
T856 /workspace/coverage/default/38.sram_ctrl_ram_cfg.3207298140 Jan 21 12:45:25 PM PST 24 Jan 21 12:45:32 PM PST 24 711266389 ps
T857 /workspace/coverage/default/22.sram_ctrl_multiple_keys.4276192728 Jan 21 12:37:52 PM PST 24 Jan 21 01:06:08 PM PST 24 26485059470 ps
T858 /workspace/coverage/default/6.sram_ctrl_executable.4201693827 Jan 21 12:32:32 PM PST 24 Jan 21 12:55:35 PM PST 24 67844308759 ps
T859 /workspace/coverage/default/27.sram_ctrl_alert_test.1191643237 Jan 21 12:40:18 PM PST 24 Jan 21 12:40:20 PM PST 24 21015938 ps
T860 /workspace/coverage/default/37.sram_ctrl_executable.3700079740 Jan 21 12:44:52 PM PST 24 Jan 21 12:59:36 PM PST 24 20005376845 ps
T861 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2045336262 Jan 21 12:39:41 PM PST 24 Jan 21 12:41:56 PM PST 24 6516093841 ps
T862 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3305055946 Jan 21 01:25:59 PM PST 24 Jan 21 01:31:25 PM PST 24 4343310859 ps
T863 /workspace/coverage/default/37.sram_ctrl_alert_test.3164226315 Jan 21 02:08:30 PM PST 24 Jan 21 02:08:32 PM PST 24 14659934 ps
T864 /workspace/coverage/default/45.sram_ctrl_max_throughput.815737989 Jan 21 12:48:48 PM PST 24 Jan 21 12:49:18 PM PST 24 2819536598 ps
T865 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1151249539 Jan 21 12:42:55 PM PST 24 Jan 21 12:49:35 PM PST 24 10469001752 ps
T866 /workspace/coverage/default/16.sram_ctrl_regwen.2471889344 Jan 21 12:35:49 PM PST 24 Jan 21 12:54:25 PM PST 24 11714996196 ps
T867 /workspace/coverage/default/46.sram_ctrl_bijection.2688670619 Jan 21 12:49:16 PM PST 24 Jan 21 01:32:18 PM PST 24 566588630600 ps
T868 /workspace/coverage/default/8.sram_ctrl_alert_test.3467428505 Jan 21 12:33:15 PM PST 24 Jan 21 12:33:16 PM PST 24 25321579 ps
T869 /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2462142296 Jan 21 01:31:32 PM PST 24 Jan 21 01:39:56 PM PST 24 32182915478 ps
T870 /workspace/coverage/default/15.sram_ctrl_stress_all.2790134283 Jan 21 12:35:26 PM PST 24 Jan 21 02:51:18 PM PST 24 730201660616 ps
T871 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2268572161 Jan 21 12:32:26 PM PST 24 Jan 21 12:35:06 PM PST 24 39474430945 ps
T872 /workspace/coverage/default/2.sram_ctrl_lc_escalation.3438699548 Jan 21 12:32:04 PM PST 24 Jan 21 12:38:18 PM PST 24 15106146919 ps
T873 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.798600722 Jan 21 12:32:09 PM PST 24 Jan 21 01:19:40 PM PST 24 421602128 ps
T874 /workspace/coverage/default/39.sram_ctrl_max_throughput.3047213169 Jan 21 12:45:55 PM PST 24 Jan 21 12:48:09 PM PST 24 3236732273 ps
T875 /workspace/coverage/default/41.sram_ctrl_smoke.25549717 Jan 21 12:46:45 PM PST 24 Jan 21 12:48:35 PM PST 24 3742883208 ps
T876 /workspace/coverage/default/1.sram_ctrl_access_during_key_req.4026786472 Jan 21 12:32:04 PM PST 24 Jan 21 12:40:10 PM PST 24 8855573114 ps
T877 /workspace/coverage/default/35.sram_ctrl_max_throughput.901936518 Jan 21 12:43:34 PM PST 24 Jan 21 12:46:00 PM PST 24 758320169 ps
T878 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1091061593 Jan 21 12:39:26 PM PST 24 Jan 21 12:42:01 PM PST 24 9934039964 ps
T879 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2688268373 Jan 21 12:33:37 PM PST 24 Jan 21 12:50:39 PM PST 24 19848572160 ps
T880 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3867167046 Jan 21 12:49:30 PM PST 24 Jan 21 12:52:03 PM PST 24 24476859326 ps
T881 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2641420912 Jan 21 12:38:27 PM PST 24 Jan 21 12:38:44 PM PST 24 1931731332 ps
T882 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2269273863 Jan 21 12:58:05 PM PST 24 Jan 21 12:58:11 PM PST 24 552607347 ps
T883 /workspace/coverage/default/27.sram_ctrl_ram_cfg.2211448611 Jan 21 12:40:08 PM PST 24 Jan 21 12:40:15 PM PST 24 1523995981 ps
T884 /workspace/coverage/default/43.sram_ctrl_bijection.3134002136 Jan 21 12:47:41 PM PST 24 Jan 21 12:56:51 PM PST 24 32897604651 ps
T885 /workspace/coverage/default/15.sram_ctrl_multiple_keys.3300238888 Jan 21 12:56:09 PM PST 24 Jan 21 01:17:11 PM PST 24 44099724666 ps
T886 /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2709257385 Jan 21 12:41:27 PM PST 24 Jan 21 12:53:20 PM PST 24 20756669888 ps
T887 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4281535737 Jan 21 12:35:18 PM PST 24 Jan 21 12:36:08 PM PST 24 3367181262 ps
T888 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3805513481 Jan 21 12:32:06 PM PST 24 Jan 21 01:58:57 PM PST 24 896308237 ps
T889 /workspace/coverage/default/22.sram_ctrl_partial_access.267746497 Jan 21 12:37:52 PM PST 24 Jan 21 12:40:21 PM PST 24 994999303 ps
T890 /workspace/coverage/default/40.sram_ctrl_executable.451365113 Jan 21 12:46:26 PM PST 24 Jan 21 12:50:37 PM PST 24 4567083250 ps
T891 /workspace/coverage/default/30.sram_ctrl_bijection.4024704337 Jan 21 12:41:05 PM PST 24 Jan 21 01:03:51 PM PST 24 40816296040 ps
T892 /workspace/coverage/default/29.sram_ctrl_stress_all.2566171309 Jan 21 12:41:03 PM PST 24 Jan 21 02:03:34 PM PST 24 1443334344221 ps
T893 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3327839572 Jan 21 12:39:40 PM PST 24 Jan 21 01:55:04 PM PST 24 1916449956 ps
T894 /workspace/coverage/default/27.sram_ctrl_multiple_keys.619995042 Jan 21 12:39:48 PM PST 24 Jan 21 12:54:52 PM PST 24 6484568061 ps
T895 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.709051291 Jan 21 12:49:48 PM PST 24 Jan 21 12:52:13 PM PST 24 44394920709 ps
T896 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1310660352 Jan 21 12:36:55 PM PST 24 Jan 21 12:38:23 PM PST 24 45701532471 ps
T897 /workspace/coverage/default/32.sram_ctrl_multiple_keys.256501713 Jan 21 12:41:58 PM PST 24 Jan 21 01:18:45 PM PST 24 14960726211 ps
T898 /workspace/coverage/default/27.sram_ctrl_partial_access.2411645795 Jan 21 12:39:55 PM PST 24 Jan 21 12:42:01 PM PST 24 1345121970 ps
T899 /workspace/coverage/default/21.sram_ctrl_lc_escalation.965625735 Jan 21 12:37:44 PM PST 24 Jan 21 12:38:23 PM PST 24 1371205684 ps
T900 /workspace/coverage/default/7.sram_ctrl_multiple_keys.2571084780 Jan 21 12:52:55 PM PST 24 Jan 21 01:08:41 PM PST 24 39122394014 ps
T901 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3379247416 Jan 21 12:35:52 PM PST 24 Jan 21 12:40:14 PM PST 24 15889394528 ps
T902 /workspace/coverage/default/20.sram_ctrl_partial_access.4144691099 Jan 21 12:37:13 PM PST 24 Jan 21 12:37:20 PM PST 24 363469069 ps
T903 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1249661724 Jan 21 12:42:59 PM PST 24 Jan 21 12:44:11 PM PST 24 19096195983 ps
T904 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3316486982 Jan 21 12:35:31 PM PST 24 Jan 21 12:36:30 PM PST 24 1506809434 ps
T905 /workspace/coverage/default/35.sram_ctrl_alert_test.2693468649 Jan 21 12:43:47 PM PST 24 Jan 21 12:43:48 PM PST 24 34404233 ps
T906 /workspace/coverage/default/27.sram_ctrl_executable.3381352882 Jan 21 12:39:59 PM PST 24 Jan 21 12:48:26 PM PST 24 41762715097 ps
T907 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2413448417 Jan 21 12:32:06 PM PST 24 Jan 21 12:37:08 PM PST 24 31900869009 ps
T908 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.297177394 Jan 21 12:36:29 PM PST 24 Jan 21 12:42:17 PM PST 24 5882199466 ps
T909 /workspace/coverage/default/3.sram_ctrl_executable.2147295655 Jan 21 12:32:04 PM PST 24 Jan 21 12:33:35 PM PST 24 3326203918 ps
T910 /workspace/coverage/default/19.sram_ctrl_executable.2239971107 Jan 21 12:36:56 PM PST 24 Jan 21 01:05:31 PM PST 24 46452169852 ps
T911 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2609559889 Jan 21 12:42:57 PM PST 24 Jan 21 01:08:12 PM PST 24 10843003608 ps
T912 /workspace/coverage/default/25.sram_ctrl_max_throughput.1004786582 Jan 21 12:39:09 PM PST 24 Jan 21 12:42:11 PM PST 24 1595849957 ps
T913 /workspace/coverage/default/46.sram_ctrl_alert_test.4245868950 Jan 21 12:49:33 PM PST 24 Jan 21 12:49:35 PM PST 24 15888614 ps
T914 /workspace/coverage/default/44.sram_ctrl_multiple_keys.2855788126 Jan 21 01:42:43 PM PST 24 Jan 21 01:48:39 PM PST 24 22858975690 ps
T915 /workspace/coverage/default/3.sram_ctrl_partial_access.4108311904 Jan 21 12:32:06 PM PST 24 Jan 21 12:33:29 PM PST 24 2644614247 ps
T916 /workspace/coverage/default/24.sram_ctrl_multiple_keys.491287978 Jan 21 12:38:45 PM PST 24 Jan 21 01:00:51 PM PST 24 9573830998 ps
T917 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.750299752 Jan 21 12:39:10 PM PST 24 Jan 21 12:42:46 PM PST 24 17889544140 ps
T918 /workspace/coverage/default/36.sram_ctrl_stress_pipeline.31355095 Jan 21 12:43:50 PM PST 24 Jan 21 12:48:13 PM PST 24 13966595447 ps
T919 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.132414809 Jan 21 12:31:51 PM PST 24 Jan 21 12:35:57 PM PST 24 3247516248 ps
T920 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3729991340 Jan 21 02:06:14 PM PST 24 Jan 21 02:30:40 PM PST 24 57251066448 ps
T921 /workspace/coverage/default/12.sram_ctrl_lc_escalation.2951978322 Jan 21 12:34:13 PM PST 24 Jan 21 12:38:57 PM PST 24 14416662648 ps
T922 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.419182886 Jan 21 12:41:35 PM PST 24 Jan 21 12:47:11 PM PST 24 175282349641 ps
T923 /workspace/coverage/default/11.sram_ctrl_mem_walk.1163520050 Jan 21 12:34:03 PM PST 24 Jan 21 12:38:06 PM PST 24 7882802303 ps
T924 /workspace/coverage/default/21.sram_ctrl_executable.3681600657 Jan 21 12:37:48 PM PST 24 Jan 21 01:01:23 PM PST 24 75687220334 ps
T925 /workspace/coverage/default/42.sram_ctrl_bijection.1557404055 Jan 21 01:15:50 PM PST 24 Jan 21 01:45:54 PM PST 24 116266152059 ps
T926 /workspace/coverage/default/15.sram_ctrl_partial_access.1785895067 Jan 21 12:35:17 PM PST 24 Jan 21 12:37:45 PM PST 24 1069962162 ps
T927 /workspace/coverage/default/29.sram_ctrl_max_throughput.2874936449 Jan 21 12:40:40 PM PST 24 Jan 21 12:41:10 PM PST 24 693204299 ps
T928 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2499144046 Jan 21 12:38:26 PM PST 24 Jan 21 12:38:43 PM PST 24 346734021 ps
T929 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.4243865693 Jan 21 12:44:44 PM PST 24 Jan 21 12:48:34 PM PST 24 10084837949 ps
T930 /workspace/coverage/default/25.sram_ctrl_bijection.3024374658 Jan 21 12:39:01 PM PST 24 Jan 21 01:03:15 PM PST 24 187062277109 ps
T931 /workspace/coverage/default/0.sram_ctrl_mem_walk.4198459778 Jan 21 12:31:57 PM PST 24 Jan 21 12:34:16 PM PST 24 2019038202 ps
T932 /workspace/coverage/default/31.sram_ctrl_regwen.3058559941 Jan 21 12:41:43 PM PST 24 Jan 21 01:01:09 PM PST 24 4473457055 ps
T933 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.22044998 Jan 21 12:42:51 PM PST 24 Jan 21 12:45:03 PM PST 24 797780460 ps
T934 /workspace/coverage/default/13.sram_ctrl_partial_access.4144125253 Jan 21 12:34:33 PM PST 24 Jan 21 12:34:42 PM PST 24 2171699135 ps
T935 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2120568886 Jan 21 12:37:13 PM PST 24 Jan 21 12:45:05 PM PST 24 77642324303 ps
T936 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3733994899 Jan 21 12:37:59 PM PST 24 Jan 21 12:43:56 PM PST 24 47124648521 ps
T937 /workspace/coverage/default/13.sram_ctrl_bijection.4273380945 Jan 21 12:34:34 PM PST 24 Jan 21 12:52:38 PM PST 24 32137152696 ps
T938 /workspace/coverage/default/11.sram_ctrl_regwen.2963649156 Jan 21 02:20:34 PM PST 24 Jan 21 02:27:23 PM PST 24 9148946955 ps
T939 /workspace/coverage/default/43.sram_ctrl_mem_walk.1883027153 Jan 21 01:09:32 PM PST 24 Jan 21 01:11:35 PM PST 24 2048508464 ps
T940 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1493361488 Jan 21 12:35:23 PM PST 24 Jan 21 01:48:42 PM PST 24 1192838568 ps
T941 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3245713271 Jan 21 12:35:31 PM PST 24 Jan 21 12:40:36 PM PST 24 4442332028 ps
T942 /workspace/coverage/default/5.sram_ctrl_bijection.247836782 Jan 21 12:32:22 PM PST 24 Jan 21 01:07:56 PM PST 24 620581078148 ps
T943 /workspace/coverage/default/44.sram_ctrl_bijection.2462558183 Jan 21 01:14:28 PM PST 24 Jan 21 01:48:29 PM PST 24 110969882918 ps
T944 /workspace/coverage/default/29.sram_ctrl_ram_cfg.969882066 Jan 21 12:40:55 PM PST 24 Jan 21 12:41:09 PM PST 24 709263260 ps
T945 /workspace/coverage/default/4.sram_ctrl_regwen.172799076 Jan 21 12:32:11 PM PST 24 Jan 21 12:38:15 PM PST 24 1546925451 ps
T946 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1345528940 Jan 21 12:36:29 PM PST 24 Jan 21 12:45:40 PM PST 24 5265675864 ps
T947 /workspace/coverage/default/29.sram_ctrl_multiple_keys.2456093843 Jan 21 12:40:41 PM PST 24 Jan 21 01:07:24 PM PST 24 88425421027 ps
T948 /workspace/coverage/default/47.sram_ctrl_ram_cfg.4167593133 Jan 21 12:49:47 PM PST 24 Jan 21 12:50:02 PM PST 24 369695543 ps
T949 /workspace/coverage/default/3.sram_ctrl_smoke.1124902035 Jan 21 12:32:06 PM PST 24 Jan 21 12:32:40 PM PST 24 3113897370 ps
T950 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.389549657 Jan 21 12:32:00 PM PST 24 Jan 21 12:33:07 PM PST 24 1404006234 ps
T951 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2500030887 Jan 21 12:34:06 PM PST 24 Jan 21 01:50:38 PM PST 24 6001252685 ps
T952 /workspace/coverage/default/15.sram_ctrl_executable.4151335431 Jan 21 12:35:19 PM PST 24 Jan 21 12:37:16 PM PST 24 7414869776 ps
T953 /workspace/coverage/default/44.sram_ctrl_lc_escalation.4167687689 Jan 21 01:26:23 PM PST 24 Jan 21 01:28:23 PM PST 24 41928499681 ps
T954 /workspace/coverage/default/16.sram_ctrl_partial_access.636866061 Jan 21 12:35:32 PM PST 24 Jan 21 12:36:15 PM PST 24 794018703 ps
T955 /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4202369916 Jan 21 12:36:10 PM PST 24 Jan 21 12:38:07 PM PST 24 3061329942 ps
T956 /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2810166735 Jan 21 01:10:32 PM PST 24 Jan 21 01:50:54 PM PST 24 1335439472 ps
T957 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.4204535514 Jan 21 12:36:24 PM PST 24 Jan 21 12:38:38 PM PST 24 6198935788 ps
T958 /workspace/coverage/default/8.sram_ctrl_bijection.3927842348 Jan 21 12:33:09 PM PST 24 Jan 21 01:02:43 PM PST 24 52588430791 ps
T959 /workspace/coverage/default/48.sram_ctrl_mem_walk.105301120 Jan 21 01:23:57 PM PST 24 Jan 21 01:26:37 PM PST 24 26496527120 ps
T960 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.648449857 Jan 21 12:53:53 PM PST 24 Jan 21 12:56:35 PM PST 24 3262328452 ps
T961 /workspace/coverage/default/32.sram_ctrl_partial_access.255532324 Jan 21 12:42:00 PM PST 24 Jan 21 12:42:21 PM PST 24 8944760075 ps
T962 /workspace/coverage/default/2.sram_ctrl_max_throughput.298320955 Jan 21 12:32:04 PM PST 24 Jan 21 12:32:50 PM PST 24 741124687 ps
T963 /workspace/coverage/default/39.sram_ctrl_mem_walk.3270229896 Jan 21 12:45:56 PM PST 24 Jan 21 12:50:05 PM PST 24 15147662140 ps
T964 /workspace/coverage/default/7.sram_ctrl_max_throughput.2557009038 Jan 21 12:32:56 PM PST 24 Jan 21 12:33:32 PM PST 24 802302179 ps

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.1157885457
Short name T4
Test name
Test status
Simulation time 9664265893 ps
CPU time 80.14 seconds
Started Jan 21 12:44:46 PM PST 24
Finished Jan 21 12:46:06 PM PST 24
Peak memory 210284 kb
Host smart-ed62c385-fb4a-411d-857e-12a03c9f9425
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157885457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.1157885457
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.926118701
Short name T14
Test name
Test status
Simulation time 18336224907 ps
CPU time 73.23 seconds
Started Jan 21 12:36:11 PM PST 24
Finished Jan 21 12:37:25 PM PST 24
Peak memory 232916 kb
Host smart-082058d4-29ec-4501-bc9e-40decb2a61dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926118701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.926118701
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.392948670
Short name T27
Test name
Test status
Simulation time 541712137 ps
CPU time 2269.12 seconds
Started Jan 21 12:41:05 PM PST 24
Finished Jan 21 01:18:57 PM PST 24
Peak memory 417748 kb
Host smart-a2535513-20a0-4820-8b37-b0000c2dcb40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=392948670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.392948670
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4029077139
Short name T64
Test name
Test status
Simulation time 20830842258 ps
CPU time 333.29 seconds
Started Jan 21 01:37:29 PM PST 24
Finished Jan 21 01:43:03 PM PST 24
Peak memory 202296 kb
Host smart-d80b8e72-f694-4f26-b57e-347a96114da1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029077139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.4029077139
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3004743494
Short name T42
Test name
Test status
Simulation time 507877609 ps
CPU time 2.37 seconds
Started Jan 21 01:09:36 PM PST 24
Finished Jan 21 01:09:39 PM PST 24
Peak memory 202312 kb
Host smart-456379fe-4c71-4770-a0a1-c119da2f8675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004743494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.3004743494
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.2738514586
Short name T6
Test name
Test status
Simulation time 202331653694 ps
CPU time 6596.21 seconds
Started Jan 21 12:47:03 PM PST 24
Finished Jan 21 02:37:01 PM PST 24
Peak memory 387172 kb
Host smart-c744c50b-6c19-480f-b7c8-36cb5bb28b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738514586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.2738514586
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.820270718
Short name T8
Test name
Test status
Simulation time 577956328 ps
CPU time 1.88 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:32:25 PM PST 24
Peak memory 231584 kb
Host smart-6821be0a-9fea-40cc-8412-38cdfeff4dc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820270718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_sec_cm.820270718
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1534779812
Short name T113
Test name
Test status
Simulation time 89508637934 ps
CPU time 478.53 seconds
Started Jan 21 12:36:10 PM PST 24
Finished Jan 21 12:44:10 PM PST 24
Peak memory 202152 kb
Host smart-836d0372-c0b4-4ccf-8c45-14aa6effc80b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534779812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.1534779812
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.1077282334
Short name T131
Test name
Test status
Simulation time 104595846512 ps
CPU time 4215.75 seconds
Started Jan 21 02:05:11 PM PST 24
Finished Jan 21 03:15:30 PM PST 24
Peak memory 382180 kb
Host smart-e7d704be-c7eb-4dfe-b5c6-46abc0b56bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077282334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.1077282334
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1980806914
Short name T125
Test name
Test status
Simulation time 604471714 ps
CPU time 2.35 seconds
Started Jan 21 12:24:53 PM PST 24
Finished Jan 21 12:24:58 PM PST 24
Peak memory 202352 kb
Host smart-3a5b755b-13d8-4f8f-a55b-a7e54757faa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980806914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.1980806914
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.890591676
Short name T19
Test name
Test status
Simulation time 5148122876 ps
CPU time 668.7 seconds
Started Jan 21 12:38:24 PM PST 24
Finished Jan 21 12:49:38 PM PST 24
Peak memory 376952 kb
Host smart-2d28f2e8-1d75-4563-91be-23c2b6c72d8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890591676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 23.sram_ctrl_access_during_key_req.890591676
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3287907089
Short name T57
Test name
Test status
Simulation time 52171502 ps
CPU time 1.74 seconds
Started Jan 21 01:32:11 PM PST 24
Finished Jan 21 01:32:13 PM PST 24
Peak memory 202296 kb
Host smart-e4db338b-b1c2-473c-aad1-37a383323507
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287907089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.3287907089
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.2589285695
Short name T30
Test name
Test status
Simulation time 344125672 ps
CPU time 5.12 seconds
Started Jan 21 12:34:20 PM PST 24
Finished Jan 21 12:34:26 PM PST 24
Peak memory 202388 kb
Host smart-5a2636f7-5b00-47e1-b209-0e72c62abca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589285695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2589285695
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1182100971
Short name T130
Test name
Test status
Simulation time 176515186 ps
CPU time 2.22 seconds
Started Jan 21 01:30:11 PM PST 24
Finished Jan 21 01:30:15 PM PST 24
Peak memory 202556 kb
Host smart-eb41a778-1849-4438-82ba-12108ed0dd2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182100971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.1182100971
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.1786703375
Short name T132
Test name
Test status
Simulation time 14538316152 ps
CPU time 1074.7 seconds
Started Jan 21 12:40:25 PM PST 24
Finished Jan 21 12:58:20 PM PST 24
Peak memory 378012 kb
Host smart-2a7924c1-7611-430a-9c70-8ec52984a5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786703375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.1786703375
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.1869291396
Short name T231
Test name
Test status
Simulation time 31751499 ps
CPU time 0.6 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:32:24 PM PST 24
Peak memory 201332 kb
Host smart-4db24bfd-4697-4070-bc9d-6d770c3e1fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869291396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.1869291396
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1366223626
Short name T151
Test name
Test status
Simulation time 688707225 ps
CPU time 12.48 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:49 PM PST 24
Peak memory 202288 kb
Host smart-64f79a99-b3a9-4b5c-bf28-66ffaf9b2bcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366223626 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1366223626
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.1712676455
Short name T192
Test name
Test status
Simulation time 23954629680 ps
CPU time 133.34 seconds
Started Jan 21 12:33:44 PM PST 24
Finished Jan 21 12:35:58 PM PST 24
Peak memory 202228 kb
Host smart-c978ec7b-69df-4f03-841e-80236e3cd458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712676455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.1712676455
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2680105016
Short name T79
Test name
Test status
Simulation time 46866566 ps
CPU time 0.62 seconds
Started Jan 21 12:24:53 PM PST 24
Finished Jan 21 12:24:56 PM PST 24
Peak memory 202048 kb
Host smart-ed27a04d-b881-49a2-b215-2a4ac61d9a5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680105016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.2680105016
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.615025683
Short name T67
Test name
Test status
Simulation time 13267976 ps
CPU time 0.71 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:37 PM PST 24
Peak memory 201120 kb
Host smart-d2cbe39e-90ac-468f-9c98-8a6d9619a47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615025683 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.615025683
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2502839551
Short name T115
Test name
Test status
Simulation time 50193854 ps
CPU time 0.73 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:37 PM PST 24
Peak memory 201932 kb
Host smart-d95cfb73-8bd4-4a32-9bb9-c351bb90c442
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502839551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.2502839551
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3938103109
Short name T91
Test name
Test status
Simulation time 102598952 ps
CPU time 1.5 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:38 PM PST 24
Peak memory 202176 kb
Host smart-88074ee1-bc68-401b-9ee6-167059c2a1e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938103109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.3938103109
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3373121917
Short name T101
Test name
Test status
Simulation time 6862803189 ps
CPU time 6.75 seconds
Started Jan 21 12:24:53 PM PST 24
Finished Jan 21 12:25:02 PM PST 24
Peak memory 210800 kb
Host smart-078ff691-1cb3-4540-9117-94c35926b5c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373121917 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3373121917
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2706760841
Short name T82
Test name
Test status
Simulation time 21487493 ps
CPU time 0.63 seconds
Started Jan 21 12:24:51 PM PST 24
Finished Jan 21 12:24:54 PM PST 24
Peak memory 201216 kb
Host smart-d2517264-1607-4f70-b2e4-680c09cf9e3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706760841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.2706760841
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3683000596
Short name T184
Test name
Test status
Simulation time 32154578 ps
CPU time 0.74 seconds
Started Jan 21 12:22:02 PM PST 24
Finished Jan 21 12:22:04 PM PST 24
Peak memory 202084 kb
Host smart-ebb1e9e3-1265-4bd2-b1d0-0dab28bc39f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683000596 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3683000596
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3283233154
Short name T49
Test name
Test status
Simulation time 294762579 ps
CPU time 2.75 seconds
Started Jan 21 01:02:18 PM PST 24
Finished Jan 21 01:02:27 PM PST 24
Peak memory 202348 kb
Host smart-4dc9a7f9-6fd6-464a-8a4b-0cb4bbb72581
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283233154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3283233154
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3266983508
Short name T72
Test name
Test status
Simulation time 19343631 ps
CPU time 0.7 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:37 PM PST 24
Peak memory 202012 kb
Host smart-7a960a05-0a6d-4bf0-bf99-b97265753bec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266983508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.3266983508
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2898211785
Short name T149
Test name
Test status
Simulation time 135206991 ps
CPU time 1.32 seconds
Started Jan 21 12:58:06 PM PST 24
Finished Jan 21 12:58:09 PM PST 24
Peak memory 202276 kb
Host smart-833e3a20-f971-4f14-bd06-f646def688bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898211785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2898211785
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1389808067
Short name T81
Test name
Test status
Simulation time 24601738 ps
CPU time 0.65 seconds
Started Jan 21 01:10:27 PM PST 24
Finished Jan 21 01:10:34 PM PST 24
Peak memory 202108 kb
Host smart-6777848a-4ca9-4428-93ea-233600249da9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389808067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1389808067
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.413363314
Short name T145
Test name
Test status
Simulation time 15291654 ps
CPU time 0.71 seconds
Started Jan 21 12:24:10 PM PST 24
Finished Jan 21 12:24:12 PM PST 24
Peak memory 200380 kb
Host smart-305e4f75-fa57-4714-894e-04c4b5b6fce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413363314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_csr_rw.413363314
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.688629019
Short name T45
Test name
Test status
Simulation time 63348115 ps
CPU time 2.34 seconds
Started Jan 21 12:46:18 PM PST 24
Finished Jan 21 12:46:22 PM PST 24
Peak memory 200856 kb
Host smart-b6ec3e6b-d81c-4abf-8ccb-3226e8ccd641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688629019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_tl_errors.688629019
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3854201641
Short name T153
Test name
Test status
Simulation time 351489148 ps
CPU time 4.97 seconds
Started Jan 21 12:24:20 PM PST 24
Finished Jan 21 12:24:26 PM PST 24
Peak memory 210408 kb
Host smart-9d0bafd4-1b29-490d-a251-16f2500792c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854201641 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3854201641
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2183339557
Short name T114
Test name
Test status
Simulation time 19975675 ps
CPU time 0.65 seconds
Started Jan 21 12:54:50 PM PST 24
Finished Jan 21 12:54:52 PM PST 24
Peak memory 201128 kb
Host smart-22af3721-1418-4b3e-afb1-bb40d207eec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183339557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.2183339557
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1160271604
Short name T68
Test name
Test status
Simulation time 21321986 ps
CPU time 0.68 seconds
Started Jan 21 12:24:49 PM PST 24
Finished Jan 21 12:24:51 PM PST 24
Peak memory 202072 kb
Host smart-0eb6893d-f198-4c45-ac9a-56d8be40675e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160271604 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.1160271604
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2075963877
Short name T150
Test name
Test status
Simulation time 38784256 ps
CPU time 1.63 seconds
Started Jan 21 12:25:00 PM PST 24
Finished Jan 21 12:25:03 PM PST 24
Peak memory 202340 kb
Host smart-0f2ca169-1f4e-4932-8d93-1d40d13ebf68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075963877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.2075963877
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.557198387
Short name T129
Test name
Test status
Simulation time 1068747306 ps
CPU time 3.17 seconds
Started Jan 21 12:54:54 PM PST 24
Finished Jan 21 12:54:58 PM PST 24
Peak memory 202432 kb
Host smart-2af50cc2-285d-4a84-86da-cdeac7332b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557198387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.sram_ctrl_tl_intg_err.557198387
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2554981315
Short name T148
Test name
Test status
Simulation time 1441444086 ps
CPU time 6.04 seconds
Started Jan 21 01:00:28 PM PST 24
Finished Jan 21 01:00:35 PM PST 24
Peak memory 202448 kb
Host smart-76bbc08f-b6c8-4d24-a9ee-22bd972830e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554981315 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2554981315
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2749140350
Short name T173
Test name
Test status
Simulation time 28724305 ps
CPU time 0.65 seconds
Started Jan 21 12:37:44 PM PST 24
Finished Jan 21 12:37:45 PM PST 24
Peak memory 202084 kb
Host smart-56c3914b-eddb-428a-995a-f53ea868e3a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749140350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2749140350
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.858768291
Short name T164
Test name
Test status
Simulation time 13122881 ps
CPU time 0.64 seconds
Started Jan 21 12:46:43 PM PST 24
Finished Jan 21 12:46:44 PM PST 24
Peak memory 202120 kb
Host smart-50fc4814-03f4-4e33-bc7d-5eb17aa8be90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858768291 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.858768291
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3542892962
Short name T159
Test name
Test status
Simulation time 113629549 ps
CPU time 3.67 seconds
Started Jan 21 12:26:04 PM PST 24
Finished Jan 21 12:26:09 PM PST 24
Peak memory 202372 kb
Host smart-ea8c1ff4-fac8-429f-9629-74dc6d86b980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542892962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.3542892962
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1138917404
Short name T124
Test name
Test status
Simulation time 376483862 ps
CPU time 1.65 seconds
Started Jan 21 12:24:36 PM PST 24
Finished Jan 21 12:24:39 PM PST 24
Peak memory 201348 kb
Host smart-86a846fe-cce9-41dd-afbf-d4e94f1c5109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138917404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.1138917404
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1434883396
Short name T92
Test name
Test status
Simulation time 1426570473 ps
CPU time 12.95 seconds
Started Jan 21 12:22:04 PM PST 24
Finished Jan 21 12:22:18 PM PST 24
Peak memory 210960 kb
Host smart-27b1a831-88e4-48f6-bf0b-b4b4ccc2f8a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434883396 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1434883396
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1813753150
Short name T158
Test name
Test status
Simulation time 25681294 ps
CPU time 0.67 seconds
Started Jan 21 12:38:49 PM PST 24
Finished Jan 21 12:38:50 PM PST 24
Peak memory 202128 kb
Host smart-9d0ebce5-c80c-4985-b790-cab04216cff1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813753150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.1813753150
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1254511536
Short name T187
Test name
Test status
Simulation time 16892758 ps
CPU time 0.69 seconds
Started Jan 21 12:57:58 PM PST 24
Finished Jan 21 12:58:00 PM PST 24
Peak memory 201552 kb
Host smart-112118d1-91c9-4e7d-ae2f-e6f928443f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254511536 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.1254511536
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.875066232
Short name T118
Test name
Test status
Simulation time 70512136 ps
CPU time 2.49 seconds
Started Jan 21 12:37:18 PM PST 24
Finished Jan 21 12:37:21 PM PST 24
Peak memory 202768 kb
Host smart-e8f4ebdc-a054-44a9-82fd-c3f043ccc823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875066232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_tl_errors.875066232
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2759739309
Short name T121
Test name
Test status
Simulation time 288077022 ps
CPU time 2.39 seconds
Started Jan 21 12:29:38 PM PST 24
Finished Jan 21 12:29:47 PM PST 24
Peak memory 202792 kb
Host smart-b29ffc6b-8440-468f-9917-f9112ea57627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759739309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.2759739309
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1554007047
Short name T170
Test name
Test status
Simulation time 704373418 ps
CPU time 5.09 seconds
Started Jan 21 12:24:45 PM PST 24
Finished Jan 21 12:24:52 PM PST 24
Peak memory 210596 kb
Host smart-d4412a5e-94d3-423d-a2a4-063879c6bd50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554007047 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1554007047
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.988167090
Short name T180
Test name
Test status
Simulation time 36251336 ps
CPU time 0.65 seconds
Started Jan 21 01:25:18 PM PST 24
Finished Jan 21 01:25:19 PM PST 24
Peak memory 202172 kb
Host smart-f8754aec-e9aa-4ec7-8e42-d22aa52cf1ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988167090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_csr_rw.988167090
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2712355801
Short name T76
Test name
Test status
Simulation time 14460815 ps
CPU time 0.71 seconds
Started Jan 21 12:21:10 PM PST 24
Finished Jan 21 12:21:18 PM PST 24
Peak memory 202216 kb
Host smart-54755a4e-3d5e-4bb5-a222-a959440947ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712355801 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2712355801
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1683244336
Short name T156
Test name
Test status
Simulation time 24166300 ps
CPU time 1.65 seconds
Started Jan 21 12:56:59 PM PST 24
Finished Jan 21 12:57:06 PM PST 24
Peak memory 202352 kb
Host smart-634d0495-d90b-4a31-bbce-a0b69dc5b152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683244336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1683244336
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3333810670
Short name T102
Test name
Test status
Simulation time 487631313 ps
CPU time 2.4 seconds
Started Jan 21 12:40:52 PM PST 24
Finished Jan 21 12:40:55 PM PST 24
Peak memory 202508 kb
Host smart-b24be3c5-e3cf-47ca-a0a8-145c721971b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333810670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3333810670
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2812647054
Short name T74
Test name
Test status
Simulation time 713694832 ps
CPU time 5.51 seconds
Started Jan 21 12:24:49 PM PST 24
Finished Jan 21 12:24:56 PM PST 24
Peak memory 202136 kb
Host smart-1a16277d-bd02-4753-becf-577b3530493b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812647054 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2812647054
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1093099527
Short name T62
Test name
Test status
Simulation time 41870643 ps
CPU time 0.62 seconds
Started Jan 21 01:15:54 PM PST 24
Finished Jan 21 01:15:56 PM PST 24
Peak memory 202096 kb
Host smart-7743cb7e-1e5b-4729-88c1-8638b3432bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093099527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.1093099527
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.971937744
Short name T112
Test name
Test status
Simulation time 24808360 ps
CPU time 0.79 seconds
Started Jan 21 12:47:09 PM PST 24
Finished Jan 21 12:47:10 PM PST 24
Peak memory 202176 kb
Host smart-d55abb95-dd0f-428b-a796-173c2578fb1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971937744 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.971937744
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2947122682
Short name T40
Test name
Test status
Simulation time 699781479 ps
CPU time 1.94 seconds
Started Jan 21 12:50:24 PM PST 24
Finished Jan 21 12:50:26 PM PST 24
Peak memory 202336 kb
Host smart-504c2c58-76bb-40af-a0dd-0be1d4e23e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947122682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.2947122682
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3740717414
Short name T171
Test name
Test status
Simulation time 120843744 ps
CPU time 1.45 seconds
Started Jan 21 12:22:25 PM PST 24
Finished Jan 21 12:22:27 PM PST 24
Peak memory 202312 kb
Host smart-659c7a88-b1e3-46b7-812f-2e8a7ca5940e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740717414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3740717414
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1252102961
Short name T29
Test name
Test status
Simulation time 366432938 ps
CPU time 5.47 seconds
Started Jan 21 12:22:42 PM PST 24
Finished Jan 21 12:22:49 PM PST 24
Peak memory 202340 kb
Host smart-18fbc711-d409-46f0-99fc-0711e2e62f5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252102961 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1252102961
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1324258261
Short name T71
Test name
Test status
Simulation time 15023434 ps
CPU time 0.64 seconds
Started Jan 21 12:22:42 PM PST 24
Finished Jan 21 12:22:44 PM PST 24
Peak memory 202060 kb
Host smart-aa8572ac-0484-44b5-9e76-b6d98a89ae5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324258261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.1324258261
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3947633244
Short name T106
Test name
Test status
Simulation time 27043395 ps
CPU time 0.7 seconds
Started Jan 21 01:04:03 PM PST 24
Finished Jan 21 01:04:05 PM PST 24
Peak memory 202196 kb
Host smart-1952e7b9-a3c5-40fc-884a-3e6b06c4e30e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947633244 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.3947633244
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1872153177
Short name T177
Test name
Test status
Simulation time 146880235 ps
CPU time 4.46 seconds
Started Jan 21 12:49:36 PM PST 24
Finished Jan 21 12:49:41 PM PST 24
Peak memory 202436 kb
Host smart-47988b7d-62b8-4fc5-b3a6-8cfeff116ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872153177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1872153177
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.730676658
Short name T75
Test name
Test status
Simulation time 470329913 ps
CPU time 2.07 seconds
Started Jan 21 01:02:15 PM PST 24
Finished Jan 21 01:02:19 PM PST 24
Peak memory 202400 kb
Host smart-a3df9229-127e-41fb-ac82-ff825850fc32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730676658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.sram_ctrl_tl_intg_err.730676658
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2066786160
Short name T186
Test name
Test status
Simulation time 558287863 ps
CPU time 12.27 seconds
Started Jan 21 01:14:26 PM PST 24
Finished Jan 21 01:14:39 PM PST 24
Peak memory 210672 kb
Host smart-92b64fef-c656-4ce5-a4c7-018353d8ab23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066786160 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2066786160
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3057880846
Short name T60
Test name
Test status
Simulation time 13572547 ps
CPU time 0.64 seconds
Started Jan 21 01:08:51 PM PST 24
Finished Jan 21 01:08:52 PM PST 24
Peak memory 202212 kb
Host smart-22be8d83-c4cd-48f5-be0b-831d03e72e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057880846 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.3057880846
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2256622146
Short name T168
Test name
Test status
Simulation time 16313701 ps
CPU time 0.69 seconds
Started Jan 21 12:33:37 PM PST 24
Finished Jan 21 12:33:38 PM PST 24
Peak memory 202216 kb
Host smart-c9a32ca7-8a40-48d5-a195-21d11060f0f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256622146 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2256622146
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.499516544
Short name T77
Test name
Test status
Simulation time 120772179 ps
CPU time 2.1 seconds
Started Jan 21 12:33:48 PM PST 24
Finished Jan 21 12:33:51 PM PST 24
Peak memory 202444 kb
Host smart-cc4770b9-9d00-463a-94c3-7c38df7b0e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499516544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_tl_errors.499516544
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3022895254
Short name T126
Test name
Test status
Simulation time 333144292 ps
CPU time 1.54 seconds
Started Jan 21 12:28:50 PM PST 24
Finished Jan 21 12:28:52 PM PST 24
Peak memory 202400 kb
Host smart-574afb14-88a1-4e4f-a58f-76b905219d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022895254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.3022895254
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.769863691
Short name T146
Test name
Test status
Simulation time 2316918455 ps
CPU time 6.14 seconds
Started Jan 21 12:22:09 PM PST 24
Finished Jan 21 12:22:19 PM PST 24
Peak memory 210724 kb
Host smart-3c42df8d-5ca5-4acb-9226-80df4f854f0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769863691 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.769863691
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3709366448
Short name T61
Test name
Test status
Simulation time 15574575 ps
CPU time 0.67 seconds
Started Jan 21 12:44:59 PM PST 24
Finished Jan 21 12:45:01 PM PST 24
Peak memory 201412 kb
Host smart-1f1221a6-63d0-43fe-95a5-9ea1d3e331c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709366448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.3709366448
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1104537007
Short name T99
Test name
Test status
Simulation time 63883034 ps
CPU time 0.75 seconds
Started Jan 21 12:22:20 PM PST 24
Finished Jan 21 12:22:22 PM PST 24
Peak memory 201880 kb
Host smart-cac4cccf-5828-410d-8a6c-c9587c40bf8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104537007 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1104537007
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1848394067
Short name T95
Test name
Test status
Simulation time 614414698 ps
CPU time 4.48 seconds
Started Jan 21 12:22:25 PM PST 24
Finished Jan 21 12:22:30 PM PST 24
Peak memory 202284 kb
Host smart-175b785e-6559-4438-bd58-87d014ac9d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848394067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.1848394067
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.609099651
Short name T128
Test name
Test status
Simulation time 133040478 ps
CPU time 1.3 seconds
Started Jan 21 12:33:01 PM PST 24
Finished Jan 21 12:33:03 PM PST 24
Peak memory 202436 kb
Host smart-f1d4c0b1-638f-46f7-b477-ba9b0c04e102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609099651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.sram_ctrl_tl_intg_err.609099651
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.902233005
Short name T46
Test name
Test status
Simulation time 966192445 ps
CPU time 12.49 seconds
Started Jan 21 12:34:06 PM PST 24
Finished Jan 21 12:34:19 PM PST 24
Peak memory 210680 kb
Host smart-f7829160-bff7-4dfc-9df5-f2d0092a6c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902233005 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.902233005
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.156189934
Short name T107
Test name
Test status
Simulation time 13046093 ps
CPU time 0.65 seconds
Started Jan 21 12:20:28 PM PST 24
Finished Jan 21 12:20:29 PM PST 24
Peak memory 201392 kb
Host smart-e8b1d3a5-150d-48bc-b434-fed3575dfe58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156189934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.sram_ctrl_csr_rw.156189934
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.50857743
Short name T185
Test name
Test status
Simulation time 25239711 ps
CPU time 0.74 seconds
Started Jan 21 12:20:28 PM PST 24
Finished Jan 21 12:20:29 PM PST 24
Peak memory 202228 kb
Host smart-830e611f-2766-4762-b2a1-5967489d5fe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50857743 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.50857743
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.747478456
Short name T41
Test name
Test status
Simulation time 565129139 ps
CPU time 5.73 seconds
Started Jan 21 12:22:41 PM PST 24
Finished Jan 21 12:22:47 PM PST 24
Peak memory 210948 kb
Host smart-24187c3e-4188-4327-8552-4ca65ac0dde3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747478456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.747478456
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3956952595
Short name T122
Test name
Test status
Simulation time 196058934 ps
CPU time 1.53 seconds
Started Jan 21 12:24:18 PM PST 24
Finished Jan 21 12:24:21 PM PST 24
Peak memory 200668 kb
Host smart-3a70d60d-32c0-4309-954f-90cc619c448e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956952595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.3956952595
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3882789214
Short name T152
Test name
Test status
Simulation time 1815304224 ps
CPU time 13.67 seconds
Started Jan 21 12:20:55 PM PST 24
Finished Jan 21 12:21:09 PM PST 24
Peak memory 210684 kb
Host smart-cd26d369-2cd5-481b-ade7-d7db62ba5325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882789214 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3882789214
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.882938742
Short name T70
Test name
Test status
Simulation time 19188829 ps
CPU time 0.64 seconds
Started Jan 21 12:58:03 PM PST 24
Finished Jan 21 12:58:04 PM PST 24
Peak memory 201176 kb
Host smart-92ff81b5-ae67-4db2-b3f7-2a8525d3628f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882938742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 19.sram_ctrl_csr_rw.882938742
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1532686117
Short name T165
Test name
Test status
Simulation time 26359048 ps
CPU time 0.69 seconds
Started Jan 21 12:21:00 PM PST 24
Finished Jan 21 12:21:03 PM PST 24
Peak memory 201832 kb
Host smart-5aeec6e8-274d-4783-93c2-19cf887b9eea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532686117 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1532686117
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4244203127
Short name T44
Test name
Test status
Simulation time 589451203 ps
CPU time 4.53 seconds
Started Jan 21 01:03:51 PM PST 24
Finished Jan 21 01:03:56 PM PST 24
Peak memory 202472 kb
Host smart-a2c43bf3-addb-408b-9122-911e6ee35d83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244203127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.4244203127
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4128687502
Short name T120
Test name
Test status
Simulation time 109859994 ps
CPU time 1.48 seconds
Started Jan 21 01:47:37 PM PST 24
Finished Jan 21 01:47:40 PM PST 24
Peak memory 202476 kb
Host smart-ed28b83d-180f-4558-aed6-506f3d67b51b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128687502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.4128687502
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2578698
Short name T80
Test name
Test status
Simulation time 95777756 ps
CPU time 0.69 seconds
Started Jan 21 12:24:34 PM PST 24
Finished Jan 21 12:24:36 PM PST 24
Peak memory 201932 kb
Host smart-c205e5e0-3458-42d2-a24e-89b1e76dd6bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_csr_aliasing.2578698
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3944879236
Short name T181
Test name
Test status
Simulation time 90935193 ps
CPU time 1.47 seconds
Started Jan 21 12:24:10 PM PST 24
Finished Jan 21 12:24:12 PM PST 24
Peak memory 200700 kb
Host smart-b0d2112d-e51c-415e-a01f-fd3366d75de1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944879236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.3944879236
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2986847187
Short name T161
Test name
Test status
Simulation time 18768955 ps
CPU time 0.68 seconds
Started Jan 21 12:56:57 PM PST 24
Finished Jan 21 12:57:00 PM PST 24
Peak memory 201268 kb
Host smart-4e3c0df4-175d-4a8a-b850-8abfca2bc92e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986847187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2986847187
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2963324114
Short name T98
Test name
Test status
Simulation time 370946842 ps
CPU time 4.59 seconds
Started Jan 21 01:16:39 PM PST 24
Finished Jan 21 01:16:44 PM PST 24
Peak memory 202360 kb
Host smart-ba1f34b9-28f0-4171-8e39-852b87a284e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963324114 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2963324114
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3291311205
Short name T83
Test name
Test status
Simulation time 39848533 ps
CPU time 0.7 seconds
Started Jan 21 12:49:31 PM PST 24
Finished Jan 21 12:49:33 PM PST 24
Peak memory 201492 kb
Host smart-7be31894-a832-4a8b-bc6c-78b9ebbd429e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291311205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3291311205
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1214068661
Short name T108
Test name
Test status
Simulation time 42704396 ps
CPU time 0.69 seconds
Started Jan 21 12:56:14 PM PST 24
Finished Jan 21 12:56:20 PM PST 24
Peak memory 202152 kb
Host smart-db42047d-ee31-4bde-b86f-29ca14722f57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214068661 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.1214068661
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1431601450
Short name T93
Test name
Test status
Simulation time 302723615 ps
CPU time 4.97 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:41 PM PST 24
Peak memory 202272 kb
Host smart-7147290f-174b-4403-ac9d-4b06269f8c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431601450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.1431601450
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.335703563
Short name T94
Test name
Test status
Simulation time 220543236 ps
CPU time 2.15 seconds
Started Jan 21 12:48:07 PM PST 24
Finished Jan 21 12:48:14 PM PST 24
Peak memory 202224 kb
Host smart-2b4b8670-0230-4980-b7bd-878a8bab5897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335703563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.sram_ctrl_tl_intg_err.335703563
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1264330730
Short name T176
Test name
Test status
Simulation time 47194210 ps
CPU time 0.7 seconds
Started Jan 21 01:42:10 PM PST 24
Finished Jan 21 01:42:12 PM PST 24
Peak memory 202080 kb
Host smart-7cba3292-e01e-47eb-abf9-90456e5f700d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264330730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.1264330730
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.110469651
Short name T179
Test name
Test status
Simulation time 48012692 ps
CPU time 1.72 seconds
Started Jan 21 12:24:40 PM PST 24
Finished Jan 21 12:24:43 PM PST 24
Peak memory 201260 kb
Host smart-5d17cca8-ca86-4d86-a41f-b334fc97ea4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110469651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_bit_bash.110469651
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1112684978
Short name T58
Test name
Test status
Simulation time 16030659 ps
CPU time 0.65 seconds
Started Jan 21 12:52:54 PM PST 24
Finished Jan 21 12:52:56 PM PST 24
Peak memory 202132 kb
Host smart-037d7dae-6185-4e01-bed0-482cd85c75bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112684978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.1112684978
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2816209036
Short name T138
Test name
Test status
Simulation time 725047657 ps
CPU time 12.4 seconds
Started Jan 21 12:24:40 PM PST 24
Finished Jan 21 12:24:54 PM PST 24
Peak memory 210200 kb
Host smart-fc932c20-57c6-4f6d-ad27-4ae350eb8574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816209036 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2816209036
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3083422666
Short name T174
Test name
Test status
Simulation time 15121559 ps
CPU time 0.66 seconds
Started Jan 21 12:25:01 PM PST 24
Finished Jan 21 12:25:04 PM PST 24
Peak memory 200424 kb
Host smart-69e5f52e-9873-4c54-bdbf-0c040e93ad2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083422666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.3083422666
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1402882526
Short name T100
Test name
Test status
Simulation time 58927567 ps
CPU time 0.7 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:37 PM PST 24
Peak memory 202016 kb
Host smart-95421d0f-a905-4eb4-9677-c0791e64d526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402882526 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1402882526
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1087127480
Short name T48
Test name
Test status
Simulation time 74588356 ps
CPU time 4.04 seconds
Started Jan 21 01:11:42 PM PST 24
Finished Jan 21 01:11:46 PM PST 24
Peak memory 202384 kb
Host smart-2d49c12a-e528-4a88-83ea-6d2eb179ce5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087127480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.1087127480
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.208638463
Short name T43
Test name
Test status
Simulation time 93253075 ps
CPU time 1.36 seconds
Started Jan 21 12:25:01 PM PST 24
Finished Jan 21 12:25:04 PM PST 24
Peak memory 201476 kb
Host smart-3bd5f69a-42ae-48db-b232-7a587bb9c9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208638463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.sram_ctrl_tl_intg_err.208638463
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3630034950
Short name T169
Test name
Test status
Simulation time 17121591 ps
CPU time 0.67 seconds
Started Jan 21 12:24:49 PM PST 24
Finished Jan 21 12:24:51 PM PST 24
Peak memory 202004 kb
Host smart-d48c6221-d40d-48ca-8112-e08888a144ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630034950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.3630034950
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4232868875
Short name T160
Test name
Test status
Simulation time 24005295 ps
CPU time 0.69 seconds
Started Jan 21 01:04:15 PM PST 24
Finished Jan 21 01:04:16 PM PST 24
Peak memory 202472 kb
Host smart-128dfb11-ee5d-4f90-924d-afa72dafd227
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232868875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.4232868875
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3092250994
Short name T73
Test name
Test status
Simulation time 694469451 ps
CPU time 5.49 seconds
Started Jan 21 12:51:48 PM PST 24
Finished Jan 21 12:51:58 PM PST 24
Peak memory 202312 kb
Host smart-c6667054-eb03-410b-ace4-ae5cfd5f848f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092250994 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3092250994
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1547874286
Short name T69
Test name
Test status
Simulation time 13808942 ps
CPU time 0.68 seconds
Started Jan 21 12:41:15 PM PST 24
Finished Jan 21 12:41:16 PM PST 24
Peak memory 201484 kb
Host smart-3b7a1d41-b45a-4c22-bbc2-102d4044bc9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547874286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.1547874286
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2735554823
Short name T175
Test name
Test status
Simulation time 44834489 ps
CPU time 0.68 seconds
Started Jan 21 12:57:59 PM PST 24
Finished Jan 21 12:58:01 PM PST 24
Peak memory 202100 kb
Host smart-97f8c9f3-34f0-4393-9c3f-1f5bc859c822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735554823 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2735554823
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3398377636
Short name T166
Test name
Test status
Simulation time 138778869 ps
CPU time 4.63 seconds
Started Jan 21 12:24:24 PM PST 24
Finished Jan 21 12:24:31 PM PST 24
Peak memory 201492 kb
Host smart-eca6c421-1ce6-42c3-9eee-9d2e3d58657a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398377636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.3398377636
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3189877553
Short name T117
Test name
Test status
Simulation time 114491519 ps
CPU time 1.49 seconds
Started Jan 21 12:25:01 PM PST 24
Finished Jan 21 12:25:05 PM PST 24
Peak memory 202236 kb
Host smart-4b64dc12-b4d5-4a52-961e-558aa39a8d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189877553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.3189877553
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4175010336
Short name T163
Test name
Test status
Simulation time 3424510516 ps
CPU time 4.78 seconds
Started Jan 21 12:46:50 PM PST 24
Finished Jan 21 12:46:56 PM PST 24
Peak memory 202432 kb
Host smart-d7d76618-881b-4530-a61a-68039e75021d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175010336 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.4175010336
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1378292781
Short name T147
Test name
Test status
Simulation time 48956204 ps
CPU time 0.65 seconds
Started Jan 21 12:44:33 PM PST 24
Finished Jan 21 12:44:34 PM PST 24
Peak memory 201384 kb
Host smart-16924dd7-c5fa-4d95-8137-158135e0d89a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378292781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.1378292781
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1637736118
Short name T96
Test name
Test status
Simulation time 36912488 ps
CPU time 0.8 seconds
Started Jan 21 12:55:45 PM PST 24
Finished Jan 21 12:55:47 PM PST 24
Peak memory 202128 kb
Host smart-faba1c79-3b00-4e83-99c4-55ef159fb5a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637736118 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1637736118
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1448204711
Short name T154
Test name
Test status
Simulation time 128605609 ps
CPU time 4.28 seconds
Started Jan 21 12:56:24 PM PST 24
Finished Jan 21 12:56:30 PM PST 24
Peak memory 202388 kb
Host smart-b0d68921-0ed2-4efd-81b8-25ddd2b9d978
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448204711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.1448204711
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3655759397
Short name T157
Test name
Test status
Simulation time 356160642 ps
CPU time 11.58 seconds
Started Jan 21 12:24:49 PM PST 24
Finished Jan 21 12:25:01 PM PST 24
Peak memory 202328 kb
Host smart-b541241a-00ba-4d02-bd9d-c0c7bbb5f7cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655759397 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3655759397
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3638467201
Short name T63
Test name
Test status
Simulation time 19077907 ps
CPU time 0.64 seconds
Started Jan 21 12:21:25 PM PST 24
Finished Jan 21 12:21:27 PM PST 24
Peak memory 202240 kb
Host smart-3cb89eb1-f5bf-49d1-87bc-23f1e422f81b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638467201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3638467201
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1405294331
Short name T111
Test name
Test status
Simulation time 53604278 ps
CPU time 0.7 seconds
Started Jan 21 01:00:30 PM PST 24
Finished Jan 21 01:00:32 PM PST 24
Peak memory 202100 kb
Host smart-30136508-51c9-45ed-b901-e970de52ee24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405294331 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.1405294331
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2164932261
Short name T167
Test name
Test status
Simulation time 105365564 ps
CPU time 2.31 seconds
Started Jan 21 12:24:26 PM PST 24
Finished Jan 21 12:24:30 PM PST 24
Peak memory 201444 kb
Host smart-9f48b48e-e782-4403-a7e8-c5e576037f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164932261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.sram_ctrl_tl_errors.2164932261
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4023372574
Short name T119
Test name
Test status
Simulation time 2026685538 ps
CPU time 2.67 seconds
Started Jan 21 12:24:49 PM PST 24
Finished Jan 21 12:24:53 PM PST 24
Peak memory 202300 kb
Host smart-bb9f8345-888b-4f8a-a5bc-d8d6017d7e54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023372574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.4023372574
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.173351865
Short name T155
Test name
Test status
Simulation time 1434827158 ps
CPU time 5.93 seconds
Started Jan 21 12:24:45 PM PST 24
Finished Jan 21 12:24:52 PM PST 24
Peak memory 210600 kb
Host smart-f4b49501-241e-4e9f-a0de-51640c84f79c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173351865 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.173351865
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2214675666
Short name T172
Test name
Test status
Simulation time 28893038 ps
CPU time 0.64 seconds
Started Jan 21 12:43:00 PM PST 24
Finished Jan 21 12:43:02 PM PST 24
Peak memory 202172 kb
Host smart-7dd2c716-febd-4431-a06b-8352160d4226
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214675666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.2214675666
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3681491350
Short name T110
Test name
Test status
Simulation time 15477239 ps
CPU time 0.75 seconds
Started Jan 21 12:22:25 PM PST 24
Finished Jan 21 12:22:26 PM PST 24
Peak memory 202072 kb
Host smart-e5a4c745-e37f-45c9-9b58-88cd47b4e3b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681491350 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3681491350
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3899728506
Short name T182
Test name
Test status
Simulation time 136414350 ps
CPU time 2.32 seconds
Started Jan 21 12:24:49 PM PST 24
Finished Jan 21 12:24:53 PM PST 24
Peak memory 202308 kb
Host smart-ca3e1b4b-2a11-473a-a9bf-e8fa60a6114c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899728506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.3899728506
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.500950212
Short name T127
Test name
Test status
Simulation time 154186905 ps
CPU time 1.36 seconds
Started Jan 21 12:20:01 PM PST 24
Finished Jan 21 12:20:03 PM PST 24
Peak memory 202460 kb
Host smart-4e24371b-fcec-40ac-94a4-76b090c79fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500950212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.sram_ctrl_tl_intg_err.500950212
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.858087807
Short name T183
Test name
Test status
Simulation time 1513601629 ps
CPU time 6.49 seconds
Started Jan 21 01:20:38 PM PST 24
Finished Jan 21 01:20:46 PM PST 24
Peak memory 210756 kb
Host smart-e17114e4-39a1-4c88-821c-331497fb378d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858087807 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.858087807
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1276991433
Short name T59
Test name
Test status
Simulation time 14557470 ps
CPU time 0.65 seconds
Started Jan 21 01:04:38 PM PST 24
Finished Jan 21 01:04:39 PM PST 24
Peak memory 201440 kb
Host smart-afe992f8-0e17-411b-96e0-ce32be0184bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276991433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.1276991433
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.151150089
Short name T105
Test name
Test status
Simulation time 18125913 ps
CPU time 0.73 seconds
Started Jan 21 01:40:25 PM PST 24
Finished Jan 21 01:40:27 PM PST 24
Peak memory 202216 kb
Host smart-976f47a2-5fc5-4f13-88b1-f736df24a278
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151150089 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.151150089
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3477469937
Short name T162
Test name
Test status
Simulation time 34966748 ps
CPU time 3.13 seconds
Started Jan 21 12:31:11 PM PST 24
Finished Jan 21 12:31:14 PM PST 24
Peak memory 202508 kb
Host smart-dc9a0d67-c1de-4eb4-ba53-70a6be8d497c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477469937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.3477469937
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3808108855
Short name T123
Test name
Test status
Simulation time 186143438 ps
CPU time 2.41 seconds
Started Jan 21 12:21:05 PM PST 24
Finished Jan 21 12:21:10 PM PST 24
Peak memory 202476 kb
Host smart-23fd0f74-1997-4345-b578-18ecb998ce92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808108855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.3808108855
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.707767236
Short name T56
Test name
Test status
Simulation time 1404458224 ps
CPU time 4.79 seconds
Started Jan 21 12:25:00 PM PST 24
Finished Jan 21 12:25:06 PM PST 24
Peak memory 202340 kb
Host smart-295fbc3f-6f66-4591-8c4b-9569dcaf745c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707767236 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.707767236
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1629772811
Short name T89
Test name
Test status
Simulation time 11709037 ps
CPU time 0.65 seconds
Started Jan 21 12:23:01 PM PST 24
Finished Jan 21 12:23:02 PM PST 24
Peak memory 202108 kb
Host smart-eb94c45f-f813-464e-9681-11f0bc30d99f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629772811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1629772811
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2210043354
Short name T97
Test name
Test status
Simulation time 99738414 ps
CPU time 0.82 seconds
Started Jan 21 12:24:19 PM PST 24
Finished Jan 21 12:24:21 PM PST 24
Peak memory 200952 kb
Host smart-47f32ad5-8679-45e9-8be6-e6d0d9eb0c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210043354 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2210043354
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1995976264
Short name T178
Test name
Test status
Simulation time 153231214 ps
CPU time 3.67 seconds
Started Jan 21 12:49:54 PM PST 24
Finished Jan 21 12:49:58 PM PST 24
Peak memory 202336 kb
Host smart-cfb34080-414d-4494-8fc5-70a8de16e6be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995976264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.1995976264
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3512378206
Short name T47
Test name
Test status
Simulation time 238100337 ps
CPU time 1.55 seconds
Started Jan 21 12:22:09 PM PST 24
Finished Jan 21 12:22:14 PM PST 24
Peak memory 202336 kb
Host smart-64d05fe6-f763-46ae-a77f-37cee84f7cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512378206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.3512378206
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1249772270
Short name T560
Test name
Test status
Simulation time 9626625397 ps
CPU time 1115.84 seconds
Started Jan 21 12:31:56 PM PST 24
Finished Jan 21 12:50:53 PM PST 24
Peak memory 373884 kb
Host smart-26b42216-9a26-48e0-a9fa-071e1748cfb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249772270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1249772270
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.4126021431
Short name T422
Test name
Test status
Simulation time 224958041781 ps
CPU time 994.51 seconds
Started Jan 21 12:32:01 PM PST 24
Finished Jan 21 12:48:56 PM PST 24
Peak memory 202276 kb
Host smart-5909a24c-d01e-4e2b-968c-1aad67178ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126021431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
4126021431
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.1107291212
Short name T266
Test name
Test status
Simulation time 9250900656 ps
CPU time 113.6 seconds
Started Jan 21 12:31:58 PM PST 24
Finished Jan 21 12:34:13 PM PST 24
Peak memory 210316 kb
Host smart-e7ac2228-a272-4186-bacd-ddfc040c6e46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107291212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.1107291212
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.1024909768
Short name T681
Test name
Test status
Simulation time 3638666978 ps
CPU time 129.19 seconds
Started Jan 21 12:31:56 PM PST 24
Finished Jan 21 12:34:27 PM PST 24
Peak memory 365108 kb
Host smart-e14f51ae-4cf4-42ac-97c1-fe0c71496a53
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024909768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.1024909768
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1107508728
Short name T313
Test name
Test status
Simulation time 3459849852 ps
CPU time 75.71 seconds
Started Jan 21 12:31:59 PM PST 24
Finished Jan 21 12:33:36 PM PST 24
Peak memory 211172 kb
Host smart-4b16bc00-93f8-4664-b95f-86dd807ec29a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107508728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.1107508728
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.4198459778
Short name T931
Test name
Test status
Simulation time 2019038202 ps
CPU time 117.92 seconds
Started Jan 21 12:31:57 PM PST 24
Finished Jan 21 12:34:16 PM PST 24
Peak memory 202064 kb
Host smart-c1872bde-9142-43fd-b3c7-2eabca407da1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198459778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.4198459778
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.4201722691
Short name T529
Test name
Test status
Simulation time 933559225 ps
CPU time 42 seconds
Started Jan 21 12:31:51 PM PST 24
Finished Jan 21 12:32:53 PM PST 24
Peak memory 202104 kb
Host smart-0e441f8b-9382-449b-b8ed-70e5706b9832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201722691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.4201722691
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.589581196
Short name T585
Test name
Test status
Simulation time 2337086123 ps
CPU time 22.5 seconds
Started Jan 21 12:31:51 PM PST 24
Finished Jan 21 12:32:34 PM PST 24
Peak memory 265340 kb
Host smart-8b4d1c8b-19af-48df-a2c7-df03a4fe5754
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589581196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr
am_ctrl_partial_access.589581196
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2355126112
Short name T832
Test name
Test status
Simulation time 47988041328 ps
CPU time 289.21 seconds
Started Jan 21 12:31:56 PM PST 24
Finished Jan 21 12:37:07 PM PST 24
Peak memory 202044 kb
Host smart-3130586f-ebe5-41c0-9bc0-8757e3d4e99b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355126112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.2355126112
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.2535767013
Short name T733
Test name
Test status
Simulation time 1345750320 ps
CPU time 5.55 seconds
Started Jan 21 12:31:56 PM PST 24
Finished Jan 21 12:32:23 PM PST 24
Peak memory 202348 kb
Host smart-cc74cb8d-a6e6-4195-9118-47c709e49398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535767013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2535767013
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.2095959699
Short name T423
Test name
Test status
Simulation time 19873069967 ps
CPU time 1370.45 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:55:13 PM PST 24
Peak memory 380228 kb
Host smart-02ffd3ed-1d4f-4f88-8d6c-5e707a66dbdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095959699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2095959699
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.2894688681
Short name T34
Test name
Test status
Simulation time 974875414 ps
CPU time 3.23 seconds
Started Jan 21 12:31:58 PM PST 24
Finished Jan 21 12:32:22 PM PST 24
Peak memory 220620 kb
Host smart-51befa88-fedc-4cd9-a287-deae3601be7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894688681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.2894688681
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2357433734
Short name T605
Test name
Test status
Simulation time 641443998 ps
CPU time 19.09 seconds
Started Jan 21 12:31:56 PM PST 24
Finished Jan 21 12:32:37 PM PST 24
Peak memory 261216 kb
Host smart-42df3cbe-321f-4d85-8410-89cc23d92cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357433734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2357433734
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1989038999
Short name T419
Test name
Test status
Simulation time 4835830294 ps
CPU time 4971.08 seconds
Started Jan 21 12:31:59 PM PST 24
Finished Jan 21 01:55:12 PM PST 24
Peak memory 640960 kb
Host smart-e4816c2b-4968-4846-b4fc-c40579f895a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1989038999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1989038999
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.132414809
Short name T919
Test name
Test status
Simulation time 3247516248 ps
CPU time 226.75 seconds
Started Jan 21 12:31:51 PM PST 24
Finished Jan 21 12:35:57 PM PST 24
Peak memory 202116 kb
Host smart-92e4388b-9a86-46db-8c02-1492aa2af96d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132414809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_stress_pipeline.132414809
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.389549657
Short name T950
Test name
Test status
Simulation time 1404006234 ps
CPU time 46.81 seconds
Started Jan 21 12:32:00 PM PST 24
Finished Jan 21 12:33:07 PM PST 24
Peak memory 283940 kb
Host smart-dadce0ea-0ef2-42da-9741-cb927c8f9748
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389549657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_throughput_w_partial_write.389549657
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.4026786472
Short name T876
Test name
Test status
Simulation time 8855573114 ps
CPU time 467.08 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:40:10 PM PST 24
Peak memory 359484 kb
Host smart-9eb7dd86-da81-4b15-a12d-57777b1f08cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026786472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.4026786472
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.4096130975
Short name T508
Test name
Test status
Simulation time 13703335 ps
CPU time 0.64 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:32:24 PM PST 24
Peak memory 201464 kb
Host smart-7bc6a193-7cec-411b-9b3b-431217b334d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096130975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.4096130975
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.4145209616
Short name T637
Test name
Test status
Simulation time 30484007556 ps
CPU time 1965.33 seconds
Started Jan 21 12:31:55 PM PST 24
Finished Jan 21 01:05:03 PM PST 24
Peak memory 202276 kb
Host smart-86a2b75d-3b81-4ff6-be26-127dd7eb38ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145209616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
4145209616
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.2757415361
Short name T316
Test name
Test status
Simulation time 2999298480 ps
CPU time 87.86 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 12:33:51 PM PST 24
Peak memory 343148 kb
Host smart-0e1b6dff-324f-4506-bea8-1f1d7a08372d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757415361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.2757415361
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3563515054
Short name T88
Test name
Test status
Simulation time 17490135754 ps
CPU time 152.14 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:34:55 PM PST 24
Peak memory 210128 kb
Host smart-b9284d98-f483-476f-bfbd-974aa19bebd3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563515054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.3563515054
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.2606438330
Short name T242
Test name
Test status
Simulation time 13794139926 ps
CPU time 280.56 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:37:04 PM PST 24
Peak memory 201888 kb
Host smart-38a0d4d5-d7db-48d0-a37b-37ce5c51505a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606438330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.2606438330
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.867710262
Short name T780
Test name
Test status
Simulation time 5968320707 ps
CPU time 702.94 seconds
Started Jan 21 12:31:55 PM PST 24
Finished Jan 21 12:44:00 PM PST 24
Peak memory 375992 kb
Host smart-8f60a681-54cb-437d-a0c2-d7c720cde70e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867710262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multipl
e_keys.867710262
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2433864741
Short name T458
Test name
Test status
Simulation time 439971745 ps
CPU time 35.09 seconds
Started Jan 21 12:31:55 PM PST 24
Finished Jan 21 12:32:52 PM PST 24
Peak memory 280756 kb
Host smart-81a426f6-77e2-4506-b3e2-f43b7a4e5c71
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433864741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2433864741
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2087583729
Short name T845
Test name
Test status
Simulation time 76823985281 ps
CPU time 495.64 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 12:40:39 PM PST 24
Peak memory 202076 kb
Host smart-715366b0-42e2-4de6-8dcb-ad488a2db599
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087583729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.sram_ctrl_partial_access_b2b.2087583729
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.649657931
Short name T626
Test name
Test status
Simulation time 755301462 ps
CPU time 5.47 seconds
Started Jan 21 12:31:56 PM PST 24
Finished Jan 21 12:32:23 PM PST 24
Peak memory 202200 kb
Host smart-0c3076a4-81af-4db1-b0d5-b714672e9ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649657931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.649657931
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.502563183
Short name T230
Test name
Test status
Simulation time 6138856866 ps
CPU time 1185.88 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:52:09 PM PST 24
Peak memory 377772 kb
Host smart-e4eabbb9-8ac8-40e3-bcbb-999851f25355
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502563183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.502563183
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.2670340337
Short name T21
Test name
Test status
Simulation time 1249652588 ps
CPU time 2.8 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 12:32:26 PM PST 24
Peak memory 219716 kb
Host smart-690f2250-e875-49a9-a025-ede1db011ce7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670340337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.2670340337
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.498695313
Short name T813
Test name
Test status
Simulation time 7357519573 ps
CPU time 31.61 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 12:32:54 PM PST 24
Peak memory 201852 kb
Host smart-4dda5fc5-ec64-4051-9224-16177c7580f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498695313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.498695313
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.3349164088
Short name T227
Test name
Test status
Simulation time 87241785896 ps
CPU time 2929.94 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 01:21:13 PM PST 24
Peak memory 374948 kb
Host smart-f2d8ea45-c7f2-4fea-9c77-451318fd6aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349164088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.3349164088
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4135210334
Short name T260
Test name
Test status
Simulation time 714944877 ps
CPU time 3538.32 seconds
Started Jan 21 12:31:56 PM PST 24
Finished Jan 21 01:31:17 PM PST 24
Peak memory 413044 kb
Host smart-67422841-1615-4486-becb-fef1b4767858
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4135210334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.4135210334
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2095211555
Short name T344
Test name
Test status
Simulation time 13044361773 ps
CPU time 473.05 seconds
Started Jan 21 12:32:00 PM PST 24
Finished Jan 21 12:40:14 PM PST 24
Peak memory 202132 kb
Host smart-3a22e53a-8f89-468d-8954-91ae274948ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095211555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2095211555
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.426987414
Short name T530
Test name
Test status
Simulation time 708767522 ps
CPU time 28.84 seconds
Started Jan 21 12:31:55 PM PST 24
Finished Jan 21 12:32:46 PM PST 24
Peak memory 223236 kb
Host smart-a524e846-8f8e-4979-b4c2-3d45d83cd4d6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426987414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.426987414
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2688268373
Short name T879
Test name
Test status
Simulation time 19848572160 ps
CPU time 1020.99 seconds
Started Jan 21 12:33:37 PM PST 24
Finished Jan 21 12:50:39 PM PST 24
Peak memory 377492 kb
Host smart-64f04d3a-2097-4646-b8f4-4ebc8dffdd3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688268373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.2688268373
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.3257950253
Short name T324
Test name
Test status
Simulation time 17801494 ps
CPU time 0.64 seconds
Started Jan 21 12:33:52 PM PST 24
Finished Jan 21 12:33:54 PM PST 24
Peak memory 201364 kb
Host smart-2488cc4a-03c0-4e49-890b-2583ceb49cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257950253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.3257950253
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.1520105094
Short name T819
Test name
Test status
Simulation time 32799170997 ps
CPU time 1121.78 seconds
Started Jan 21 12:33:33 PM PST 24
Finished Jan 21 12:52:15 PM PST 24
Peak memory 202232 kb
Host smart-44fae56a-fafb-4ea0-9e07-2213ead62388
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520105094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.1520105094
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3238010865
Short name T670
Test name
Test status
Simulation time 795538882 ps
CPU time 144.22 seconds
Started Jan 21 12:33:37 PM PST 24
Finished Jan 21 12:36:02 PM PST 24
Peak memory 367684 kb
Host smart-25a93323-f0fd-470c-9110-d4379424295c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238010865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3238010865
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2883286627
Short name T90
Test name
Test status
Simulation time 4031629339 ps
CPU time 76.61 seconds
Started Jan 21 12:33:45 PM PST 24
Finished Jan 21 12:35:02 PM PST 24
Peak memory 211916 kb
Host smart-1a045050-94ad-4b21-bcbf-4f2317e03e61
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883286627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.2883286627
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.2649049744
Short name T354
Test name
Test status
Simulation time 1978630121 ps
CPU time 119.54 seconds
Started Jan 21 12:33:46 PM PST 24
Finished Jan 21 12:35:46 PM PST 24
Peak memory 202068 kb
Host smart-43db2b61-0722-4998-a609-fc173540658d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649049744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.2649049744
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.231002100
Short name T445
Test name
Test status
Simulation time 72975435839 ps
CPU time 544.29 seconds
Started Jan 21 12:33:29 PM PST 24
Finished Jan 21 12:42:34 PM PST 24
Peak memory 366748 kb
Host smart-44b5d338-89c6-46e2-85c1-408b5fb575c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231002100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip
le_keys.231002100
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.3721963639
Short name T276
Test name
Test status
Simulation time 1090471841 ps
CPU time 78.36 seconds
Started Jan 21 12:33:40 PM PST 24
Finished Jan 21 12:34:59 PM PST 24
Peak memory 359596 kb
Host smart-9c4c3914-c174-47e0-8df9-96e4ef07229a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721963639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.3721963639
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.624539790
Short name T798
Test name
Test status
Simulation time 55523683059 ps
CPU time 362.1 seconds
Started Jan 21 12:33:38 PM PST 24
Finished Jan 21 12:39:41 PM PST 24
Peak memory 202048 kb
Host smart-a28f5cd0-1084-4582-92a3-f03488db9976
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624539790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.sram_ctrl_partial_access_b2b.624539790
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.48993094
Short name T495
Test name
Test status
Simulation time 1415697337 ps
CPU time 13.29 seconds
Started Jan 21 12:33:43 PM PST 24
Finished Jan 21 12:33:56 PM PST 24
Peak memory 202376 kb
Host smart-2f4562ca-4828-4c78-9829-0f78a231b579
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48993094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.48993094
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.3372465545
Short name T262
Test name
Test status
Simulation time 2689919781 ps
CPU time 200.61 seconds
Started Jan 21 12:33:38 PM PST 24
Finished Jan 21 12:36:59 PM PST 24
Peak memory 359836 kb
Host smart-174649eb-f9e7-4ea3-9487-af13c1d0ec84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372465545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.3372465545
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.1833768610
Short name T353
Test name
Test status
Simulation time 1919604194 ps
CPU time 47.54 seconds
Started Jan 21 12:33:30 PM PST 24
Finished Jan 21 12:34:19 PM PST 24
Peak memory 303488 kb
Host smart-60b6e478-8fcb-4ff3-ad43-22a5ad29a08d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833768610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1833768610
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.2072861077
Short name T372
Test name
Test status
Simulation time 33839338854 ps
CPU time 1054.34 seconds
Started Jan 21 12:33:43 PM PST 24
Finished Jan 21 12:51:18 PM PST 24
Peak memory 379016 kb
Host smart-15d0003e-fc38-461c-aaef-73da793408d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072861077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.sram_ctrl_stress_all.2072861077
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3439379410
Short name T431
Test name
Test status
Simulation time 7387413526 ps
CPU time 2335.27 seconds
Started Jan 21 12:46:43 PM PST 24
Finished Jan 21 01:25:40 PM PST 24
Peak memory 606764 kb
Host smart-307340d2-ba64-46f4-9b62-2aac053c6997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3439379410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3439379410
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3418681981
Short name T217
Test name
Test status
Simulation time 3129894431 ps
CPU time 218.35 seconds
Started Jan 21 12:33:28 PM PST 24
Finished Jan 21 12:37:07 PM PST 24
Peak memory 202124 kb
Host smart-850f92cd-a4ea-44e1-a34e-48863c41eb0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418681981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.3418681981
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.845929753
Short name T377
Test name
Test status
Simulation time 2786506689 ps
CPU time 27.01 seconds
Started Jan 21 12:47:28 PM PST 24
Finished Jan 21 12:47:56 PM PST 24
Peak memory 210348 kb
Host smart-98882af7-a60a-4c23-a514-cc1498578665
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845929753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.845929753
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.96628690
Short name T328
Test name
Test status
Simulation time 6097033027 ps
CPU time 702.66 seconds
Started Jan 21 12:48:47 PM PST 24
Finished Jan 21 01:00:31 PM PST 24
Peak memory 369812 kb
Host smart-0edb2d92-61ad-4cb8-9475-3ad906c7fab4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96628690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.sram_ctrl_access_during_key_req.96628690
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.2500537861
Short name T703
Test name
Test status
Simulation time 42236853 ps
CPU time 0.66 seconds
Started Jan 21 12:34:04 PM PST 24
Finished Jan 21 12:34:05 PM PST 24
Peak memory 201396 kb
Host smart-aea33bb3-8e33-4fdf-8188-4842e18fe1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500537861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.2500537861
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.1599668056
Short name T831
Test name
Test status
Simulation time 121563707109 ps
CPU time 2071.15 seconds
Started Jan 21 02:33:40 PM PST 24
Finished Jan 21 03:08:12 PM PST 24
Peak memory 202356 kb
Host smart-3155dda5-80f2-491b-a1d9-f64d14a40772
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599668056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.1599668056
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.3441590971
Short name T847
Test name
Test status
Simulation time 1531938486 ps
CPU time 124.81 seconds
Started Jan 21 12:33:52 PM PST 24
Finished Jan 21 12:35:58 PM PST 24
Peak memory 364584 kb
Host smart-08ddeb42-f8f2-4baa-9858-49c7e8d1d7f2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441590971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.3441590971
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3418913635
Short name T769
Test name
Test status
Simulation time 988336227 ps
CPU time 73.96 seconds
Started Jan 21 12:40:44 PM PST 24
Finished Jan 21 12:42:00 PM PST 24
Peak memory 210996 kb
Host smart-1659b34d-066f-4b26-a3c1-76c30860fac3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418913635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.3418913635
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.1163520050
Short name T923
Test name
Test status
Simulation time 7882802303 ps
CPU time 242.81 seconds
Started Jan 21 12:34:03 PM PST 24
Finished Jan 21 12:38:06 PM PST 24
Peak memory 202468 kb
Host smart-fb6d1056-ca35-48a2-a3db-788bcf5b0bda
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163520050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.1163520050
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.784154731
Short name T785
Test name
Test status
Simulation time 22563150211 ps
CPU time 1459.14 seconds
Started Jan 21 12:33:53 PM PST 24
Finished Jan 21 12:58:13 PM PST 24
Peak memory 373940 kb
Host smart-5e684e9c-d804-42bc-96fd-26e18cd89a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784154731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multip
le_keys.784154731
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.1110757823
Short name T676
Test name
Test status
Simulation time 1008841913 ps
CPU time 144.86 seconds
Started Jan 21 12:33:52 PM PST 24
Finished Jan 21 12:36:18 PM PST 24
Peak memory 369816 kb
Host smart-f24de98a-36ce-41e8-932f-0327407acf58
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110757823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.1110757823
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2944473120
Short name T567
Test name
Test status
Simulation time 164350289392 ps
CPU time 427.04 seconds
Started Jan 21 12:33:53 PM PST 24
Finished Jan 21 12:41:01 PM PST 24
Peak memory 202112 kb
Host smart-0c28b876-df49-48f6-b5d7-3e3dc8356206
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944473120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.2944473120
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.2478817216
Short name T675
Test name
Test status
Simulation time 2241667561 ps
CPU time 13.93 seconds
Started Jan 21 12:33:58 PM PST 24
Finished Jan 21 12:34:14 PM PST 24
Peak memory 202396 kb
Host smart-e482cc59-82be-440c-8ba4-4913ea09798b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478817216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2478817216
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.2963649156
Short name T938
Test name
Test status
Simulation time 9148946955 ps
CPU time 408.91 seconds
Started Jan 21 02:20:34 PM PST 24
Finished Jan 21 02:27:23 PM PST 24
Peak memory 372964 kb
Host smart-48a34e59-a78c-4459-81c6-ef201f69f4fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963649156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2963649156
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.223315321
Short name T679
Test name
Test status
Simulation time 394532636 ps
CPU time 7.44 seconds
Started Jan 21 12:33:53 PM PST 24
Finished Jan 21 12:34:01 PM PST 24
Peak memory 202088 kb
Host smart-96ec69b5-dca4-414f-bbaf-5495b11dc76c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223315321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.223315321
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.681814239
Short name T449
Test name
Test status
Simulation time 123641634880 ps
CPU time 2006.63 seconds
Started Jan 21 12:34:03 PM PST 24
Finished Jan 21 01:07:30 PM PST 24
Peak memory 372852 kb
Host smart-08ac63af-b30f-4924-bcf8-2722273d323a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681814239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_stress_all.681814239
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2500030887
Short name T951
Test name
Test status
Simulation time 6001252685 ps
CPU time 4590.89 seconds
Started Jan 21 12:34:06 PM PST 24
Finished Jan 21 01:50:38 PM PST 24
Peak memory 675804 kb
Host smart-1534761e-4f8d-4361-9e0e-9e5906f2a951
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2500030887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2500030887
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1887392561
Short name T839
Test name
Test status
Simulation time 4706763784 ps
CPU time 374.96 seconds
Started Jan 21 12:33:52 PM PST 24
Finished Jan 21 12:40:07 PM PST 24
Peak memory 202152 kb
Host smart-7e56d239-b3bb-4b8f-b8ae-3b19a470d000
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887392561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.1887392561
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1052303152
Short name T517
Test name
Test status
Simulation time 2940155518 ps
CPU time 39.39 seconds
Started Jan 21 12:33:55 PM PST 24
Finished Jan 21 12:34:35 PM PST 24
Peak memory 257128 kb
Host smart-7164490b-869c-4443-b23b-e68f1945f50d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052303152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.1052303152
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1012594208
Short name T348
Test name
Test status
Simulation time 21796712455 ps
CPU time 755.33 seconds
Started Jan 21 12:34:13 PM PST 24
Finished Jan 21 12:46:49 PM PST 24
Peak memory 369736 kb
Host smart-9eb61d3f-eee8-4c53-a02e-0ab61aa983a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012594208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.1012594208
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3601884502
Short name T674
Test name
Test status
Simulation time 23336154 ps
CPU time 0.63 seconds
Started Jan 21 12:34:26 PM PST 24
Finished Jan 21 12:34:27 PM PST 24
Peak memory 202132 kb
Host smart-3db56d14-6173-456d-82d8-232c59310975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601884502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3601884502
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.2702547331
Short name T15
Test name
Test status
Simulation time 998372622965 ps
CPU time 1712.91 seconds
Started Jan 21 12:34:11 PM PST 24
Finished Jan 21 01:02:45 PM PST 24
Peak memory 202272 kb
Host smart-d1535170-4f0a-4ee4-b789-be74268d131c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702547331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2702547331
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.3608264857
Short name T630
Test name
Test status
Simulation time 3423001355 ps
CPU time 448.31 seconds
Started Jan 21 12:34:23 PM PST 24
Finished Jan 21 12:41:52 PM PST 24
Peak memory 366768 kb
Host smart-2182a2e6-2595-4e14-9ede-059046e5ee28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608264857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.3608264857
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.2951978322
Short name T921
Test name
Test status
Simulation time 14416662648 ps
CPU time 282.92 seconds
Started Jan 21 12:34:13 PM PST 24
Finished Jan 21 12:38:57 PM PST 24
Peak memory 212080 kb
Host smart-1f9152fd-2261-4842-bb6c-6c5fcc80fc29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951978322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.2951978322
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.1727284726
Short name T299
Test name
Test status
Simulation time 5256639552 ps
CPU time 31.58 seconds
Started Jan 21 12:34:13 PM PST 24
Finished Jan 21 12:34:45 PM PST 24
Peak memory 227664 kb
Host smart-9cd7e06f-835c-4977-9593-6a344446aef0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727284726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.1727284726
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3646379991
Short name T429
Test name
Test status
Simulation time 2741769293 ps
CPU time 78.76 seconds
Started Jan 21 12:34:22 PM PST 24
Finished Jan 21 12:35:41 PM PST 24
Peak memory 211148 kb
Host smart-604fb9b0-2d79-439b-a814-02d212bf2330
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646379991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.3646379991
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.3958384640
Short name T796
Test name
Test status
Simulation time 20681947707 ps
CPU time 151.96 seconds
Started Jan 21 12:34:24 PM PST 24
Finished Jan 21 12:36:56 PM PST 24
Peak memory 202144 kb
Host smart-e09086f0-6938-419f-8400-930aa8ac9a38
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958384640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.3958384640
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.2771409725
Short name T673
Test name
Test status
Simulation time 708994744 ps
CPU time 10.53 seconds
Started Jan 21 01:25:20 PM PST 24
Finished Jan 21 01:25:31 PM PST 24
Peak memory 202204 kb
Host smart-d3e1283e-d7d7-41d7-aeee-a0fb8bf89917
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771409725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.2771409725
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2313739838
Short name T647
Test name
Test status
Simulation time 10686502509 ps
CPU time 322.52 seconds
Started Jan 21 12:34:14 PM PST 24
Finished Jan 21 12:39:37 PM PST 24
Peak memory 202192 kb
Host smart-c1f077e9-c58f-4108-b88e-dc60565d204f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313739838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.2313739838
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.2651598940
Short name T744
Test name
Test status
Simulation time 2906336633 ps
CPU time 116.92 seconds
Started Jan 21 12:34:19 PM PST 24
Finished Jan 21 12:36:17 PM PST 24
Peak memory 372812 kb
Host smart-8a3f4410-d9a4-4f6a-b4d0-75d686030b17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651598940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2651598940
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.225380465
Short name T300
Test name
Test status
Simulation time 5372112251 ps
CPU time 9.78 seconds
Started Jan 21 12:34:04 PM PST 24
Finished Jan 21 12:34:15 PM PST 24
Peak memory 216304 kb
Host smart-304526be-85dd-4f9f-ae9e-536c0d2fdb63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225380465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.225380465
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3231723892
Short name T347
Test name
Test status
Simulation time 2362680624 ps
CPU time 5587.49 seconds
Started Jan 21 12:34:21 PM PST 24
Finished Jan 21 02:07:29 PM PST 24
Peak memory 698972 kb
Host smart-d0b89258-f2bc-4ee5-9da9-ba34b632cf29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3231723892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3231723892
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.4243911940
Short name T706
Test name
Test status
Simulation time 18263442981 ps
CPU time 337.64 seconds
Started Jan 21 12:34:14 PM PST 24
Finished Jan 21 12:39:52 PM PST 24
Peak memory 202216 kb
Host smart-228a5c06-9b9e-4b1a-9369-f98ce3dafe25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243911940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.4243911940
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.899106938
Short name T844
Test name
Test status
Simulation time 7742761470 ps
CPU time 177 seconds
Started Jan 21 12:34:13 PM PST 24
Finished Jan 21 12:37:11 PM PST 24
Peak memory 354576 kb
Host smart-990d6237-d490-4189-bc22-610bc104fd9b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899106938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.899106938
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3316409272
Short name T444
Test name
Test status
Simulation time 9828466026 ps
CPU time 1088.8 seconds
Started Jan 21 12:34:43 PM PST 24
Finished Jan 21 12:52:57 PM PST 24
Peak memory 367868 kb
Host smart-f58699b1-4d5c-4489-8bb4-faf7637a1551
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316409272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.3316409272
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.2749002466
Short name T235
Test name
Test status
Simulation time 32655209 ps
CPU time 0.64 seconds
Started Jan 21 12:34:51 PM PST 24
Finished Jan 21 12:34:54 PM PST 24
Peak memory 202076 kb
Host smart-51c19a53-1e5f-459d-9aa4-511b3bd20850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749002466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.2749002466
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.4273380945
Short name T937
Test name
Test status
Simulation time 32137152696 ps
CPU time 1083.16 seconds
Started Jan 21 12:34:34 PM PST 24
Finished Jan 21 12:52:38 PM PST 24
Peak memory 202252 kb
Host smart-5d4a10a9-566d-40b6-bdce-49149d4012f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273380945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.4273380945
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.419178972
Short name T602
Test name
Test status
Simulation time 15941550179 ps
CPU time 85.14 seconds
Started Jan 21 12:34:41 PM PST 24
Finished Jan 21 12:36:12 PM PST 24
Peak memory 210468 kb
Host smart-0f18246e-ca59-4089-a92a-5ed67828553f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419178972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_esc
alation.419178972
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.1492149935
Short name T636
Test name
Test status
Simulation time 3698857378 ps
CPU time 45.11 seconds
Started Jan 21 12:34:34 PM PST 24
Finished Jan 21 12:35:20 PM PST 24
Peak memory 267516 kb
Host smart-627ada39-5536-4233-a048-86a4daad1fa6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492149935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.1492149935
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.903129357
Short name T638
Test name
Test status
Simulation time 1893140359 ps
CPU time 70.59 seconds
Started Jan 21 12:34:41 PM PST 24
Finished Jan 21 12:35:53 PM PST 24
Peak memory 210996 kb
Host smart-3150cc15-5f0f-4e25-ace8-b887b5ec1d40
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903129357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.sram_ctrl_mem_partial_access.903129357
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1449559712
Short name T624
Test name
Test status
Simulation time 4111786180 ps
CPU time 234.49 seconds
Started Jan 21 12:34:41 PM PST 24
Finished Jan 21 12:38:37 PM PST 24
Peak memory 202140 kb
Host smart-37abfb89-31b4-494e-b1de-2d3d4a520f11
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449559712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1449559712
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.1500038034
Short name T820
Test name
Test status
Simulation time 14055574217 ps
CPU time 1423.78 seconds
Started Jan 21 12:34:25 PM PST 24
Finished Jan 21 12:58:10 PM PST 24
Peak memory 380064 kb
Host smart-b51ca537-b1d5-43a7-8435-f62a3de785b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500038034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.1500038034
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.4144125253
Short name T934
Test name
Test status
Simulation time 2171699135 ps
CPU time 8.16 seconds
Started Jan 21 12:34:33 PM PST 24
Finished Jan 21 12:34:42 PM PST 24
Peak memory 202124 kb
Host smart-2acf8397-8a1d-446b-91c3-3dd5ad56dc1b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144125253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.4144125253
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1044118157
Short name T465
Test name
Test status
Simulation time 146835883267 ps
CPU time 355.4 seconds
Started Jan 21 12:34:33 PM PST 24
Finished Jan 21 12:40:29 PM PST 24
Peak memory 210308 kb
Host smart-e9af39b1-8b58-49c3-b2f0-55f7406057f1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044118157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.1044118157
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.1088117973
Short name T577
Test name
Test status
Simulation time 712151583 ps
CPU time 6.3 seconds
Started Jan 21 12:34:42 PM PST 24
Finished Jan 21 12:34:55 PM PST 24
Peak memory 202248 kb
Host smart-b54f5042-7907-4bea-b26a-5e01923513a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088117973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1088117973
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.155569583
Short name T248
Test name
Test status
Simulation time 27113681696 ps
CPU time 615.02 seconds
Started Jan 21 12:34:43 PM PST 24
Finished Jan 21 12:45:04 PM PST 24
Peak memory 350364 kb
Host smart-f1b3398d-8065-46f4-9fbe-283f5996da1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155569583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.155569583
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.1366911487
Short name T770
Test name
Test status
Simulation time 1979377508 ps
CPU time 132.34 seconds
Started Jan 21 12:34:28 PM PST 24
Finished Jan 21 12:36:41 PM PST 24
Peak memory 368656 kb
Host smart-d70b4376-079f-421a-b5a4-9bd708f4efa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366911487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1366911487
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.4035865178
Short name T822
Test name
Test status
Simulation time 520033502470 ps
CPU time 7674.35 seconds
Started Jan 21 12:34:48 PM PST 24
Finished Jan 21 02:42:47 PM PST 24
Peak memory 378988 kb
Host smart-fc0cf13e-c3ef-4031-b996-3d6359425fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035865178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.4035865178
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.982698424
Short name T341
Test name
Test status
Simulation time 3196967511 ps
CPU time 5309.9 seconds
Started Jan 21 12:34:44 PM PST 24
Finished Jan 21 02:03:19 PM PST 24
Peak memory 440888 kb
Host smart-ac026427-380c-4300-952f-e10e2076f76a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=982698424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.982698424
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3645771945
Short name T16
Test name
Test status
Simulation time 2675722855 ps
CPU time 169.73 seconds
Started Jan 21 01:13:03 PM PST 24
Finished Jan 21 01:15:53 PM PST 24
Peak memory 202176 kb
Host smart-2f3108c7-8091-4217-805d-b24c17731d22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645771945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.3645771945
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1238612641
Short name T629
Test name
Test status
Simulation time 1249240830 ps
CPU time 135.89 seconds
Started Jan 21 12:45:27 PM PST 24
Finished Jan 21 12:47:45 PM PST 24
Peak memory 364708 kb
Host smart-d0c8f362-3f23-4528-a163-9d4691e6bd7d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238612641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1238612641
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.962045948
Short name T754
Test name
Test status
Simulation time 10038068399 ps
CPU time 1124.73 seconds
Started Jan 21 12:35:01 PM PST 24
Finished Jan 21 12:53:48 PM PST 24
Peak memory 371608 kb
Host smart-bafded61-5cac-4bbb-bc55-e406566a9041
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962045948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.sram_ctrl_access_during_key_req.962045948
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.699959757
Short name T511
Test name
Test status
Simulation time 22691640 ps
CPU time 0.65 seconds
Started Jan 21 02:51:22 PM PST 24
Finished Jan 21 02:51:23 PM PST 24
Peak memory 201592 kb
Host smart-b2fa37a1-0f4b-46ec-b92c-2f5f8b378c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699959757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.699959757
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.1254229662
Short name T469
Test name
Test status
Simulation time 258662895916 ps
CPU time 2418.34 seconds
Started Jan 21 12:34:49 PM PST 24
Finished Jan 21 01:15:11 PM PST 24
Peak memory 202084 kb
Host smart-605ff9bc-f1ea-49c5-b1d7-cfad4cd10580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254229662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.1254229662
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.990301715
Short name T463
Test name
Test status
Simulation time 4288406078 ps
CPU time 113.19 seconds
Started Jan 21 12:35:05 PM PST 24
Finished Jan 21 12:36:59 PM PST 24
Peak memory 244380 kb
Host smart-a08fde30-4d5f-44b3-b7bf-d575a6ae9520
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990301715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl
e.990301715
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.1199240293
Short name T369
Test name
Test status
Simulation time 20880888581 ps
CPU time 123.8 seconds
Started Jan 21 12:35:01 PM PST 24
Finished Jan 21 12:37:06 PM PST 24
Peak memory 210308 kb
Host smart-f95bdba5-00c8-4cea-88c0-513893fab3bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199240293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.1199240293
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.2512135605
Short name T760
Test name
Test status
Simulation time 2882570877 ps
CPU time 32.5 seconds
Started Jan 21 12:34:55 PM PST 24
Finished Jan 21 12:35:31 PM PST 24
Peak memory 242720 kb
Host smart-57b567bc-7ed7-477e-afcd-cd2feb7be335
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512135605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.2512135605
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3607149622
Short name T457
Test name
Test status
Simulation time 5604774669 ps
CPU time 73.04 seconds
Started Jan 21 12:35:03 PM PST 24
Finished Jan 21 12:36:17 PM PST 24
Peak memory 211204 kb
Host smart-57210f5e-306a-41ba-ac56-f60c5fc1eff2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607149622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.3607149622
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.2101607253
Short name T846
Test name
Test status
Simulation time 4108802444 ps
CPU time 230.17 seconds
Started Jan 21 12:35:04 PM PST 24
Finished Jan 21 12:38:55 PM PST 24
Peak memory 202128 kb
Host smart-49aaab00-348c-4c71-9208-3be8b8773df8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101607253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.2101607253
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.3102645705
Short name T319
Test name
Test status
Simulation time 12795834058 ps
CPU time 916.55 seconds
Started Jan 21 01:02:14 PM PST 24
Finished Jan 21 01:17:32 PM PST 24
Peak memory 376244 kb
Host smart-7e69f1df-cdb0-4daf-883f-70cb68eb7dff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102645705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.3102645705
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.1100509362
Short name T318
Test name
Test status
Simulation time 19729419972 ps
CPU time 83.16 seconds
Started Jan 21 12:34:50 PM PST 24
Finished Jan 21 12:36:16 PM PST 24
Peak memory 318824 kb
Host smart-f09a5a6c-dd75-4807-9361-552f3df098c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100509362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.1100509362
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1862598262
Short name T550
Test name
Test status
Simulation time 22472421802 ps
CPU time 233.81 seconds
Started Jan 21 12:34:48 PM PST 24
Finished Jan 21 12:38:45 PM PST 24
Peak memory 202044 kb
Host smart-d0204114-e0aa-4d93-a826-07e3737e43ee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862598262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.1862598262
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.320920371
Short name T618
Test name
Test status
Simulation time 1411464691 ps
CPU time 5.47 seconds
Started Jan 21 12:35:02 PM PST 24
Finished Jan 21 12:35:09 PM PST 24
Peak memory 202308 kb
Host smart-0a887e12-3eb1-42b6-9c5e-35af5ca79f58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320920371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.320920371
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.3346920521
Short name T202
Test name
Test status
Simulation time 19411890576 ps
CPU time 836.07 seconds
Started Jan 21 01:03:49 PM PST 24
Finished Jan 21 01:17:46 PM PST 24
Peak memory 378128 kb
Host smart-48483d11-901d-410c-aef9-cdfd92177ce1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346920521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3346920521
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.1614617994
Short name T274
Test name
Test status
Simulation time 456277734 ps
CPU time 114.81 seconds
Started Jan 21 12:34:51 PM PST 24
Finished Jan 21 12:36:48 PM PST 24
Peak memory 345048 kb
Host smart-ee290a84-f0c1-4545-8ae0-2f4c952f2a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614617994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1614617994
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1952238997
Short name T563
Test name
Test status
Simulation time 1942236499 ps
CPU time 1154.14 seconds
Started Jan 21 12:35:03 PM PST 24
Finished Jan 21 12:54:18 PM PST 24
Peak memory 472336 kb
Host smart-44ddf6f4-4f4c-427f-9d6b-b1031becc271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1952238997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1952238997
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.3409177116
Short name T407
Test name
Test status
Simulation time 4559946040 ps
CPU time 301.57 seconds
Started Jan 21 12:34:49 PM PST 24
Finished Jan 21 12:39:54 PM PST 24
Peak memory 202188 kb
Host smart-54a19749-a697-4f8a-9a6f-ab7ce1a15b71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409177116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.3409177116
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.981300885
Short name T412
Test name
Test status
Simulation time 3041950958 ps
CPU time 123.3 seconds
Started Jan 21 12:35:00 PM PST 24
Finished Jan 21 12:37:04 PM PST 24
Peak memory 340132 kb
Host smart-68efe780-35fe-4bfe-8dbe-e23b3f2f4bf6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981300885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_throughput_w_partial_write.981300885
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.4261624543
Short name T745
Test name
Test status
Simulation time 7183659318 ps
CPU time 92.05 seconds
Started Jan 21 12:35:21 PM PST 24
Finished Jan 21 12:37:07 PM PST 24
Peak memory 239928 kb
Host smart-75d62e36-93ac-45da-ab33-7c41d4dd9aa9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261624543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.4261624543
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.1703188759
Short name T824
Test name
Test status
Simulation time 56092893 ps
CPU time 0.62 seconds
Started Jan 21 12:35:25 PM PST 24
Finished Jan 21 12:35:46 PM PST 24
Peak memory 202116 kb
Host smart-948ac1e3-f64f-470b-bb11-24704fea885b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703188759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.1703188759
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.1430505540
Short name T599
Test name
Test status
Simulation time 18691264171 ps
CPU time 1301.97 seconds
Started Jan 21 12:35:10 PM PST 24
Finished Jan 21 12:56:53 PM PST 24
Peak memory 202220 kb
Host smart-b679fd8a-f001-427d-8016-2a5b3429a3bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430505540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.1430505540
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.4151335431
Short name T952
Test name
Test status
Simulation time 7414869776 ps
CPU time 105.02 seconds
Started Jan 21 12:35:19 PM PST 24
Finished Jan 21 12:37:16 PM PST 24
Peak memory 280904 kb
Host smart-85cfbb85-d885-4126-af37-9deec0e6161b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151335431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.4151335431
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.2109694759
Short name T853
Test name
Test status
Simulation time 101329197235 ps
CPU time 294.2 seconds
Started Jan 21 12:54:48 PM PST 24
Finished Jan 21 12:59:44 PM PST 24
Peak memory 210600 kb
Host smart-5956b63c-98fe-4149-adf2-0a7116248ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109694759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.2109694759
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.18590960
Short name T103
Test name
Test status
Simulation time 3021238596 ps
CPU time 127.5 seconds
Started Jan 21 12:35:18 PM PST 24
Finished Jan 21 12:37:36 PM PST 24
Peak memory 356556 kb
Host smart-5a8dabfb-d7e2-47e1-ab96-bb87f476a3f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18590960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_max_throughput.18590960
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1335605367
Short name T840
Test name
Test status
Simulation time 2667805748 ps
CPU time 78.24 seconds
Started Jan 21 12:35:27 PM PST 24
Finished Jan 21 12:37:05 PM PST 24
Peak memory 211148 kb
Host smart-76cf64b1-4ea8-4df3-ac61-24d98fbfbb45
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335605367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.1335605367
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.1818947329
Short name T387
Test name
Test status
Simulation time 8212803821 ps
CPU time 242.34 seconds
Started Jan 21 12:35:26 PM PST 24
Finished Jan 21 12:39:48 PM PST 24
Peak memory 202188 kb
Host smart-330a14e0-e746-4ddf-ab5f-89bb84e2a38c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818947329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.1818947329
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3300238888
Short name T885
Test name
Test status
Simulation time 44099724666 ps
CPU time 1260.5 seconds
Started Jan 21 12:56:09 PM PST 24
Finished Jan 21 01:17:11 PM PST 24
Peak memory 377004 kb
Host smart-7918cd6f-369c-4703-a929-6df5600a8804
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300238888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3300238888
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.1785895067
Short name T926
Test name
Test status
Simulation time 1069962162 ps
CPU time 137.95 seconds
Started Jan 21 12:35:17 PM PST 24
Finished Jan 21 12:37:45 PM PST 24
Peak memory 358848 kb
Host smart-8a7de6f3-5603-4faf-9498-e4e045f4ceb5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785895067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.1785895067
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3709998032
Short name T478
Test name
Test status
Simulation time 29258564420 ps
CPU time 341.88 seconds
Started Jan 21 12:53:45 PM PST 24
Finished Jan 21 12:59:31 PM PST 24
Peak memory 202184 kb
Host smart-0f8030a0-9e57-4826-b03d-a594401d8d80
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709998032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.3709998032
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.2269273863
Short name T882
Test name
Test status
Simulation time 552607347 ps
CPU time 5.35 seconds
Started Jan 21 12:58:05 PM PST 24
Finished Jan 21 12:58:11 PM PST 24
Peak memory 202344 kb
Host smart-a2831ff8-59c4-4f23-8d29-526c91a28821
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269273863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2269273863
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.1739571289
Short name T417
Test name
Test status
Simulation time 47069779137 ps
CPU time 915.1 seconds
Started Jan 21 12:35:24 PM PST 24
Finished Jan 21 12:50:58 PM PST 24
Peak memory 373956 kb
Host smart-0e4832a6-df0d-4da1-8e41-6e296d81915c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739571289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1739571289
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.4012455180
Short name T502
Test name
Test status
Simulation time 3318607361 ps
CPU time 32.43 seconds
Started Jan 21 12:35:10 PM PST 24
Finished Jan 21 12:35:43 PM PST 24
Peak memory 202256 kb
Host smart-29d21c57-8793-4af7-9c4a-bfede61a7124
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012455180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.4012455180
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.2790134283
Short name T870
Test name
Test status
Simulation time 730201660616 ps
CPU time 8131.6 seconds
Started Jan 21 12:35:26 PM PST 24
Finished Jan 21 02:51:18 PM PST 24
Peak memory 381176 kb
Host smart-6c0c3c99-86e6-4656-a732-b1a35dc80776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790134283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.2790134283
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1493361488
Short name T940
Test name
Test status
Simulation time 1192838568 ps
CPU time 4380.38 seconds
Started Jan 21 12:35:23 PM PST 24
Finished Jan 21 01:48:42 PM PST 24
Peak memory 548612 kb
Host smart-c6de6c31-9ff1-4cd8-ba93-259eff00e4ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1493361488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1493361488
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1132805091
Short name T851
Test name
Test status
Simulation time 20082866950 ps
CPU time 255.18 seconds
Started Jan 21 12:35:10 PM PST 24
Finished Jan 21 12:39:26 PM PST 24
Peak memory 202272 kb
Host smart-a3023acf-87c9-466e-ac20-f6b18407853d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132805091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.1132805091
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4281535737
Short name T887
Test name
Test status
Simulation time 3367181262 ps
CPU time 39.43 seconds
Started Jan 21 12:35:18 PM PST 24
Finished Jan 21 12:36:08 PM PST 24
Peak memory 258208 kb
Host smart-d9b7c985-2a76-4fac-bf57-5113f8177131
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281535737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.4281535737
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.50703142
Short name T665
Test name
Test status
Simulation time 9076754924 ps
CPU time 1757.75 seconds
Started Jan 21 12:35:40 PM PST 24
Finished Jan 21 01:05:10 PM PST 24
Peak memory 377976 kb
Host smart-652fd2d1-2973-4df7-a7b4-f83fd78a1992
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50703142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.sram_ctrl_access_during_key_req.50703142
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.595596685
Short name T788
Test name
Test status
Simulation time 17891205 ps
CPU time 0.67 seconds
Started Jan 21 12:35:46 PM PST 24
Finished Jan 21 12:35:55 PM PST 24
Peak memory 201400 kb
Host smart-10ef453d-38fe-49c2-84e1-01f304f88616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595596685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.595596685
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.2098177275
Short name T38
Test name
Test status
Simulation time 17390823454 ps
CPU time 1211.17 seconds
Started Jan 21 12:35:29 PM PST 24
Finished Jan 21 12:56:00 PM PST 24
Peak memory 202220 kb
Host smart-498bbefe-d004-457c-a627-44c5898726cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098177275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.2098177275
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.4127559174
Short name T413
Test name
Test status
Simulation time 7297884635 ps
CPU time 65.39 seconds
Started Jan 21 12:35:36 PM PST 24
Finished Jan 21 12:36:56 PM PST 24
Peak memory 210400 kb
Host smart-daa41d85-6f6f-44b8-9dad-5fa71b8997bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127559174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.4127559174
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.3842730837
Short name T741
Test name
Test status
Simulation time 2097511500 ps
CPU time 135.78 seconds
Started Jan 21 12:35:31 PM PST 24
Finished Jan 21 12:38:05 PM PST 24
Peak memory 353416 kb
Host smart-3e70b1e2-91d6-4fac-b54d-ee3460765185
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842730837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.3842730837
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1866051424
Short name T278
Test name
Test status
Simulation time 15563967556 ps
CPU time 75.18 seconds
Started Jan 21 12:35:45 PM PST 24
Finished Jan 21 12:37:10 PM PST 24
Peak memory 212184 kb
Host smart-3097bfc9-ed54-46e1-a7f5-56112b1af56e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866051424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.1866051424
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.178462828
Short name T723
Test name
Test status
Simulation time 16412416264 ps
CPU time 249.73 seconds
Started Jan 21 12:35:46 PM PST 24
Finished Jan 21 12:40:05 PM PST 24
Peak memory 202260 kb
Host smart-a228b60c-760f-4224-9c7b-95442778a9ee
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178462828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_mem_walk.178462828
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.1040197215
Short name T10
Test name
Test status
Simulation time 17758712298 ps
CPU time 411.61 seconds
Started Jan 21 12:35:23 PM PST 24
Finished Jan 21 12:42:31 PM PST 24
Peak memory 377344 kb
Host smart-0000839b-547a-4998-bf98-a497e6dc92b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040197215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.1040197215
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.636866061
Short name T954
Test name
Test status
Simulation time 794018703 ps
CPU time 25.95 seconds
Started Jan 21 12:35:32 PM PST 24
Finished Jan 21 12:36:15 PM PST 24
Peak memory 250716 kb
Host smart-4e772890-125e-4d6e-9cba-638a6ead839d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636866061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s
ram_ctrl_partial_access.636866061
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3328426753
Short name T211
Test name
Test status
Simulation time 20014339639 ps
CPU time 376.91 seconds
Started Jan 21 12:35:31 PM PST 24
Finished Jan 21 12:42:06 PM PST 24
Peak memory 202084 kb
Host smart-ad2fda84-3241-42b0-b9be-e05f8723c7fc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328426753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.3328426753
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3670359405
Short name T662
Test name
Test status
Simulation time 1352716880 ps
CPU time 6.7 seconds
Started Jan 21 01:24:01 PM PST 24
Finished Jan 21 01:24:08 PM PST 24
Peak memory 202428 kb
Host smart-705d5af2-4c2e-42fb-aaba-3f112a795c03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670359405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3670359405
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.2471889344
Short name T866
Test name
Test status
Simulation time 11714996196 ps
CPU time 1109.67 seconds
Started Jan 21 12:35:49 PM PST 24
Finished Jan 21 12:54:25 PM PST 24
Peak memory 378244 kb
Host smart-31987c2f-fdd6-4173-869f-8bc82fb1ccb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471889344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2471889344
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.3034452709
Short name T355
Test name
Test status
Simulation time 2969983341 ps
CPU time 136.76 seconds
Started Jan 21 12:35:26 PM PST 24
Finished Jan 21 12:38:03 PM PST 24
Peak memory 365672 kb
Host smart-31b0495f-e892-4f7e-9889-fe78cd6d1a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034452709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3034452709
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.2348597320
Short name T848
Test name
Test status
Simulation time 584493790606 ps
CPU time 5381.15 seconds
Started Jan 21 12:35:49 PM PST 24
Finished Jan 21 02:05:37 PM PST 24
Peak memory 378032 kb
Host smart-c32117af-073b-4de3-ab78-50bd3e4c1e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348597320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.2348597320
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1965234673
Short name T403
Test name
Test status
Simulation time 7776179965 ps
CPU time 5446.43 seconds
Started Jan 21 12:35:46 PM PST 24
Finished Jan 21 02:06:42 PM PST 24
Peak memory 676052 kb
Host smart-e455593c-2c66-4232-8d8f-0ef95ea5a260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1965234673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1965234673
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3245713271
Short name T941
Test name
Test status
Simulation time 4442332028 ps
CPU time 285.82 seconds
Started Jan 21 12:35:31 PM PST 24
Finished Jan 21 12:40:36 PM PST 24
Peak memory 202176 kb
Host smart-c05f0dc7-e989-4776-ae51-1757ee7577d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245713271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.3245713271
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3316486982
Short name T904
Test name
Test status
Simulation time 1506809434 ps
CPU time 40.75 seconds
Started Jan 21 12:35:31 PM PST 24
Finished Jan 21 12:36:30 PM PST 24
Peak memory 260928 kb
Host smart-b8d7b1af-4a66-4bf5-8e03-e735e5c2da8d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316486982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.3316486982
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.4266578528
Short name T427
Test name
Test status
Simulation time 7661367632 ps
CPU time 1037.82 seconds
Started Jan 21 12:36:10 PM PST 24
Finished Jan 21 12:53:29 PM PST 24
Peak memory 379996 kb
Host smart-9ab03de6-140e-4fe0-9d39-7606d0563c0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266578528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.4266578528
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.2734296370
Short name T473
Test name
Test status
Simulation time 31491406 ps
CPU time 0.65 seconds
Started Jan 21 12:36:20 PM PST 24
Finished Jan 21 12:36:21 PM PST 24
Peak memory 201428 kb
Host smart-94ce3649-2803-4018-afd5-d656de073deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734296370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.2734296370
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.979663268
Short name T53
Test name
Test status
Simulation time 335229566805 ps
CPU time 1996.18 seconds
Started Jan 21 12:35:54 PM PST 24
Finished Jan 21 01:09:13 PM PST 24
Peak memory 202196 kb
Host smart-ac836a19-d1d2-4a20-a43e-dcedbe642e45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979663268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.
979663268
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.3755033789
Short name T229
Test name
Test status
Simulation time 3675782435 ps
CPU time 202.71 seconds
Started Jan 21 12:36:10 PM PST 24
Finished Jan 21 12:39:34 PM PST 24
Peak memory 374012 kb
Host smart-8f050925-43a3-48f1-9d15-c56f42956b36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755033789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.3755033789
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.29462244
Short name T294
Test name
Test status
Simulation time 35438016393 ps
CPU time 91.82 seconds
Started Jan 21 12:36:12 PM PST 24
Finished Jan 21 12:37:45 PM PST 24
Peak memory 210328 kb
Host smart-6b728204-19a8-451d-9c6e-c2239e2f539e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29462244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_esca
lation.29462244
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.3659177226
Short name T501
Test name
Test status
Simulation time 806390741 ps
CPU time 175.58 seconds
Started Jan 21 12:36:09 PM PST 24
Finished Jan 21 12:39:06 PM PST 24
Peak memory 366236 kb
Host smart-9580bc22-2576-4459-9e6a-46f2e9af611b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659177226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.3659177226
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.4204535514
Short name T957
Test name
Test status
Simulation time 6198935788 ps
CPU time 133.66 seconds
Started Jan 21 12:36:24 PM PST 24
Finished Jan 21 12:38:38 PM PST 24
Peak memory 214716 kb
Host smart-34e728c8-6398-4715-83f4-189ea79342c4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204535514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.4204535514
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2093378543
Short name T615
Test name
Test status
Simulation time 55012552101 ps
CPU time 301.33 seconds
Started Jan 21 12:36:10 PM PST 24
Finished Jan 21 12:41:12 PM PST 24
Peak memory 202148 kb
Host smart-54a4943e-c385-49dd-83c4-65d0a5120246
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093378543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2093378543
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.1055101785
Short name T203
Test name
Test status
Simulation time 100350566990 ps
CPU time 1543.52 seconds
Started Jan 21 12:35:48 PM PST 24
Finished Jan 21 01:01:39 PM PST 24
Peak memory 381192 kb
Host smart-7cca232a-9404-4763-97a3-15afb6c71306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055101785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.1055101785
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.180482964
Short name T833
Test name
Test status
Simulation time 1086165714 ps
CPU time 56.94 seconds
Started Jan 21 12:35:54 PM PST 24
Finished Jan 21 12:36:54 PM PST 24
Peak memory 315480 kb
Host smart-9ad99d3a-b4f5-49de-8111-54f6380fff62
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180482964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.s
ram_ctrl_partial_access.180482964
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.3872027676
Short name T544
Test name
Test status
Simulation time 1346127773 ps
CPU time 5.61 seconds
Started Jan 21 12:36:12 PM PST 24
Finished Jan 21 12:36:19 PM PST 24
Peak memory 202276 kb
Host smart-38134ae4-9b78-4522-a139-4e8e947422f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872027676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3872027676
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.3023384780
Short name T607
Test name
Test status
Simulation time 3026253508 ps
CPU time 114.23 seconds
Started Jan 21 12:35:50 PM PST 24
Finished Jan 21 12:37:50 PM PST 24
Peak memory 339544 kb
Host smart-23c53df5-0459-45a4-9b7b-3fc4c86e897e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023384780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3023384780
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.284221319
Short name T264
Test name
Test status
Simulation time 940888162 ps
CPU time 4158.45 seconds
Started Jan 21 12:36:24 PM PST 24
Finished Jan 21 01:45:45 PM PST 24
Peak memory 653900 kb
Host smart-b91b8677-bafe-41df-92c5-4e6c27eb14b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=284221319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.284221319
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3379247416
Short name T901
Test name
Test status
Simulation time 15889394528 ps
CPU time 257.48 seconds
Started Jan 21 12:35:52 PM PST 24
Finished Jan 21 12:40:14 PM PST 24
Peak memory 202108 kb
Host smart-d6011c59-af8e-489a-b756-a0487c057f68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379247416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.3379247416
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4202369916
Short name T955
Test name
Test status
Simulation time 3061329942 ps
CPU time 115.35 seconds
Started Jan 21 12:36:10 PM PST 24
Finished Jan 21 12:38:07 PM PST 24
Peak memory 336096 kb
Host smart-70d6cb04-3280-45fc-b39c-6ba296a3827c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202369916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.4202369916
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1345528940
Short name T946
Test name
Test status
Simulation time 5265675864 ps
CPU time 550.73 seconds
Started Jan 21 12:36:29 PM PST 24
Finished Jan 21 12:45:40 PM PST 24
Peak memory 352372 kb
Host smart-197b0644-dad6-4dc1-8ae6-d5b3abede459
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345528940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.1345528940
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.2139702347
Short name T410
Test name
Test status
Simulation time 13842887 ps
CPU time 0.65 seconds
Started Jan 21 01:42:59 PM PST 24
Finished Jan 21 01:43:01 PM PST 24
Peak memory 202004 kb
Host smart-57466c90-791a-41fb-9487-08239c2c8495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139702347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.2139702347
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.3927780053
Short name T688
Test name
Test status
Simulation time 86218767139 ps
CPU time 839.62 seconds
Started Jan 21 12:36:25 PM PST 24
Finished Jan 21 12:50:26 PM PST 24
Peak memory 202124 kb
Host smart-61b28791-80e3-434b-ad10-542c0f9ceb52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927780053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.3927780053
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.3675294932
Short name T582
Test name
Test status
Simulation time 29353183619 ps
CPU time 75.59 seconds
Started Jan 21 12:36:33 PM PST 24
Finished Jan 21 12:37:49 PM PST 24
Peak memory 202292 kb
Host smart-26cd96e9-3ef9-48e3-8813-d668f868425d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675294932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.3675294932
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.2304541805
Short name T586
Test name
Test status
Simulation time 719317358 ps
CPU time 48.38 seconds
Started Jan 21 12:36:33 PM PST 24
Finished Jan 21 12:37:22 PM PST 24
Peak memory 271624 kb
Host smart-ae7eb960-e22f-4379-8423-5172b39962e2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304541805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.2304541805
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.2980578265
Short name T612
Test name
Test status
Simulation time 5103178978 ps
CPU time 147.13 seconds
Started Jan 21 12:36:38 PM PST 24
Finished Jan 21 12:39:06 PM PST 24
Peak memory 213500 kb
Host smart-55303fcd-c5df-411b-9de5-72b7c7659652
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980578265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.2980578265
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.3156644216
Short name T358
Test name
Test status
Simulation time 114660626931 ps
CPU time 307.34 seconds
Started Jan 21 12:36:38 PM PST 24
Finished Jan 21 12:41:46 PM PST 24
Peak memory 202256 kb
Host smart-ad10feb5-ea6c-408e-8253-d2b1d000fdd0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156644216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.3156644216
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.187229878
Short name T542
Test name
Test status
Simulation time 43357714616 ps
CPU time 1410.22 seconds
Started Jan 21 12:36:21 PM PST 24
Finished Jan 21 12:59:53 PM PST 24
Peak memory 378996 kb
Host smart-7c6de5b2-5db7-495f-a337-0ac2ca3e8fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187229878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multip
le_keys.187229878
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2461600505
Short name T545
Test name
Test status
Simulation time 902368945 ps
CPU time 15.14 seconds
Started Jan 21 12:36:31 PM PST 24
Finished Jan 21 12:36:47 PM PST 24
Peak memory 202096 kb
Host smart-be778177-e795-4239-93f9-a6aaf54a8456
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461600505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2461600505
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.297177394
Short name T908
Test name
Test status
Simulation time 5882199466 ps
CPU time 347.8 seconds
Started Jan 21 12:36:29 PM PST 24
Finished Jan 21 12:42:17 PM PST 24
Peak memory 202260 kb
Host smart-d62b8a27-2b0e-4a8e-80d6-3cf10dea8a74
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297177394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.sram_ctrl_partial_access_b2b.297177394
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.116038056
Short name T656
Test name
Test status
Simulation time 357714162 ps
CPU time 13.06 seconds
Started Jan 21 12:36:38 PM PST 24
Finished Jan 21 12:36:52 PM PST 24
Peak memory 202328 kb
Host smart-8e242be0-147a-4cf5-9a68-eab1d5be0034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116038056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.116038056
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.1737625097
Short name T610
Test name
Test status
Simulation time 61213180322 ps
CPU time 636.38 seconds
Started Jan 21 12:36:39 PM PST 24
Finished Jan 21 12:47:16 PM PST 24
Peak memory 356644 kb
Host smart-c4e679c2-a799-4be7-96c2-505db0ccce42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737625097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1737625097
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.3091277469
Short name T11
Test name
Test status
Simulation time 1190635943 ps
CPU time 22.49 seconds
Started Jan 21 12:36:25 PM PST 24
Finished Jan 21 12:36:49 PM PST 24
Peak memory 202076 kb
Host smart-59465b94-4b5b-4e1e-8a03-a861555b7db1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091277469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3091277469
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all.3890638107
Short name T430
Test name
Test status
Simulation time 50434226775 ps
CPU time 3479.81 seconds
Started Jan 21 12:36:47 PM PST 24
Finished Jan 21 01:34:49 PM PST 24
Peak memory 397448 kb
Host smart-bb1a31c2-e100-407d-b5b0-6927fd87d91c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890638107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.sram_ctrl_stress_all.3890638107
Directory /workspace/18.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2563451887
Short name T345
Test name
Test status
Simulation time 732540117 ps
CPU time 2923.41 seconds
Started Jan 21 12:36:40 PM PST 24
Finished Jan 21 01:25:24 PM PST 24
Peak memory 413368 kb
Host smart-7ba7e1ca-0731-4634-95e0-b9baf409347a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2563451887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2563451887
Directory /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.465429304
Short name T609
Test name
Test status
Simulation time 25820328344 ps
CPU time 452.35 seconds
Started Jan 21 12:36:21 PM PST 24
Finished Jan 21 12:43:54 PM PST 24
Peak memory 202148 kb
Host smart-4294bc33-ed7f-423b-8b6f-37f6378ca08b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465429304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.sram_ctrl_stress_pipeline.465429304
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1608033082
Short name T216
Test name
Test status
Simulation time 1459749250 ps
CPU time 32.1 seconds
Started Jan 21 12:36:32 PM PST 24
Finished Jan 21 12:37:05 PM PST 24
Peak memory 234932 kb
Host smart-4c5fd960-a499-4330-8aeb-a65ee29d6801
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608033082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.1608033082
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1491748468
Short name T466
Test name
Test status
Simulation time 13638961917 ps
CPU time 2414.93 seconds
Started Jan 21 12:36:56 PM PST 24
Finished Jan 21 01:17:12 PM PST 24
Peak memory 378524 kb
Host smart-3bbc5bd3-3ec3-42ee-b327-49687bfea182
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491748468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.1491748468
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.3954468337
Short name T642
Test name
Test status
Simulation time 27600560 ps
CPU time 0.61 seconds
Started Jan 21 12:37:07 PM PST 24
Finished Jan 21 12:37:09 PM PST 24
Peak memory 201588 kb
Host smart-aa0e467c-25dd-455a-b977-f26cbb89be5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954468337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.3954468337
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.2239971107
Short name T910
Test name
Test status
Simulation time 46452169852 ps
CPU time 1714.02 seconds
Started Jan 21 12:36:56 PM PST 24
Finished Jan 21 01:05:31 PM PST 24
Peak memory 379084 kb
Host smart-9927e51c-14d9-4e1c-99c6-ac725bddff6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239971107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab
le.2239971107
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.1310660352
Short name T896
Test name
Test status
Simulation time 45701532471 ps
CPU time 86.57 seconds
Started Jan 21 12:36:55 PM PST 24
Finished Jan 21 12:38:23 PM PST 24
Peak memory 210336 kb
Host smart-40f6eb15-06e2-4e83-889d-0c9526f2fcb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310660352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.1310660352
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.3056352936
Short name T855
Test name
Test status
Simulation time 1568639461 ps
CPU time 154.75 seconds
Started Jan 21 12:36:50 PM PST 24
Finished Jan 21 12:39:25 PM PST 24
Peak memory 367796 kb
Host smart-ec2ff90a-45b3-402b-9ab4-20d636944a45
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056352936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.3056352936
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3045822903
Short name T66
Test name
Test status
Simulation time 1569601905 ps
CPU time 139.04 seconds
Started Jan 21 12:37:05 PM PST 24
Finished Jan 21 12:39:24 PM PST 24
Peak memory 211188 kb
Host smart-f2f128ae-11a3-4b7f-aff1-369e2d2c47b5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045822903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.3045822903
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.6300118
Short name T364
Test name
Test status
Simulation time 28699345988 ps
CPU time 143.78 seconds
Started Jan 21 01:28:32 PM PST 24
Finished Jan 21 01:30:56 PM PST 24
Peak memory 202324 kb
Host smart-f63fe86e-0816-47b5-9560-ccb44e75a4f2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6300118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sra
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_m
em_walk.6300118
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.1513279321
Short name T336
Test name
Test status
Simulation time 38399559119 ps
CPU time 1382.38 seconds
Started Jan 21 12:36:50 PM PST 24
Finished Jan 21 12:59:53 PM PST 24
Peak memory 368836 kb
Host smart-a9c8ea2f-5267-4e50-be59-31de21ab109b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513279321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.1513279321
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.747269909
Short name T55
Test name
Test status
Simulation time 503102772 ps
CPU time 20.47 seconds
Started Jan 21 12:36:46 PM PST 24
Finished Jan 21 12:37:07 PM PST 24
Peak memory 201996 kb
Host smart-fbf4b48d-1986-465e-ae99-f918143adb6c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747269909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_partial_access.747269909
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1932528798
Short name T644
Test name
Test status
Simulation time 17725689724 ps
CPU time 572.97 seconds
Started Jan 21 12:36:47 PM PST 24
Finished Jan 21 12:46:21 PM PST 24
Peak memory 202080 kb
Host smart-44a65fb6-31b0-442f-ae5b-b60715885a86
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932528798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1932528798
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.1701053186
Short name T689
Test name
Test status
Simulation time 351719557 ps
CPU time 12.79 seconds
Started Jan 21 12:37:03 PM PST 24
Finished Jan 21 12:37:17 PM PST 24
Peak memory 202336 kb
Host smart-5221fb7e-e861-43db-bd30-6347a0b2927c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701053186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1701053186
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.4202212232
Short name T823
Test name
Test status
Simulation time 9220559278 ps
CPU time 1356.92 seconds
Started Jan 21 02:30:28 PM PST 24
Finished Jan 21 02:53:10 PM PST 24
Peak memory 378120 kb
Host smart-737768a1-2a68-47c9-9b74-cc026174418b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202212232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4202212232
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.2846212055
Short name T677
Test name
Test status
Simulation time 889186682 ps
CPU time 34.4 seconds
Started Jan 21 12:36:46 PM PST 24
Finished Jan 21 12:37:21 PM PST 24
Peak memory 202076 kb
Host smart-7706e48f-4742-470b-b3ca-4b71c56ace39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846212055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2846212055
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.3865313225
Short name T578
Test name
Test status
Simulation time 78510883745 ps
CPU time 1680.09 seconds
Started Jan 21 12:37:06 PM PST 24
Finished Jan 21 01:05:07 PM PST 24
Peak memory 354540 kb
Host smart-e7a46154-0247-42a3-840a-65aba45d646c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865313225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.3865313225
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3065169978
Short name T752
Test name
Test status
Simulation time 2522890064 ps
CPU time 4146.87 seconds
Started Jan 21 01:19:56 PM PST 24
Finished Jan 21 02:29:04 PM PST 24
Peak memory 770276 kb
Host smart-94d5c66f-62da-42e9-80e1-0ac7d2a87087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3065169978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3065169978
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.4290856900
Short name T359
Test name
Test status
Simulation time 5839601234 ps
CPU time 459.88 seconds
Started Jan 21 12:36:48 PM PST 24
Finished Jan 21 12:44:29 PM PST 24
Peak memory 202136 kb
Host smart-237a1b0c-a736-4bf2-add8-85c8ea420ede
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290856900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.4290856900
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2639225211
Short name T366
Test name
Test status
Simulation time 3586608325 ps
CPU time 87.31 seconds
Started Jan 21 12:36:48 PM PST 24
Finished Jan 21 12:38:16 PM PST 24
Peak memory 329940 kb
Host smart-65efa049-8aab-4acb-acac-8a5b3c0e40c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639225211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.2639225211
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.18165013
Short name T447
Test name
Test status
Simulation time 6643986722 ps
CPU time 1055.23 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:49:59 PM PST 24
Peak memory 376060 kb
Host smart-3343dd54-989a-44b7-afa2-2a8be19a0cbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18165013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.sram_ctrl_access_during_key_req.18165013
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.1839843484
Short name T736
Test name
Test status
Simulation time 10584914 ps
CPU time 0.62 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:32:24 PM PST 24
Peak memory 202004 kb
Host smart-1da9e196-9442-4e1d-886b-2def3b08a08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839843484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.1839843484
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.2077132423
Short name T475
Test name
Test status
Simulation time 27379958980 ps
CPU time 1787.91 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 01:02:11 PM PST 24
Peak memory 201332 kb
Host smart-6a73a749-f281-4252-87e1-7fbd006bcc59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077132423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
2077132423
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.3438699548
Short name T872
Test name
Test status
Simulation time 15106146919 ps
CPU time 355.54 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:38:18 PM PST 24
Peak memory 210344 kb
Host smart-a54a0fa3-6864-4531-9a2b-e46d325ab4ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438699548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.3438699548
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.298320955
Short name T962
Test name
Test status
Simulation time 741124687 ps
CPU time 27.49 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:32:50 PM PST 24
Peak memory 218428 kb
Host smart-0a7fe730-c389-4631-a594-35006e34ac28
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298320955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.sram_ctrl_max_throughput.298320955
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1778063754
Short name T436
Test name
Test status
Simulation time 2780736861 ps
CPU time 72.09 seconds
Started Jan 21 12:31:52 PM PST 24
Finished Jan 21 12:33:27 PM PST 24
Peak memory 211012 kb
Host smart-f4b38347-a81e-402d-87e0-4260323bd65a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778063754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.1778063754
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.35047689
Short name T259
Test name
Test status
Simulation time 24591477120 ps
CPU time 146.48 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:34:49 PM PST 24
Peak memory 202308 kb
Host smart-16b9e2b4-f36d-40c7-8edf-fde118a8f406
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35047689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_m
em_walk.35047689
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.2164658066
Short name T721
Test name
Test status
Simulation time 30744164012 ps
CPU time 2523.18 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 01:14:26 PM PST 24
Peak memory 378356 kb
Host smart-d0fbe649-dcd8-497e-964a-acc8520ae064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164658066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.2164658066
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.908111544
Short name T432
Test name
Test status
Simulation time 640967774 ps
CPU time 28.13 seconds
Started Jan 21 12:31:55 PM PST 24
Finished Jan 21 12:32:45 PM PST 24
Peak memory 277408 kb
Host smart-6b553622-31f0-40e4-95db-efa908aaf66a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908111544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sr
am_ctrl_partial_access.908111544
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3669380168
Short name T333
Test name
Test status
Simulation time 63874476837 ps
CPU time 364.26 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:38:28 PM PST 24
Peak memory 202016 kb
Host smart-b4d209a8-2301-4e58-afd3-82d6ba7a6f4e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669380168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3669380168
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.1003779130
Short name T543
Test name
Test status
Simulation time 4231540024 ps
CPU time 12.97 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:32:36 PM PST 24
Peak memory 202136 kb
Host smart-3727726b-9d7d-4c00-9d17-9bd5845327d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003779130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1003779130
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.784635417
Short name T634
Test name
Test status
Simulation time 24786222498 ps
CPU time 833.19 seconds
Started Jan 21 12:31:55 PM PST 24
Finished Jan 21 12:46:10 PM PST 24
Peak memory 375972 kb
Host smart-dc88af13-4b62-4ca1-b699-f9fa8245c76e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784635417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.784635417
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.441362437
Short name T514
Test name
Test status
Simulation time 1507226912 ps
CPU time 69.09 seconds
Started Jan 21 12:31:59 PM PST 24
Finished Jan 21 12:33:29 PM PST 24
Peak memory 304540 kb
Host smart-522e7892-81e0-42e4-9ceb-bf889f788bcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441362437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.441362437
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3063813396
Short name T646
Test name
Test status
Simulation time 809032971 ps
CPU time 2211.14 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 01:09:14 PM PST 24
Peak memory 411208 kb
Host smart-4515b310-5522-4488-9944-307ca7aa448d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3063813396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3063813396
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2601685506
Short name T815
Test name
Test status
Simulation time 7097861720 ps
CPU time 246.59 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:36:30 PM PST 24
Peak memory 201792 kb
Host smart-53636469-3236-4f2b-9ed9-acb509bdf573
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601685506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.2601685506
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1196474095
Short name T821
Test name
Test status
Simulation time 1568179646 ps
CPU time 88.14 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 12:33:51 PM PST 24
Peak memory 320404 kb
Host smart-bb9cd363-d44a-4245-a358-dc00fca53baf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196474095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1196474095
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1826554478
Short name T739
Test name
Test status
Simulation time 5527796642 ps
CPU time 703.56 seconds
Started Jan 21 12:37:21 PM PST 24
Finished Jan 21 12:49:05 PM PST 24
Peak memory 376920 kb
Host smart-b0682e87-45cf-4904-a4e1-0444461593b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826554478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.1826554478
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.441735333
Short name T301
Test name
Test status
Simulation time 41121647 ps
CPU time 0.62 seconds
Started Jan 21 12:37:37 PM PST 24
Finished Jan 21 12:37:38 PM PST 24
Peak memory 202096 kb
Host smart-279acae6-f5e6-40d4-bcc1-107d4c208266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441735333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.441735333
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.1620512186
Short name T569
Test name
Test status
Simulation time 103786386084 ps
CPU time 1147.97 seconds
Started Jan 21 01:07:36 PM PST 24
Finished Jan 21 01:26:51 PM PST 24
Peak memory 202204 kb
Host smart-32289765-15be-4c2c-8f94-0f05c989d4dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620512186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.1620512186
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.3774342440
Short name T135
Test name
Test status
Simulation time 48115283233 ps
CPU time 838.34 seconds
Started Jan 21 12:49:24 PM PST 24
Finished Jan 21 01:03:23 PM PST 24
Peak memory 376956 kb
Host smart-22af5952-d3d4-430f-a9a6-fab19cfe81f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774342440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.3774342440
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.3885284820
Short name T327
Test name
Test status
Simulation time 11580285986 ps
CPU time 37.77 seconds
Started Jan 21 12:37:20 PM PST 24
Finished Jan 21 12:37:58 PM PST 24
Peak memory 252304 kb
Host smart-64a24333-e4ae-4ca8-a832-d6d30e72d891
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885284820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.3885284820
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2526778671
Short name T86
Test name
Test status
Simulation time 980061903 ps
CPU time 68.7 seconds
Started Jan 21 12:37:34 PM PST 24
Finished Jan 21 12:38:43 PM PST 24
Peak memory 211188 kb
Host smart-b2e0c9b0-c751-4c7d-9db7-8b98b7e4e259
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526778671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2526778671
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.1162555296
Short name T314
Test name
Test status
Simulation time 112070091714 ps
CPU time 162.91 seconds
Started Jan 21 12:37:29 PM PST 24
Finished Jan 21 12:40:12 PM PST 24
Peak memory 202272 kb
Host smart-dd4c6e22-9bf8-4e7b-842d-78fd3290b5fc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162555296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.1162555296
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.754600472
Short name T437
Test name
Test status
Simulation time 14180119460 ps
CPU time 670.42 seconds
Started Jan 21 12:37:06 PM PST 24
Finished Jan 21 12:48:17 PM PST 24
Peak memory 366624 kb
Host smart-503b71c4-b1d8-4353-ac01-c7443143d51f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754600472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip
le_keys.754600472
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.4144691099
Short name T902
Test name
Test status
Simulation time 363469069 ps
CPU time 6.22 seconds
Started Jan 21 12:37:13 PM PST 24
Finished Jan 21 12:37:20 PM PST 24
Peak memory 202136 kb
Host smart-482bfd01-ee46-4a82-b9a1-9ae8756fc6b4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144691099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.4144691099
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2120568886
Short name T935
Test name
Test status
Simulation time 77642324303 ps
CPU time 471.57 seconds
Started Jan 21 12:37:13 PM PST 24
Finished Jan 21 12:45:05 PM PST 24
Peak memory 202052 kb
Host smart-d7be77cb-9da1-46c2-9244-95dd263bd414
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120568886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2120568886
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.4045559244
Short name T705
Test name
Test status
Simulation time 693808521 ps
CPU time 6.6 seconds
Started Jan 21 12:37:27 PM PST 24
Finished Jan 21 12:37:34 PM PST 24
Peak memory 202248 kb
Host smart-abcf2d2d-38ca-4676-a17d-88b02dcdba4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045559244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.4045559244
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.3771289606
Short name T228
Test name
Test status
Simulation time 3686156700 ps
CPU time 900.72 seconds
Started Jan 21 12:37:29 PM PST 24
Finished Jan 21 12:52:30 PM PST 24
Peak memory 372916 kb
Host smart-95e08636-e6b5-4214-a120-8716e64174fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771289606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.3771289606
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.3617126010
Short name T709
Test name
Test status
Simulation time 1443100906 ps
CPU time 11.25 seconds
Started Jan 21 12:37:05 PM PST 24
Finished Jan 21 12:37:16 PM PST 24
Peak memory 202028 kb
Host smart-d5fd02bd-a1ab-4c30-8771-4f471a3cf8f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617126010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3617126010
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4238832419
Short name T836
Test name
Test status
Simulation time 7721067730 ps
CPU time 5781.57 seconds
Started Jan 21 12:37:33 PM PST 24
Finished Jan 21 02:13:56 PM PST 24
Peak memory 693452 kb
Host smart-770f3f26-d780-4ddb-929d-12b431e0c036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4238832419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.4238832419
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3145585539
Short name T405
Test name
Test status
Simulation time 14289190257 ps
CPU time 331.85 seconds
Started Jan 21 01:10:19 PM PST 24
Finished Jan 21 01:15:52 PM PST 24
Peak memory 202304 kb
Host smart-07003a71-8454-4bdf-a607-3d386b4f3b1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145585539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.3145585539
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.648449857
Short name T960
Test name
Test status
Simulation time 3262328452 ps
CPU time 160.69 seconds
Started Jan 21 12:53:53 PM PST 24
Finished Jan 21 12:56:35 PM PST 24
Peak memory 366864 kb
Host smart-0be40219-bd07-4e6d-ad1a-654ee93b132c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648449857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.648449857
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3739948471
Short name T506
Test name
Test status
Simulation time 17368658137 ps
CPU time 1347.91 seconds
Started Jan 21 12:37:44 PM PST 24
Finished Jan 21 01:00:13 PM PST 24
Peak memory 379092 kb
Host smart-8554dbb0-cc1e-4373-81c9-b92457ece676
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739948471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.3739948471
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.4127633271
Short name T590
Test name
Test status
Simulation time 66782241 ps
CPU time 0.7 seconds
Started Jan 21 12:37:54 PM PST 24
Finished Jan 21 12:37:57 PM PST 24
Peak memory 201520 kb
Host smart-95a1de8e-8f13-4d3b-a576-6ad94e88652d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127633271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.4127633271
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.346460617
Short name T800
Test name
Test status
Simulation time 32116589374 ps
CPU time 2131.61 seconds
Started Jan 21 12:37:40 PM PST 24
Finished Jan 21 01:13:12 PM PST 24
Peak memory 202144 kb
Host smart-20591b2a-4710-48d8-9d74-9aa493fbbfc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346460617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.
346460617
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.3681600657
Short name T924
Test name
Test status
Simulation time 75687220334 ps
CPU time 1413.62 seconds
Started Jan 21 12:37:48 PM PST 24
Finished Jan 21 01:01:23 PM PST 24
Peak memory 374296 kb
Host smart-df6baee8-e390-48d6-9b17-06b71fa3c0ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681600657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.3681600657
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.965625735
Short name T899
Test name
Test status
Simulation time 1371205684 ps
CPU time 39.25 seconds
Started Jan 21 12:37:44 PM PST 24
Finished Jan 21 12:38:23 PM PST 24
Peak memory 210248 kb
Host smart-5a58f56b-94ef-4c4f-8796-d2f24eec5394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965625735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc
alation.965625735
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.2018294905
Short name T386
Test name
Test status
Simulation time 2842666158 ps
CPU time 104.17 seconds
Started Jan 21 12:37:45 PM PST 24
Finished Jan 21 12:39:30 PM PST 24
Peak memory 324848 kb
Host smart-c9747c17-2a3d-4601-9e57-1f97ff784222
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018294905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.2018294905
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1863662824
Short name T440
Test name
Test status
Simulation time 2479262099 ps
CPU time 77.64 seconds
Started Jan 21 12:37:51 PM PST 24
Finished Jan 21 12:39:14 PM PST 24
Peak memory 211156 kb
Host smart-c28016c1-6571-4969-9dfb-b78847997169
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863662824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.1863662824
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.3201055674
Short name T467
Test name
Test status
Simulation time 17574179638 ps
CPU time 150.53 seconds
Started Jan 21 12:37:56 PM PST 24
Finished Jan 21 12:40:28 PM PST 24
Peak memory 201544 kb
Host smart-61213670-b991-4cac-9073-417ff2e8b632
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201055674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.3201055674
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.4021797322
Short name T660
Test name
Test status
Simulation time 8923039828 ps
CPU time 668.66 seconds
Started Jan 21 12:37:38 PM PST 24
Finished Jan 21 12:48:48 PM PST 24
Peak memory 371260 kb
Host smart-ef7825c4-8c5e-406d-9690-a67a02e0058d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021797322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.4021797322
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.640955742
Short name T830
Test name
Test status
Simulation time 2115172068 ps
CPU time 14.21 seconds
Started Jan 21 12:37:37 PM PST 24
Finished Jan 21 12:37:52 PM PST 24
Peak memory 202052 kb
Host smart-93d8bad8-7683-4e5a-befe-883780bf7211
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640955742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.s
ram_ctrl_partial_access.640955742
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.479619324
Short name T737
Test name
Test status
Simulation time 53509894690 ps
CPU time 224.39 seconds
Started Jan 21 12:37:45 PM PST 24
Finished Jan 21 12:41:30 PM PST 24
Peak memory 202076 kb
Host smart-5f27b4ac-a2db-4114-a6aa-451f7a9c26f9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479619324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.sram_ctrl_partial_access_b2b.479619324
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.2858930784
Short name T606
Test name
Test status
Simulation time 3064634846 ps
CPU time 14.18 seconds
Started Jan 21 12:37:48 PM PST 24
Finished Jan 21 12:38:03 PM PST 24
Peak memory 202372 kb
Host smart-d70ceb8d-3afc-484a-beac-40fb7e2dc4df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858930784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2858930784
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.4163990564
Short name T133
Test name
Test status
Simulation time 23344437601 ps
CPU time 1106.05 seconds
Started Jan 21 12:37:45 PM PST 24
Finished Jan 21 12:56:12 PM PST 24
Peak memory 378976 kb
Host smart-5cf084d6-0357-4812-b340-6d0e0ee95123
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163990564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.4163990564
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.4275429766
Short name T756
Test name
Test status
Simulation time 1575953148 ps
CPU time 16.27 seconds
Started Jan 21 12:37:36 PM PST 24
Finished Jan 21 12:37:53 PM PST 24
Peak memory 210568 kb
Host smart-5bf43f5a-2935-4e78-afe5-f64146ecee89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275429766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.4275429766
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.505179192
Short name T241
Test name
Test status
Simulation time 246522236 ps
CPU time 4430.73 seconds
Started Jan 21 01:41:24 PM PST 24
Finished Jan 21 02:55:16 PM PST 24
Peak memory 450408 kb
Host smart-c4d89d3f-e713-482e-8463-f1eb56ee486b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=505179192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.505179192
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1702894824
Short name T790
Test name
Test status
Simulation time 10090435429 ps
CPU time 175.66 seconds
Started Jan 21 12:37:36 PM PST 24
Finished Jan 21 12:40:32 PM PST 24
Peak memory 202140 kb
Host smart-a50a9912-c5bf-4e36-a494-bf16f3e08a11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702894824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.1702894824
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2432970917
Short name T816
Test name
Test status
Simulation time 1304187396 ps
CPU time 85.86 seconds
Started Jan 21 12:37:48 PM PST 24
Finished Jan 21 12:39:16 PM PST 24
Peak memory 319760 kb
Host smart-50d225b9-aa83-4ec9-aa84-0eb0aa5d517d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432970917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2432970917
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.268925763
Short name T758
Test name
Test status
Simulation time 113175663825 ps
CPU time 1256.66 seconds
Started Jan 21 12:57:00 PM PST 24
Finished Jan 21 01:18:01 PM PST 24
Peak memory 370940 kb
Host smart-5e9d6243-8908-4ec9-9b28-4d7d6b1ad62a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268925763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 22.sram_ctrl_access_during_key_req.268925763
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.24279947
Short name T480
Test name
Test status
Simulation time 54101013 ps
CPU time 0.67 seconds
Started Jan 21 12:38:15 PM PST 24
Finished Jan 21 12:38:16 PM PST 24
Peak memory 202064 kb
Host smart-07882da4-aabe-4ad7-b11e-87f3a03f245c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_alert_test.24279947
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.3062495120
Short name T281
Test name
Test status
Simulation time 11332226452 ps
CPU time 47.67 seconds
Started Jan 21 01:53:23 PM PST 24
Finished Jan 21 01:54:11 PM PST 24
Peak memory 210700 kb
Host smart-e97d4c30-d560-43cb-9e6d-a35fff7ec018
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062495120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.3062495120
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.2883641584
Short name T842
Test name
Test status
Simulation time 776606999 ps
CPU time 44.57 seconds
Started Jan 21 12:53:30 PM PST 24
Finished Jan 21 12:54:17 PM PST 24
Peak memory 267620 kb
Host smart-2cff7529-815d-4872-9a44-51ddb9701475
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883641584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.2883641584
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.3822786273
Short name T546
Test name
Test status
Simulation time 29257095125 ps
CPU time 166.49 seconds
Started Jan 21 12:38:07 PM PST 24
Finished Jan 21 12:40:56 PM PST 24
Peak memory 214816 kb
Host smart-1d79a8b8-9b80-4dbc-9207-7a722a7138d6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822786273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.3822786273
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.1983636470
Short name T239
Test name
Test status
Simulation time 57278168535 ps
CPU time 298.42 seconds
Started Jan 21 12:38:07 PM PST 24
Finished Jan 21 12:43:08 PM PST 24
Peak memory 202164 kb
Host smart-f1bb01e5-e505-4608-9b16-163c5e7b15b2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983636470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.1983636470
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.4276192728
Short name T857
Test name
Test status
Simulation time 26485059470 ps
CPU time 1691.37 seconds
Started Jan 21 12:37:52 PM PST 24
Finished Jan 21 01:06:08 PM PST 24
Peak memory 379000 kb
Host smart-31868acf-31ff-4167-ad43-aab0b3b7dec7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276192728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.4276192728
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.267746497
Short name T889
Test name
Test status
Simulation time 994999303 ps
CPU time 144.27 seconds
Started Jan 21 12:37:52 PM PST 24
Finished Jan 21 12:40:21 PM PST 24
Peak memory 372740 kb
Host smart-af7c3fa1-fe7e-4c27-bbad-ee1eda75ce93
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267746497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s
ram_ctrl_partial_access.267746497
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3733994899
Short name T936
Test name
Test status
Simulation time 47124648521 ps
CPU time 354.69 seconds
Started Jan 21 12:37:59 PM PST 24
Finished Jan 21 12:43:56 PM PST 24
Peak memory 202252 kb
Host smart-9640269f-0691-48cf-974c-16f7376adf3c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733994899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.3733994899
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.3478793966
Short name T321
Test name
Test status
Simulation time 363300049 ps
CPU time 6.34 seconds
Started Jan 21 01:41:20 PM PST 24
Finished Jan 21 01:41:27 PM PST 24
Peak memory 202360 kb
Host smart-6600be2f-a72a-4eea-b00d-d43dd9bdd720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478793966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3478793966
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.945576603
Short name T576
Test name
Test status
Simulation time 2037352446 ps
CPU time 728.6 seconds
Started Jan 21 12:38:05 PM PST 24
Finished Jan 21 12:50:18 PM PST 24
Peak memory 357464 kb
Host smart-c2433d4a-2b77-40d7-97e5-9f7e9ed5d6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945576603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.945576603
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.807481337
Short name T654
Test name
Test status
Simulation time 9915473729 ps
CPU time 102.77 seconds
Started Jan 21 12:37:53 PM PST 24
Finished Jan 21 12:39:39 PM PST 24
Peak memory 348692 kb
Host smart-ace43490-2b6c-4f93-86fc-4ab8f182e0fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807481337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.807481337
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3154538764
Short name T462
Test name
Test status
Simulation time 13415417524 ps
CPU time 3871.17 seconds
Started Jan 21 12:38:07 PM PST 24
Finished Jan 21 01:42:41 PM PST 24
Peak memory 750976 kb
Host smart-c3ae0b85-79a8-4794-a545-50dace21c8e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3154538764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3154538764
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2622507742
Short name T279
Test name
Test status
Simulation time 22181060211 ps
CPU time 307.02 seconds
Started Jan 21 12:37:53 PM PST 24
Finished Jan 21 12:43:04 PM PST 24
Peak memory 202180 kb
Host smart-4a61aa5b-be8f-41d4-af2a-9a3efcab5b6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622507742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.2622507742
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2770339865
Short name T401
Test name
Test status
Simulation time 2933679513 ps
CPU time 59.81 seconds
Started Jan 21 12:37:56 PM PST 24
Finished Jan 21 12:38:57 PM PST 24
Peak memory 293356 kb
Host smart-d0af53b6-402b-49e0-84b3-949b701f091d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770339865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.2770339865
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.4096893185
Short name T400
Test name
Test status
Simulation time 118493261 ps
CPU time 0.63 seconds
Started Jan 21 12:38:40 PM PST 24
Finished Jan 21 12:38:41 PM PST 24
Peak memory 202024 kb
Host smart-9d7bb8aa-894d-4670-a048-a4ad97ad6fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096893185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.4096893185
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.3377787004
Short name T273
Test name
Test status
Simulation time 104391824804 ps
CPU time 899.49 seconds
Started Jan 21 12:38:14 PM PST 24
Finished Jan 21 12:53:15 PM PST 24
Peak memory 202276 kb
Host smart-8ebb14de-ba12-4c0c-a40f-960fad4a3dc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377787004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.3377787004
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.3594981348
Short name T792
Test name
Test status
Simulation time 95097275850 ps
CPU time 1230.88 seconds
Started Jan 21 12:38:24 PM PST 24
Finished Jan 21 12:59:00 PM PST 24
Peak memory 374348 kb
Host smart-8f30d9df-46f7-430c-97af-2139ae14ebcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594981348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.3594981348
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.2641420912
Short name T881
Test name
Test status
Simulation time 1931731332 ps
CPU time 14.39 seconds
Started Jan 21 12:38:27 PM PST 24
Finished Jan 21 12:38:44 PM PST 24
Peak memory 202180 kb
Host smart-9c535277-707a-4ea2-b09c-4fd6109f1f73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641420912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.2641420912
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.548949459
Short name T420
Test name
Test status
Simulation time 6328292536 ps
CPU time 38.74 seconds
Started Jan 21 12:38:18 PM PST 24
Finished Jan 21 12:38:57 PM PST 24
Peak memory 256992 kb
Host smart-1c888185-61bb-487f-b79f-15bf1454452d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548949459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.sram_ctrl_max_throughput.548949459
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1479995582
Short name T838
Test name
Test status
Simulation time 12097052896 ps
CPU time 77.31 seconds
Started Jan 21 12:38:32 PM PST 24
Finished Jan 21 12:39:51 PM PST 24
Peak memory 211084 kb
Host smart-319f33f2-cf15-43f5-9c6b-45748c04e895
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479995582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.1479995582
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.3705947638
Short name T695
Test name
Test status
Simulation time 42991991362 ps
CPU time 151.81 seconds
Started Jan 21 12:38:31 PM PST 24
Finished Jan 21 12:41:05 PM PST 24
Peak memory 202304 kb
Host smart-66a98676-5d74-4921-b6c9-a59090c19e2f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705947638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.3705947638
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.2377337184
Short name T536
Test name
Test status
Simulation time 41241263641 ps
CPU time 841.19 seconds
Started Jan 21 12:38:14 PM PST 24
Finished Jan 21 12:52:16 PM PST 24
Peak memory 375020 kb
Host smart-15941a37-e53c-4036-b5d9-c99a449f51c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377337184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.2377337184
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.666836894
Short name T539
Test name
Test status
Simulation time 737529193 ps
CPU time 41.01 seconds
Started Jan 21 12:38:14 PM PST 24
Finished Jan 21 12:38:56 PM PST 24
Peak memory 250044 kb
Host smart-e9a62402-cd64-4963-905c-2f4608661cc6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666836894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.s
ram_ctrl_partial_access.666836894
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2177692438
Short name T643
Test name
Test status
Simulation time 8474707040 ps
CPU time 267.13 seconds
Started Jan 21 12:38:18 PM PST 24
Finished Jan 21 12:42:46 PM PST 24
Peak memory 202264 kb
Host smart-d70fa28c-b2c1-47de-a523-0d704b47da02
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177692438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.2177692438
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.2499144046
Short name T928
Test name
Test status
Simulation time 346734021 ps
CPU time 13.21 seconds
Started Jan 21 12:38:26 PM PST 24
Finished Jan 21 12:38:43 PM PST 24
Peak memory 202448 kb
Host smart-962005e8-73fe-426f-8070-adea67e368ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499144046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2499144046
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.1378432187
Short name T685
Test name
Test status
Simulation time 2353554718 ps
CPU time 570.76 seconds
Started Jan 21 12:38:22 PM PST 24
Finished Jan 21 12:47:59 PM PST 24
Peak memory 372012 kb
Host smart-577b0e8d-8e08-492b-9d79-ef5dc3f10172
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378432187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1378432187
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.3109724899
Short name T269
Test name
Test status
Simulation time 393388506 ps
CPU time 37.03 seconds
Started Jan 21 01:30:43 PM PST 24
Finished Jan 21 01:31:20 PM PST 24
Peak memory 278868 kb
Host smart-0ffd3594-1dac-4afd-9ca5-1a9e30050682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109724899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.3109724899
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.1513463688
Short name T496
Test name
Test status
Simulation time 49911555231 ps
CPU time 4243.55 seconds
Started Jan 21 12:38:38 PM PST 24
Finished Jan 21 01:49:23 PM PST 24
Peak memory 379944 kb
Host smart-98d8fd28-e14a-4ad9-be97-dbc73a771950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513463688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.1513463688
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3551370586
Short name T306
Test name
Test status
Simulation time 3130224245 ps
CPU time 1162.45 seconds
Started Jan 21 12:38:31 PM PST 24
Finished Jan 21 12:57:56 PM PST 24
Peak memory 415552 kb
Host smart-0b6abbbd-b89e-4cc6-8650-9b872cd72ea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3551370586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3551370586
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4088739068
Short name T497
Test name
Test status
Simulation time 9787085591 ps
CPU time 371.73 seconds
Started Jan 21 12:38:15 PM PST 24
Finished Jan 21 12:44:28 PM PST 24
Peak memory 202112 kb
Host smart-2641a3f9-0945-47ef-b972-551649914af5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088739068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.4088739068
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2965464900
Short name T809
Test name
Test status
Simulation time 3195982126 ps
CPU time 78.8 seconds
Started Jan 21 12:38:15 PM PST 24
Finished Jan 21 12:39:35 PM PST 24
Peak memory 295256 kb
Host smart-645b03eb-bfcf-46e7-9af6-e02b79b1f6c1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965464900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2965464900
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2375565123
Short name T249
Test name
Test status
Simulation time 5246171943 ps
CPU time 1044.53 seconds
Started Jan 21 12:38:52 PM PST 24
Finished Jan 21 12:56:17 PM PST 24
Peak memory 372992 kb
Host smart-8aae181a-6de2-4b39-a176-4df984709df5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375565123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.2375565123
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.438695744
Short name T3
Test name
Test status
Simulation time 38338657 ps
CPU time 0.63 seconds
Started Jan 21 12:39:00 PM PST 24
Finished Jan 21 12:39:01 PM PST 24
Peak memory 202036 kb
Host smart-bc48edbd-afac-4650-b3dc-a6d1bcdecb84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438695744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.438695744
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.99011416
Short name T340
Test name
Test status
Simulation time 11066708343 ps
CPU time 739.19 seconds
Started Jan 21 12:38:52 PM PST 24
Finished Jan 21 12:51:12 PM PST 24
Peak memory 202276 kb
Host smart-fb3c5042-491b-43f3-87d6-8f2185d70bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99011416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.99011416
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.3657910421
Short name T456
Test name
Test status
Simulation time 24331037424 ps
CPU time 148.86 seconds
Started Jan 21 12:38:46 PM PST 24
Finished Jan 21 12:41:15 PM PST 24
Peak memory 210340 kb
Host smart-947939bc-cba0-45e9-8248-9818c0a3716d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657910421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.3657910421
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2953386073
Short name T12
Test name
Test status
Simulation time 1463159029 ps
CPU time 57.83 seconds
Started Jan 21 01:03:27 PM PST 24
Finished Jan 21 01:04:26 PM PST 24
Peak memory 284028 kb
Host smart-28c8ea20-c6f5-4cd9-8fc1-70cb2088920b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953386073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2953386073
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3307821608
Short name T806
Test name
Test status
Simulation time 2695792795 ps
CPU time 77.25 seconds
Started Jan 21 12:38:54 PM PST 24
Finished Jan 21 12:40:12 PM PST 24
Peak memory 211280 kb
Host smart-633666af-63bd-461e-8743-3b64b6508ca2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307821608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.3307821608
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.684728323
Short name T782
Test name
Test status
Simulation time 28718899198 ps
CPU time 148.18 seconds
Started Jan 21 12:38:55 PM PST 24
Finished Jan 21 12:41:24 PM PST 24
Peak memory 202396 kb
Host smart-d42f6340-2702-4a3a-907a-c4270d1a845f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684728323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.684728323
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.491287978
Short name T916
Test name
Test status
Simulation time 9573830998 ps
CPU time 1325.49 seconds
Started Jan 21 12:38:45 PM PST 24
Finished Jan 21 01:00:51 PM PST 24
Peak memory 379244 kb
Host smart-cbb2610d-b655-48a5-9e95-bb85df5dbba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491287978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip
le_keys.491287978
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.765997992
Short name T189
Test name
Test status
Simulation time 497431398 ps
CPU time 111.69 seconds
Started Jan 21 12:38:47 PM PST 24
Finished Jan 21 12:40:39 PM PST 24
Peak memory 330868 kb
Host smart-92e27dc4-50db-4729-8793-50fba692c43d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765997992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.s
ram_ctrl_partial_access.765997992
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.4253296691
Short name T109
Test name
Test status
Simulation time 105206518984 ps
CPU time 249.41 seconds
Started Jan 21 12:38:46 PM PST 24
Finished Jan 21 12:42:56 PM PST 24
Peak memory 202088 kb
Host smart-251ccdf9-017f-487b-86e1-4f0346dfec35
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253296691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.4253296691
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.2896384944
Short name T794
Test name
Test status
Simulation time 1993655085 ps
CPU time 6.47 seconds
Started Jan 21 12:38:55 PM PST 24
Finished Jan 21 12:39:03 PM PST 24
Peak memory 202332 kb
Host smart-c052bb88-1199-41a4-8cc8-9f4b70a3fadb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896384944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2896384944
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.154035484
Short name T589
Test name
Test status
Simulation time 2840994536 ps
CPU time 1315.04 seconds
Started Jan 21 12:38:53 PM PST 24
Finished Jan 21 01:00:49 PM PST 24
Peak memory 378012 kb
Host smart-e329e523-59cf-4560-8358-580c2f55511d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154035484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.154035484
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.3752409318
Short name T716
Test name
Test status
Simulation time 1317496437 ps
CPU time 20.36 seconds
Started Jan 21 12:38:39 PM PST 24
Finished Jan 21 12:39:00 PM PST 24
Peak memory 202036 kb
Host smart-e61da395-8da5-47da-ac69-b295b813deca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752409318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3752409318
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2178194873
Short name T483
Test name
Test status
Simulation time 1861290095 ps
CPU time 2302.59 seconds
Started Jan 21 12:39:01 PM PST 24
Finished Jan 21 01:17:25 PM PST 24
Peak memory 431788 kb
Host smart-49f390dc-154b-4788-8e93-a3a694a137df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2178194873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2178194873
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.2032112449
Short name T521
Test name
Test status
Simulation time 4249074274 ps
CPU time 329.63 seconds
Started Jan 21 02:45:19 PM PST 24
Finished Jan 21 02:50:49 PM PST 24
Peak memory 202364 kb
Host smart-64eddbb8-46f9-4450-bb70-249ee7322c83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032112449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.2032112449
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.641720366
Short name T512
Test name
Test status
Simulation time 1686334827 ps
CPU time 107.08 seconds
Started Jan 21 12:38:47 PM PST 24
Finished Jan 21 12:40:35 PM PST 24
Peak memory 327188 kb
Host smart-e0837e3f-9fd5-4944-bc31-d7d6ee3edea2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641720366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_throughput_w_partial_write.641720366
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.399277223
Short name T9
Test name
Test status
Simulation time 6094941056 ps
CPU time 590.87 seconds
Started Jan 21 12:39:12 PM PST 24
Finished Jan 21 12:49:04 PM PST 24
Peak memory 350340 kb
Host smart-8c627340-2110-420e-b2ac-41a65eeecfbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399277223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.sram_ctrl_access_during_key_req.399277223
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.951843982
Short name T755
Test name
Test status
Simulation time 11347455 ps
CPU time 0.68 seconds
Started Jan 21 12:56:27 PM PST 24
Finished Jan 21 12:56:28 PM PST 24
Peak memory 202028 kb
Host smart-74872ada-66e9-4939-841b-d6a09a1b7419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951843982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.951843982
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.3024374658
Short name T930
Test name
Test status
Simulation time 187062277109 ps
CPU time 1452.66 seconds
Started Jan 21 12:39:01 PM PST 24
Finished Jan 21 01:03:15 PM PST 24
Peak memory 202096 kb
Host smart-97d4085d-c69d-4fb8-b2d9-e022c8e04979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024374658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.3024374658
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.3377645654
Short name T443
Test name
Test status
Simulation time 15292477194 ps
CPU time 103.35 seconds
Started Jan 21 12:39:09 PM PST 24
Finished Jan 21 12:40:54 PM PST 24
Peak memory 210304 kb
Host smart-81213f18-51a3-44d6-90cd-9affba15cf63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377645654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.3377645654
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.1004786582
Short name T912
Test name
Test status
Simulation time 1595849957 ps
CPU time 181.22 seconds
Started Jan 21 12:39:09 PM PST 24
Finished Jan 21 12:42:11 PM PST 24
Peak memory 365684 kb
Host smart-28d9701f-849c-492d-8c76-40f1ddb83789
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004786582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.1004786582
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1091061593
Short name T878
Test name
Test status
Simulation time 9934039964 ps
CPU time 153.84 seconds
Started Jan 21 12:39:26 PM PST 24
Finished Jan 21 12:42:01 PM PST 24
Peak memory 210572 kb
Host smart-70b5c148-1860-40d3-8819-44a04c944826
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091061593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.1091061593
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.1962415577
Short name T653
Test name
Test status
Simulation time 65506500677 ps
CPU time 299.16 seconds
Started Jan 21 12:39:19 PM PST 24
Finished Jan 21 12:44:19 PM PST 24
Peak memory 202172 kb
Host smart-152e334e-f1b5-4560-9f20-8f8716433eb1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962415577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.1962415577
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.433195161
Short name T142
Test name
Test status
Simulation time 3111775290 ps
CPU time 83.47 seconds
Started Jan 21 12:39:02 PM PST 24
Finished Jan 21 12:40:26 PM PST 24
Peak memory 252836 kb
Host smart-7281a6cf-3fe1-4458-8015-ff37464bd7aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433195161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multip
le_keys.433195161
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.3909414510
Short name T238
Test name
Test status
Simulation time 1515858132 ps
CPU time 47.99 seconds
Started Jan 21 12:39:11 PM PST 24
Finished Jan 21 12:40:01 PM PST 24
Peak memory 295124 kb
Host smart-7dde1f07-628c-4933-96d9-4eadaf8bf5b0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909414510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.3909414510
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.4076812960
Short name T492
Test name
Test status
Simulation time 13524063392 ps
CPU time 326.92 seconds
Started Jan 21 12:39:11 PM PST 24
Finished Jan 21 12:44:39 PM PST 24
Peak memory 202056 kb
Host smart-a62e79b2-283c-4a65-bf59-7d4f9861490d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076812960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.4076812960
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.3355769110
Short name T398
Test name
Test status
Simulation time 680330087 ps
CPU time 13.26 seconds
Started Jan 21 12:39:19 PM PST 24
Finished Jan 21 12:39:33 PM PST 24
Peak memory 202332 kb
Host smart-fca381bd-c736-4a8c-a689-44a037910ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355769110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3355769110
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.2728146149
Short name T204
Test name
Test status
Simulation time 17482655083 ps
CPU time 927.99 seconds
Started Jan 21 12:39:19 PM PST 24
Finished Jan 21 12:54:48 PM PST 24
Peak memory 351404 kb
Host smart-76d2733f-f922-4faf-8f34-66814c7bba6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728146149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2728146149
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.661912803
Short name T559
Test name
Test status
Simulation time 766533707 ps
CPU time 10.96 seconds
Started Jan 21 12:39:00 PM PST 24
Finished Jan 21 12:39:12 PM PST 24
Peak memory 202120 kb
Host smart-9ba3e9bb-9b03-426e-8e56-e2db330239bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661912803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.661912803
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.1137384224
Short name T640
Test name
Test status
Simulation time 187980004573 ps
CPU time 5447.01 seconds
Started Jan 21 01:46:03 PM PST 24
Finished Jan 21 03:16:51 PM PST 24
Peak memory 376996 kb
Host smart-78cf9d29-adab-4ecd-a2c8-7dc4e445c8a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137384224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.1137384224
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3549243683
Short name T291
Test name
Test status
Simulation time 1706351310 ps
CPU time 5880.08 seconds
Started Jan 21 12:39:27 PM PST 24
Finished Jan 21 02:17:28 PM PST 24
Peak memory 675760 kb
Host smart-6edaf15e-3646-4974-b00c-33033d8f26a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3549243683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3549243683
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.750299752
Short name T917
Test name
Test status
Simulation time 17889544140 ps
CPU time 215.3 seconds
Started Jan 21 12:39:10 PM PST 24
Finished Jan 21 12:42:46 PM PST 24
Peak memory 202084 kb
Host smart-0e0f3b1a-9f99-4b90-9831-dc2853874e1a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750299752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.sram_ctrl_stress_pipeline.750299752
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3419167001
Short name T396
Test name
Test status
Simulation time 1432408408 ps
CPU time 35.72 seconds
Started Jan 21 12:39:11 PM PST 24
Finished Jan 21 12:39:48 PM PST 24
Peak memory 250984 kb
Host smart-49945f2e-161a-49ca-b2bb-fefb48dddbe0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419167001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3419167001
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3777257112
Short name T337
Test name
Test status
Simulation time 24809391520 ps
CPU time 1018.91 seconds
Started Jan 21 12:39:38 PM PST 24
Finished Jan 21 12:56:37 PM PST 24
Peak memory 376936 kb
Host smart-d2de1c57-3e53-4b4d-a1ae-eae233bc42b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777257112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.3777257112
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.1778882881
Short name T24
Test name
Test status
Simulation time 22358772 ps
CPU time 0.64 seconds
Started Jan 21 12:39:48 PM PST 24
Finished Jan 21 12:39:49 PM PST 24
Peak memory 202024 kb
Host smart-cf58b471-66a2-4a82-893f-363e9d73adb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778882881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.1778882881
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.1102185569
Short name T581
Test name
Test status
Simulation time 265549621384 ps
CPU time 1871.1 seconds
Started Jan 21 12:39:34 PM PST 24
Finished Jan 21 01:10:46 PM PST 24
Peak memory 202200 kb
Host smart-ecd4300c-8daf-47cb-94fb-e9690d79e613
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102185569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.1102185569
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.1946562396
Short name T409
Test name
Test status
Simulation time 14227422947 ps
CPU time 923.68 seconds
Started Jan 21 02:58:12 PM PST 24
Finished Jan 21 03:13:45 PM PST 24
Peak memory 377092 kb
Host smart-74284de2-4f1c-4c69-92c9-28058f4eadc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946562396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.1946562396
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.3719170401
Short name T26
Test name
Test status
Simulation time 41079423584 ps
CPU time 261.16 seconds
Started Jan 21 12:53:48 PM PST 24
Finished Jan 21 12:58:11 PM PST 24
Peak memory 210396 kb
Host smart-1e3d2c52-efc1-4343-b28c-4cb9d28ea66c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719170401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.3719170401
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.747230758
Short name T829
Test name
Test status
Simulation time 1548824117 ps
CPU time 97.01 seconds
Started Jan 21 12:39:35 PM PST 24
Finished Jan 21 12:41:13 PM PST 24
Peak memory 322760 kb
Host smart-cda73535-03b6-4c45-a7fe-1e37456bdf5f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747230758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.sram_ctrl_max_throughput.747230758
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2045336262
Short name T861
Test name
Test status
Simulation time 6516093841 ps
CPU time 134.18 seconds
Started Jan 21 12:39:41 PM PST 24
Finished Jan 21 12:41:56 PM PST 24
Peak memory 211288 kb
Host smart-5ac52f1f-c7ee-4cfa-a835-295ea236a680
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045336262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.2045336262
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2763664369
Short name T776
Test name
Test status
Simulation time 229632941824 ps
CPU time 364.52 seconds
Started Jan 21 01:03:44 PM PST 24
Finished Jan 21 01:09:50 PM PST 24
Peak memory 202348 kb
Host smart-d7cc2f19-ed83-4804-8f6a-2b984cb56611
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763664369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2763664369
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.227123556
Short name T678
Test name
Test status
Simulation time 7531955226 ps
CPU time 1181.71 seconds
Started Jan 21 12:39:34 PM PST 24
Finished Jan 21 12:59:17 PM PST 24
Peak memory 376012 kb
Host smart-2223010e-6364-4b99-8b8b-efc1cb0be6d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227123556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multip
le_keys.227123556
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.1347977058
Short name T531
Test name
Test status
Simulation time 19793889448 ps
CPU time 42.62 seconds
Started Jan 21 01:30:12 PM PST 24
Finished Jan 21 01:30:56 PM PST 24
Peak memory 273188 kb
Host smart-6847d875-9358-4de9-9a12-4118be529ae5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347977058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.1347977058
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2246444742
Short name T663
Test name
Test status
Simulation time 5625564404 ps
CPU time 365.04 seconds
Started Jan 21 01:34:31 PM PST 24
Finished Jan 21 01:40:37 PM PST 24
Peak memory 202524 kb
Host smart-f5c59eec-4e7a-4b31-bdcc-8a24083d7fba
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246444742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.2246444742
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.387057875
Short name T323
Test name
Test status
Simulation time 446747361 ps
CPU time 5.29 seconds
Started Jan 21 12:39:45 PM PST 24
Finished Jan 21 12:39:50 PM PST 24
Peak memory 202300 kb
Host smart-fe0651d4-5894-4295-aa2a-d8a05d41ca01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387057875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.387057875
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.2846036931
Short name T297
Test name
Test status
Simulation time 8447024827 ps
CPU time 1249.83 seconds
Started Jan 21 12:39:40 PM PST 24
Finished Jan 21 01:00:30 PM PST 24
Peak memory 375932 kb
Host smart-e7751e76-465c-414e-b0b0-03f648e785c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846036931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2846036931
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.32131357
Short name T233
Test name
Test status
Simulation time 451964240 ps
CPU time 96.11 seconds
Started Jan 21 01:25:30 PM PST 24
Finished Jan 21 01:27:07 PM PST 24
Peak memory 341948 kb
Host smart-287e5175-3b37-470f-933a-ab0e56e900ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32131357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.32131357
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3327839572
Short name T893
Test name
Test status
Simulation time 1916449956 ps
CPU time 4522.87 seconds
Started Jan 21 12:39:40 PM PST 24
Finished Jan 21 01:55:04 PM PST 24
Peak memory 690840 kb
Host smart-8aee0332-3ae2-41db-8d69-c7b8bc725408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3327839572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3327839572
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.260855096
Short name T237
Test name
Test status
Simulation time 32119490100 ps
CPU time 301.97 seconds
Started Jan 21 12:39:36 PM PST 24
Finished Jan 21 12:44:39 PM PST 24
Peak memory 202112 kb
Host smart-407018b6-c96c-4f66-a469-86c53bda7642
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260855096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_stress_pipeline.260855096
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2920550247
Short name T383
Test name
Test status
Simulation time 5590045194 ps
CPU time 146.02 seconds
Started Jan 21 12:39:33 PM PST 24
Finished Jan 21 12:41:59 PM PST 24
Peak memory 364696 kb
Host smart-23620fea-794d-4195-bbc4-c23cbaa9069b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920550247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.2920550247
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.250477031
Short name T493
Test name
Test status
Simulation time 3395157505 ps
CPU time 247 seconds
Started Jan 21 12:40:00 PM PST 24
Finished Jan 21 12:44:08 PM PST 24
Peak memory 371912 kb
Host smart-0f089c6b-54bb-45a5-8559-7a9f4317c299
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250477031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.sram_ctrl_access_during_key_req.250477031
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.1191643237
Short name T859
Test name
Test status
Simulation time 21015938 ps
CPU time 0.66 seconds
Started Jan 21 12:40:18 PM PST 24
Finished Jan 21 12:40:20 PM PST 24
Peak memory 202024 kb
Host smart-6dc99351-2729-492f-bccb-d78e2c3b8160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191643237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.1191643237
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.949500025
Short name T580
Test name
Test status
Simulation time 63422588884 ps
CPU time 1301.03 seconds
Started Jan 21 12:39:54 PM PST 24
Finished Jan 21 01:01:36 PM PST 24
Peak memory 202140 kb
Host smart-d9af4ac1-bb9f-4eca-8b45-d63830b8c79e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949500025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.
949500025
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.3381352882
Short name T906
Test name
Test status
Simulation time 41762715097 ps
CPU time 505.62 seconds
Started Jan 21 12:39:59 PM PST 24
Finished Jan 21 12:48:26 PM PST 24
Peak memory 371852 kb
Host smart-9186b1d5-c694-45b7-89a7-d9cb45197357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381352882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.3381352882
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.3057618848
Short name T343
Test name
Test status
Simulation time 2954543747 ps
CPU time 29.2 seconds
Started Jan 21 12:39:51 PM PST 24
Finished Jan 21 12:40:21 PM PST 24
Peak memory 224132 kb
Host smart-3f66b009-76ef-4609-8f67-b5a88627e7e0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057618848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.3057618848
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2528167474
Short name T363
Test name
Test status
Simulation time 5580407369 ps
CPU time 122.47 seconds
Started Jan 21 12:40:07 PM PST 24
Finished Jan 21 12:42:11 PM PST 24
Peak memory 210680 kb
Host smart-47111104-bfe0-446e-8dee-98df43dd8978
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528167474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.2528167474
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.2234121383
Short name T338
Test name
Test status
Simulation time 172297439959 ps
CPU time 330.27 seconds
Started Jan 21 12:40:09 PM PST 24
Finished Jan 21 12:45:46 PM PST 24
Peak memory 202420 kb
Host smart-96398270-0449-4bcd-b6a4-b53f22cabaae
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234121383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.2234121383
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.619995042
Short name T894
Test name
Test status
Simulation time 6484568061 ps
CPU time 902.81 seconds
Started Jan 21 12:39:48 PM PST 24
Finished Jan 21 12:54:52 PM PST 24
Peak memory 375988 kb
Host smart-39eed026-1146-4eba-8b38-d83020156d41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619995042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip
le_keys.619995042
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.2411645795
Short name T898
Test name
Test status
Simulation time 1345121970 ps
CPU time 125.63 seconds
Started Jan 21 12:39:55 PM PST 24
Finished Jan 21 12:42:01 PM PST 24
Peak memory 373008 kb
Host smart-f9424828-52cd-4395-9f63-6aeafdd763c4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411645795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.2411645795
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2212566199
Short name T352
Test name
Test status
Simulation time 30434938106 ps
CPU time 378.87 seconds
Started Jan 21 12:39:51 PM PST 24
Finished Jan 21 12:46:10 PM PST 24
Peak memory 202100 kb
Host smart-3aec64ab-dbf4-45d0-bc16-61d7569a9fb7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212566199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.2212566199
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.2211448611
Short name T883
Test name
Test status
Simulation time 1523995981 ps
CPU time 6.09 seconds
Started Jan 21 12:40:08 PM PST 24
Finished Jan 21 12:40:15 PM PST 24
Peak memory 202276 kb
Host smart-d149b824-b8a7-435f-b7bb-909f24f9b7c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211448611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2211448611
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.2410514933
Short name T503
Test name
Test status
Simulation time 10464689993 ps
CPU time 465.27 seconds
Started Jan 21 12:39:58 PM PST 24
Finished Jan 21 12:47:44 PM PST 24
Peak memory 355456 kb
Host smart-e3a1c76e-58e9-45da-aee9-64c09cf0a580
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410514933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2410514933
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.2193176583
Short name T367
Test name
Test status
Simulation time 787489051 ps
CPU time 110.24 seconds
Started Jan 21 12:39:49 PM PST 24
Finished Jan 21 12:41:40 PM PST 24
Peak memory 348240 kb
Host smart-055ab05a-591c-4127-a866-70a1c3bf61fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193176583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2193176583
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.1850435634
Short name T485
Test name
Test status
Simulation time 624322889273 ps
CPU time 3602.01 seconds
Started Jan 21 12:40:09 PM PST 24
Finished Jan 21 01:40:17 PM PST 24
Peak memory 349912 kb
Host smart-fff6f139-5720-4934-a9ea-5abc5456a257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850435634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.1850435634
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2160429525
Short name T434
Test name
Test status
Simulation time 1603732211 ps
CPU time 3248.1 seconds
Started Jan 21 12:40:10 PM PST 24
Finished Jan 21 01:34:24 PM PST 24
Peak memory 608856 kb
Host smart-6f9aea2b-4d3a-49d1-8cdf-a8c335f99f96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2160429525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2160429525
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2569562567
Short name T258
Test name
Test status
Simulation time 20187006469 ps
CPU time 231.44 seconds
Started Jan 21 12:39:49 PM PST 24
Finished Jan 21 12:43:41 PM PST 24
Peak memory 202236 kb
Host smart-6113b0b0-45de-460e-b758-f257161143f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569562567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.2569562567
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2568356253
Short name T35
Test name
Test status
Simulation time 828235000 ps
CPU time 98.82 seconds
Started Jan 21 12:39:58 PM PST 24
Finished Jan 21 12:41:38 PM PST 24
Peak memory 345100 kb
Host smart-0444d323-ff4b-4d5e-907c-b3e3db14d6f6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568356253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.2568356253
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.564922824
Short name T271
Test name
Test status
Simulation time 25478096123 ps
CPU time 1136.7 seconds
Started Jan 21 12:40:25 PM PST 24
Finished Jan 21 12:59:22 PM PST 24
Peak memory 379108 kb
Host smart-3d44e155-9eb4-42f0-95f7-fb9da5336c81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564922824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 28.sram_ctrl_access_during_key_req.564922824
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.869753308
Short name T781
Test name
Test status
Simulation time 41549008 ps
CPU time 0.7 seconds
Started Jan 21 12:40:33 PM PST 24
Finished Jan 21 12:40:34 PM PST 24
Peak memory 201412 kb
Host smart-29edbe52-36bf-4f84-a423-55504c74eefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869753308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.869753308
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.1370456097
Short name T188
Test name
Test status
Simulation time 17410506606 ps
CPU time 1151.24 seconds
Started Jan 21 12:40:16 PM PST 24
Finished Jan 21 12:59:31 PM PST 24
Peak memory 202212 kb
Host smart-55abe26f-931c-419d-9620-0fd5b4c356b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370456097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.1370456097
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.2734391527
Short name T481
Test name
Test status
Simulation time 3707307204 ps
CPU time 11.46 seconds
Started Jan 21 12:40:24 PM PST 24
Finished Jan 21 12:40:36 PM PST 24
Peak memory 210292 kb
Host smart-67bc1de6-4059-483f-ab14-ff74e6f7144d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734391527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.2734391527
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.3875740765
Short name T778
Test name
Test status
Simulation time 977213188 ps
CPU time 27.35 seconds
Started Jan 21 12:40:22 PM PST 24
Finished Jan 21 12:40:50 PM PST 24
Peak memory 216220 kb
Host smart-0deeef93-d763-4792-ba12-1d25eeae90fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875740765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.3875740765
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.601365195
Short name T564
Test name
Test status
Simulation time 4877633646 ps
CPU time 75.17 seconds
Started Jan 21 12:40:32 PM PST 24
Finished Jan 21 12:41:48 PM PST 24
Peak memory 211180 kb
Host smart-6fa42c8b-5bee-406a-bfa7-910f1883c9ba
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601365195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_mem_partial_access.601365195
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.1011844278
Short name T650
Test name
Test status
Simulation time 19071027082 ps
CPU time 298.41 seconds
Started Jan 21 12:40:24 PM PST 24
Finished Jan 21 12:45:23 PM PST 24
Peak memory 202236 kb
Host smart-9e0350f0-2d57-4fc2-917f-bd5dc1597316
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011844278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.1011844278
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.738415112
Short name T255
Test name
Test status
Simulation time 60506841207 ps
CPU time 758.21 seconds
Started Jan 21 12:40:16 PM PST 24
Finished Jan 21 12:52:58 PM PST 24
Peak memory 375636 kb
Host smart-8da5ac38-d039-474f-be00-016d73bdce6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738415112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip
le_keys.738415112
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.4078317287
Short name T772
Test name
Test status
Simulation time 1034740539 ps
CPU time 17.74 seconds
Started Jan 21 12:40:18 PM PST 24
Finished Jan 21 12:40:38 PM PST 24
Peak memory 202084 kb
Host smart-14a91854-b418-477c-8b38-d376820097dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078317287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.4078317287
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1698178549
Short name T773
Test name
Test status
Simulation time 15112540961 ps
CPU time 253.54 seconds
Started Jan 21 12:40:22 PM PST 24
Finished Jan 21 12:44:37 PM PST 24
Peak memory 202156 kb
Host smart-3a3aa747-a995-42af-abbd-dc71b6913237
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698178549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1698178549
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.1498238244
Short name T684
Test name
Test status
Simulation time 1606196402 ps
CPU time 5.51 seconds
Started Jan 21 12:40:25 PM PST 24
Finished Jan 21 12:40:31 PM PST 24
Peak memory 202340 kb
Host smart-297e8418-ca12-4c37-9029-1bd69baf726b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498238244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1498238244
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.471905434
Short name T134
Test name
Test status
Simulation time 3755933703 ps
CPU time 1159.11 seconds
Started Jan 21 12:40:25 PM PST 24
Finished Jan 21 12:59:45 PM PST 24
Peak memory 380140 kb
Host smart-f1a42cf4-f160-47dd-8515-0e8b91e8ce77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471905434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.471905434
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.1532006381
Short name T370
Test name
Test status
Simulation time 4009824494 ps
CPU time 20.53 seconds
Started Jan 21 12:40:15 PM PST 24
Finished Jan 21 12:40:37 PM PST 24
Peak memory 202108 kb
Host smart-d263fe3b-75a2-45b2-a36f-9f05680b8a4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532006381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1532006381
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.1081177302
Short name T265
Test name
Test status
Simulation time 841627356431 ps
CPU time 3821.8 seconds
Started Jan 21 12:40:32 PM PST 24
Finished Jan 21 01:44:15 PM PST 24
Peak memory 380080 kb
Host smart-80cb2bef-78ee-4834-8c44-923685d591be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081177302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.1081177302
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2784590673
Short name T728
Test name
Test status
Simulation time 8028139693 ps
CPU time 2253.07 seconds
Started Jan 21 12:40:32 PM PST 24
Finished Jan 21 01:18:06 PM PST 24
Peak memory 521684 kb
Host smart-448cce3f-5fc9-4b96-a915-c54bd61d5971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2784590673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.2784590673
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.4096579358
Short name T219
Test name
Test status
Simulation time 2585413474 ps
CPU time 203.89 seconds
Started Jan 21 12:40:15 PM PST 24
Finished Jan 21 12:43:41 PM PST 24
Peak memory 210440 kb
Host smart-41c5e48e-949f-4eae-9c04-104b45dcb3a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096579358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.4096579358
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1709876707
Short name T701
Test name
Test status
Simulation time 1630646135 ps
CPU time 148.63 seconds
Started Jan 21 12:40:23 PM PST 24
Finished Jan 21 12:42:52 PM PST 24
Peak memory 364988 kb
Host smart-9a88575e-bffc-4783-9812-465d0c6a0c9d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709876707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1709876707
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1746016868
Short name T711
Test name
Test status
Simulation time 7448866753 ps
CPU time 969.85 seconds
Started Jan 21 12:40:46 PM PST 24
Finished Jan 21 12:56:58 PM PST 24
Peak memory 376920 kb
Host smart-c670db9c-21dd-4a06-9999-a79fb7e1192f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746016868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.1746016868
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.431643394
Short name T632
Test name
Test status
Simulation time 15676960 ps
CPU time 0.72 seconds
Started Jan 21 12:41:04 PM PST 24
Finished Jan 21 12:41:09 PM PST 24
Peak memory 201188 kb
Host smart-0b5f0df6-0722-4dc0-8105-b18263da9e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431643394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.431643394
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.7510029
Short name T446
Test name
Test status
Simulation time 187083084334 ps
CPU time 1468.81 seconds
Started Jan 21 12:40:42 PM PST 24
Finished Jan 21 01:05:15 PM PST 24
Peak memory 202140 kb
Host smart-d87c5d60-256f-4152-a677-f02b10d72d37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7510029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijecti
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.7510029
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.1790208921
Short name T442
Test name
Test status
Simulation time 9880583534 ps
CPU time 117.6 seconds
Started Jan 21 12:40:42 PM PST 24
Finished Jan 21 12:42:44 PM PST 24
Peak memory 210384 kb
Host smart-7bd48fe0-b45b-4d56-b974-b90ba767d56f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790208921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.1790208921
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.2874936449
Short name T927
Test name
Test status
Simulation time 693204299 ps
CPU time 28.66 seconds
Started Jan 21 12:40:40 PM PST 24
Finished Jan 21 12:41:10 PM PST 24
Peak memory 222908 kb
Host smart-c6a2379e-73b5-4977-b899-ada1248925df
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874936449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.2874936449
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1887745484
Short name T557
Test name
Test status
Simulation time 974102506 ps
CPU time 70.15 seconds
Started Jan 21 12:40:56 PM PST 24
Finished Jan 21 12:42:07 PM PST 24
Peak memory 211136 kb
Host smart-0b215620-1cdc-4bcc-9f9e-3f6fc71440d4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887745484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.1887745484
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.961624648
Short name T659
Test name
Test status
Simulation time 38082540123 ps
CPU time 302.81 seconds
Started Jan 21 12:40:55 PM PST 24
Finished Jan 21 12:45:58 PM PST 24
Peak memory 202544 kb
Host smart-2ccdbbaa-62d3-445d-8266-1ca62e94971d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961624648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl
_mem_walk.961624648
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.2456093843
Short name T947
Test name
Test status
Simulation time 88425421027 ps
CPU time 1598.21 seconds
Started Jan 21 12:40:41 PM PST 24
Finished Jan 21 01:07:24 PM PST 24
Peak memory 377016 kb
Host smart-0fde6b65-5c03-416c-aa32-592b9549ad11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456093843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.2456093843
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.4140399070
Short name T515
Test name
Test status
Simulation time 920793505 ps
CPU time 19.88 seconds
Started Jan 21 12:40:42 PM PST 24
Finished Jan 21 12:41:06 PM PST 24
Peak memory 234304 kb
Host smart-780a6cb2-c5f9-4cd3-965f-9335b6d4d950
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140399070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.4140399070
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.305478131
Short name T136
Test name
Test status
Simulation time 39835462284 ps
CPU time 239.35 seconds
Started Jan 21 12:40:40 PM PST 24
Finished Jan 21 12:44:41 PM PST 24
Peak memory 202104 kb
Host smart-1a0cb071-b27c-4a84-9720-05f2fc625991
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305478131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.sram_ctrl_partial_access_b2b.305478131
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.969882066
Short name T944
Test name
Test status
Simulation time 709263260 ps
CPU time 13.69 seconds
Started Jan 21 12:40:55 PM PST 24
Finished Jan 21 12:41:09 PM PST 24
Peak memory 202296 kb
Host smart-5331f27e-64bf-4e81-aa3f-642dc4083e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969882066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.969882066
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.3652156632
Short name T479
Test name
Test status
Simulation time 6920226607 ps
CPU time 327.77 seconds
Started Jan 21 12:40:54 PM PST 24
Finished Jan 21 12:46:22 PM PST 24
Peak memory 349376 kb
Host smart-ed256527-156a-4f9f-9962-cb8266d60f90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652156632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3652156632
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3449946793
Short name T482
Test name
Test status
Simulation time 1349697392 ps
CPU time 46.02 seconds
Started Jan 21 12:40:33 PM PST 24
Finished Jan 21 12:41:20 PM PST 24
Peak memory 288672 kb
Host smart-6d305ae5-d9b1-477c-bea8-f12f682a4605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449946793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3449946793
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.2566171309
Short name T892
Test name
Test status
Simulation time 1443334344221 ps
CPU time 4946.18 seconds
Started Jan 21 12:41:03 PM PST 24
Finished Jan 21 02:03:34 PM PST 24
Peak memory 361692 kb
Host smart-06e79d25-0f47-4cc1-8dec-e1a66dac474d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566171309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.2566171309
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.700529529
Short name T553
Test name
Test status
Simulation time 7211885853 ps
CPU time 252.61 seconds
Started Jan 21 12:40:38 PM PST 24
Finished Jan 21 12:44:51 PM PST 24
Peak memory 202080 kb
Host smart-377332b0-42bd-43ee-82e6-68f102452e25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700529529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_stress_pipeline.700529529
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.1808695553
Short name T252
Test name
Test status
Simulation time 3078967679 ps
CPU time 148.15 seconds
Started Jan 21 12:40:41 PM PST 24
Finished Jan 21 12:43:14 PM PST 24
Peak memory 348356 kb
Host smart-21f9ea8c-eb26-48fb-8e03-6a7c20b9de4b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808695553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.1808695553
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2992584517
Short name T672
Test name
Test status
Simulation time 24859496763 ps
CPU time 1344.87 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:54:49 PM PST 24
Peak memory 374720 kb
Host smart-126c7b5f-012d-4814-a718-aa86f45b1cf1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992584517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.2992584517
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.503909638
Short name T561
Test name
Test status
Simulation time 39040923 ps
CPU time 0.64 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:32:24 PM PST 24
Peak memory 202128 kb
Host smart-a20ecbb7-73f9-4b7d-8842-5dea4cc94bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503909638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.503909638
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.432195947
Short name T284
Test name
Test status
Simulation time 421962326799 ps
CPU time 2411.73 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 01:12:35 PM PST 24
Peak memory 201796 kb
Host smart-818e4121-d378-41cf-9fdf-02f96ed8764b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432195947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.432195947
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.2147295655
Short name T909
Test name
Test status
Simulation time 3326203918 ps
CPU time 71.95 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:33:35 PM PST 24
Peak memory 293740 kb
Host smart-d3510fb6-5a00-4fec-9fc3-27d5a4884d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147295655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.2147295655
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.355528221
Short name T54
Test name
Test status
Simulation time 49087707738 ps
CPU time 130.11 seconds
Started Jan 21 12:32:03 PM PST 24
Finished Jan 21 12:34:33 PM PST 24
Peak memory 210464 kb
Host smart-eaeec6e6-bcd0-414e-bd01-8d42208451f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355528221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca
lation.355528221
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3350897017
Short name T694
Test name
Test status
Simulation time 2991837671 ps
CPU time 56.01 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:33:19 PM PST 24
Peak memory 284064 kb
Host smart-398ba08a-85e3-414c-8f55-0641b71a7bd0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350897017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3350897017
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2724745467
Short name T464
Test name
Test status
Simulation time 1552889328 ps
CPU time 131.86 seconds
Started Jan 21 12:32:14 PM PST 24
Finished Jan 21 12:34:38 PM PST 24
Peak memory 211176 kb
Host smart-88af7530-e091-4215-aacc-342be15b8d69
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724745467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.2724745467
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.2711566779
Short name T378
Test name
Test status
Simulation time 228758906605 ps
CPU time 341.81 seconds
Started Jan 21 12:31:58 PM PST 24
Finished Jan 21 12:38:02 PM PST 24
Peak memory 202184 kb
Host smart-a07ec536-88a3-48a2-9de7-70d2ea52384c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711566779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.2711566779
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2005810370
Short name T196
Test name
Test status
Simulation time 9763239905 ps
CPU time 672.77 seconds
Started Jan 21 12:32:14 PM PST 24
Finished Jan 21 12:43:39 PM PST 24
Peak memory 376192 kb
Host smart-ec4bbd9d-3f01-4c4f-8f36-10b9e38c6ee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005810370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2005810370
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.4108311904
Short name T915
Test name
Test status
Simulation time 2644614247 ps
CPU time 65.45 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:33:29 PM PST 24
Peak memory 301048 kb
Host smart-094c7031-74b9-4c0a-b78f-b1a6689bfa05
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108311904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.4108311904
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2413448417
Short name T907
Test name
Test status
Simulation time 31900869009 ps
CPU time 284.1 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:37:08 PM PST 24
Peak memory 202076 kb
Host smart-dc23063d-50e4-4bf5-b773-3fbc7e5775d3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413448417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.2413448417
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.331142566
Short name T702
Test name
Test status
Simulation time 1402394137 ps
CPU time 6.86 seconds
Started Jan 21 12:32:05 PM PST 24
Finished Jan 21 12:32:30 PM PST 24
Peak memory 202340 kb
Host smart-e2a7b4b4-d0ab-42cc-b892-385cd59b46a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331142566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.331142566
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.126159490
Short name T568
Test name
Test status
Simulation time 40304129258 ps
CPU time 686.19 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:43:50 PM PST 24
Peak memory 366272 kb
Host smart-5933316a-7062-4980-bdcd-a59935d53abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126159490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.126159490
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.2771054803
Short name T20
Test name
Test status
Simulation time 873564820 ps
CPU time 2.82 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 12:32:26 PM PST 24
Peak memory 220672 kb
Host smart-479f21d5-74b3-463a-8c6c-737015c3750f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771054803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.2771054803
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.1124902035
Short name T949
Test name
Test status
Simulation time 3113897370 ps
CPU time 15.76 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:32:40 PM PST 24
Peak memory 249792 kb
Host smart-51e773bd-040f-4cda-b7f8-9ec877cf97d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124902035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1124902035
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.2851007681
Short name T392
Test name
Test status
Simulation time 107804230769 ps
CPU time 3381.73 seconds
Started Jan 21 12:32:04 PM PST 24
Finished Jan 21 01:28:45 PM PST 24
Peak memory 380128 kb
Host smart-b84fa7fb-0cca-4059-9782-0afa3d6c1137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851007681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.2851007681
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3805513481
Short name T888
Test name
Test status
Simulation time 896308237 ps
CPU time 5192.26 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 01:58:57 PM PST 24
Peak memory 433652 kb
Host smart-7b3fc897-ee4d-4ab5-89ab-0e1c9d80dce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3805513481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3805513481
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.293496782
Short name T499
Test name
Test status
Simulation time 15356291446 ps
CPU time 302.35 seconds
Started Jan 21 12:32:00 PM PST 24
Finished Jan 21 12:37:23 PM PST 24
Peak memory 202536 kb
Host smart-275b786d-1e1e-4f29-9852-4a06ecb2b0f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293496782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
sram_ctrl_stress_pipeline.293496782
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2482133145
Short name T290
Test name
Test status
Simulation time 3755856353 ps
CPU time 169.78 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:35:14 PM PST 24
Peak memory 371948 kb
Host smart-c251e7f3-e38f-4b06-8a68-1864957d2b6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482133145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.2482133145
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3255164407
Short name T468
Test name
Test status
Simulation time 1517920287 ps
CPU time 94.86 seconds
Started Jan 21 12:41:09 PM PST 24
Finished Jan 21 12:42:47 PM PST 24
Peak memory 288184 kb
Host smart-d957c3fc-27fc-40f5-b5c6-fc1c1329db31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255164407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.3255164407
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.4098879581
Short name T322
Test name
Test status
Simulation time 16199158 ps
CPU time 0.68 seconds
Started Jan 21 12:41:21 PM PST 24
Finished Jan 21 12:41:22 PM PST 24
Peak memory 201996 kb
Host smart-cdb6de82-2c9c-4947-a5d8-56ac9b650f49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098879581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.4098879581
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.4024704337
Short name T891
Test name
Test status
Simulation time 40816296040 ps
CPU time 1363.03 seconds
Started Jan 21 12:41:05 PM PST 24
Finished Jan 21 01:03:51 PM PST 24
Peak memory 202024 kb
Host smart-77da967c-bdfd-4884-a933-fa1709fe4030
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024704337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.4024704337
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.3392291383
Short name T763
Test name
Test status
Simulation time 26434345562 ps
CPU time 1142.52 seconds
Started Jan 21 03:05:05 PM PST 24
Finished Jan 21 03:24:09 PM PST 24
Peak memory 374024 kb
Host smart-1e9f0359-7e75-4e74-acea-24898e814461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392291383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.3392291383
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.4063188655
Short name T537
Test name
Test status
Simulation time 16243313796 ps
CPU time 100.78 seconds
Started Jan 21 12:55:15 PM PST 24
Finished Jan 21 12:56:56 PM PST 24
Peak memory 214512 kb
Host smart-7bfd3c47-e20d-41c2-8971-5ef832c24e3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063188655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.4063188655
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.3639192969
Short name T625
Test name
Test status
Simulation time 724455684 ps
CPU time 42.37 seconds
Started Jan 21 12:50:13 PM PST 24
Finished Jan 21 12:50:56 PM PST 24
Peak memory 262124 kb
Host smart-75947dc5-8125-42d8-88a6-f81e4682cc4f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639192969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.3639192969
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2106911348
Short name T591
Test name
Test status
Simulation time 4702697075 ps
CPU time 149.42 seconds
Started Jan 21 12:41:19 PM PST 24
Finished Jan 21 12:43:49 PM PST 24
Peak memory 211180 kb
Host smart-a652f1bf-1493-42a3-8a1d-cc83d5f268d3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106911348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.2106911348
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.2788758979
Short name T720
Test name
Test status
Simulation time 17644907031 ps
CPU time 275.49 seconds
Started Jan 21 12:41:21 PM PST 24
Finished Jan 21 12:45:57 PM PST 24
Peak memory 202164 kb
Host smart-98d7b66a-e6a1-4691-ba56-bb2f3a025f30
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788758979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.2788758979
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.3967228862
Short name T570
Test name
Test status
Simulation time 52692102224 ps
CPU time 1034.87 seconds
Started Jan 21 12:41:01 PM PST 24
Finished Jan 21 12:58:18 PM PST 24
Peak memory 379152 kb
Host smart-493772d2-22f7-408c-8a58-13bf14bb1336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967228862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.3967228862
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.3749920300
Short name T296
Test name
Test status
Simulation time 1021377313 ps
CPU time 144.7 seconds
Started Jan 21 12:41:03 PM PST 24
Finished Jan 21 12:43:32 PM PST 24
Peak memory 373756 kb
Host smart-704c2f5a-6064-4002-a827-0b4cdce6b8ab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749920300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.3749920300
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3250545157
Short name T350
Test name
Test status
Simulation time 9389899008 ps
CPU time 281.08 seconds
Started Jan 21 12:41:05 PM PST 24
Finished Jan 21 12:45:49 PM PST 24
Peak memory 202168 kb
Host smart-58a3b217-7e76-4585-abfb-51abc4b408e2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250545157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.3250545157
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.3052756261
Short name T357
Test name
Test status
Simulation time 377197608 ps
CPU time 13.29 seconds
Started Jan 21 12:41:18 PM PST 24
Finished Jan 21 12:41:32 PM PST 24
Peak memory 202336 kb
Host smart-65f418e9-0526-4e2e-bc5f-a60b567566f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052756261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3052756261
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.1397792960
Short name T573
Test name
Test status
Simulation time 72316038111 ps
CPU time 1191.75 seconds
Started Jan 21 12:41:19 PM PST 24
Finished Jan 21 01:01:11 PM PST 24
Peak memory 378048 kb
Host smart-f27aa133-e6c4-4eda-ae3a-6195dc0919ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397792960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1397792960
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.878634059
Short name T533
Test name
Test status
Simulation time 1684066309 ps
CPU time 41.55 seconds
Started Jan 21 12:41:04 PM PST 24
Finished Jan 21 12:41:50 PM PST 24
Peak memory 275884 kb
Host smart-c3a18a8f-96cf-47f1-a6f8-56c93d0f2d5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878634059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.878634059
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.3895830375
Short name T272
Test name
Test status
Simulation time 233310444574 ps
CPU time 4149.54 seconds
Started Jan 21 12:41:19 PM PST 24
Finished Jan 21 01:50:30 PM PST 24
Peak memory 381532 kb
Host smart-123d7768-6384-4caf-a187-7331ab111564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895830375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.3895830375
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4205944732
Short name T384
Test name
Test status
Simulation time 5927001645 ps
CPU time 6544.8 seconds
Started Jan 21 12:41:21 PM PST 24
Finished Jan 21 02:30:27 PM PST 24
Peak memory 611492 kb
Host smart-f63e7b41-47de-46f8-99c4-93cda9c0e7ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4205944732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.4205944732
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3430377888
Short name T613
Test name
Test status
Simulation time 4584812665 ps
CPU time 331.29 seconds
Started Jan 21 12:41:03 PM PST 24
Finished Jan 21 12:46:39 PM PST 24
Peak memory 202148 kb
Host smart-cb21c5b8-d26e-4636-a06f-db944eb72685
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430377888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.3430377888
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1026453565
Short name T197
Test name
Test status
Simulation time 2791909094 ps
CPU time 24.41 seconds
Started Jan 21 01:13:11 PM PST 24
Finished Jan 21 01:13:38 PM PST 24
Peak memory 209768 kb
Host smart-5554b200-36dd-42bf-ab9e-420ae8ade088
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026453565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1026453565
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2709257385
Short name T886
Test name
Test status
Simulation time 20756669888 ps
CPU time 712.2 seconds
Started Jan 21 12:41:27 PM PST 24
Finished Jan 21 12:53:20 PM PST 24
Peak memory 376968 kb
Host smart-fdcdd1f6-2a1f-4e2c-8a9e-c070f5350e5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709257385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.2709257385
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.1362293613
Short name T460
Test name
Test status
Simulation time 15138609 ps
CPU time 0.65 seconds
Started Jan 21 12:41:50 PM PST 24
Finished Jan 21 12:41:51 PM PST 24
Peak memory 202012 kb
Host smart-22daa148-1520-413a-a53b-bb992fcda508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362293613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.1362293613
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2923073480
Short name T649
Test name
Test status
Simulation time 239993120958 ps
CPU time 1398.45 seconds
Started Jan 21 12:41:27 PM PST 24
Finished Jan 21 01:04:46 PM PST 24
Peak memory 202128 kb
Host smart-4af7c39a-6fca-4f45-bdfe-4320979b700a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923073480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2923073480
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.3551950259
Short name T381
Test name
Test status
Simulation time 30616145065 ps
CPU time 1150.31 seconds
Started Jan 21 12:55:15 PM PST 24
Finished Jan 21 01:14:26 PM PST 24
Peak memory 377968 kb
Host smart-aa00b15a-6cd5-4b48-8b4b-1819924523c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551950259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.3551950259
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2936959303
Short name T532
Test name
Test status
Simulation time 22665549516 ps
CPU time 121.3 seconds
Started Jan 21 12:41:28 PM PST 24
Finished Jan 21 12:43:30 PM PST 24
Peak memory 202108 kb
Host smart-357f9ae5-180d-4a8d-93a5-023f98c70654
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936959303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2936959303
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.3768433116
Short name T843
Test name
Test status
Simulation time 883709233 ps
CPU time 112.29 seconds
Started Jan 21 12:41:27 PM PST 24
Finished Jan 21 12:43:20 PM PST 24
Peak memory 320700 kb
Host smart-f733e43b-cd32-4fb7-9fd1-0826a9d85b34
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768433116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.3768433116
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1830358138
Short name T765
Test name
Test status
Simulation time 13873859629 ps
CPU time 148.11 seconds
Started Jan 21 01:45:50 PM PST 24
Finished Jan 21 01:48:18 PM PST 24
Peak memory 214552 kb
Host smart-9ef43416-acd7-47c7-b6c7-a774ff9b2f56
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830358138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.1830358138
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.1984953504
Short name T315
Test name
Test status
Simulation time 21496873391 ps
CPU time 300.07 seconds
Started Jan 21 12:41:44 PM PST 24
Finished Jan 21 12:46:45 PM PST 24
Peak memory 202564 kb
Host smart-62729f6c-89b4-44a4-a002-077f41152cf4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984953504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.1984953504
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.1871902137
Short name T686
Test name
Test status
Simulation time 3001507565 ps
CPU time 254.75 seconds
Started Jan 21 12:41:21 PM PST 24
Finished Jan 21 12:45:37 PM PST 24
Peak memory 371108 kb
Host smart-f6e21442-1f45-42d1-942d-c0d68e9f4f4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871902137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.1871902137
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.2369782626
Short name T614
Test name
Test status
Simulation time 7963654626 ps
CPU time 13.13 seconds
Started Jan 21 12:41:27 PM PST 24
Finished Jan 21 12:41:41 PM PST 24
Peak memory 208172 kb
Host smart-faeb4eea-a4c8-404d-8818-f04fc651d4c7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369782626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.2369782626
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.419182886
Short name T922
Test name
Test status
Simulation time 175282349641 ps
CPU time 335.06 seconds
Started Jan 21 12:41:35 PM PST 24
Finished Jan 21 12:47:11 PM PST 24
Peak memory 202020 kb
Host smart-eb9dd979-38c3-46fc-bd82-9f4597510efb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419182886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.sram_ctrl_partial_access_b2b.419182886
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.564616764
Short name T683
Test name
Test status
Simulation time 1597809728 ps
CPU time 13.94 seconds
Started Jan 21 12:41:43 PM PST 24
Finished Jan 21 12:41:58 PM PST 24
Peak memory 202272 kb
Host smart-4891e6b0-e12f-4c0b-9648-f42cb5510c52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564616764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.564616764
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.3058559941
Short name T932
Test name
Test status
Simulation time 4473457055 ps
CPU time 1165.38 seconds
Started Jan 21 12:41:43 PM PST 24
Finished Jan 21 01:01:09 PM PST 24
Peak memory 378140 kb
Host smart-9ef29eba-b25d-425b-8748-fc04c20bb29a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058559941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3058559941
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3853001231
Short name T221
Test name
Test status
Simulation time 3420524745 ps
CPU time 26.51 seconds
Started Jan 21 12:41:19 PM PST 24
Finished Jan 21 12:41:46 PM PST 24
Peak memory 258972 kb
Host smart-70e4bce5-f218-428c-a8e9-0becdb3588be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853001231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3853001231
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.1973013184
Short name T371
Test name
Test status
Simulation time 252709683194 ps
CPU time 2520.2 seconds
Started Jan 21 12:41:51 PM PST 24
Finished Jan 21 01:23:52 PM PST 24
Peak memory 380964 kb
Host smart-d5512399-f853-4f62-a518-c48eb97fe227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973013184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.1973013184
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2236674866
Short name T631
Test name
Test status
Simulation time 3991970444 ps
CPU time 3787.59 seconds
Started Jan 21 01:09:03 PM PST 24
Finished Jan 21 02:12:12 PM PST 24
Peak memory 696516 kb
Host smart-9ed3b7a3-ab27-43c1-a8df-0ceb4034310d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2236674866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2236674866
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2342867649
Short name T724
Test name
Test status
Simulation time 10290470406 ps
CPU time 183.45 seconds
Started Jan 21 12:41:35 PM PST 24
Finished Jan 21 12:44:40 PM PST 24
Peak memory 210320 kb
Host smart-76811a8d-955d-49a7-a568-5713fddc34ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342867649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2342867649
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1711806499
Short name T210
Test name
Test status
Simulation time 730350079 ps
CPU time 35.42 seconds
Started Jan 21 12:41:26 PM PST 24
Finished Jan 21 12:42:02 PM PST 24
Peak memory 251120 kb
Host smart-c242dfc5-e0f1-4fcc-a5f5-59747b683389
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711806499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.1711806499
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.1714188033
Short name T687
Test name
Test status
Simulation time 5710836543 ps
CPU time 221.22 seconds
Started Jan 21 12:42:02 PM PST 24
Finished Jan 21 12:45:44 PM PST 24
Peak memory 287168 kb
Host smart-e7f71076-7f32-41d4-b3da-20c9a436d1e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714188033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.1714188033
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.2887797609
Short name T104
Test name
Test status
Simulation time 12184691 ps
CPU time 0.62 seconds
Started Jan 21 01:49:59 PM PST 24
Finished Jan 21 01:50:00 PM PST 24
Peak memory 202096 kb
Host smart-1abd3373-f3e2-4216-bf12-81c3578ffb23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887797609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.2887797609
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.1585019551
Short name T747
Test name
Test status
Simulation time 159361034506 ps
CPU time 1893.77 seconds
Started Jan 21 12:41:56 PM PST 24
Finished Jan 21 01:13:30 PM PST 24
Peak memory 202132 kb
Host smart-150c6f1d-3cc1-43f5-97f4-d036a1f940bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585019551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.1585019551
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.708248767
Short name T360
Test name
Test status
Simulation time 10158749346 ps
CPU time 526.68 seconds
Started Jan 21 12:42:04 PM PST 24
Finished Jan 21 12:50:51 PM PST 24
Peak memory 358796 kb
Host smart-15b119c4-543b-4a7c-92a2-317ef978e9db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708248767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executabl
e.708248767
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.359931954
Short name T488
Test name
Test status
Simulation time 61302362360 ps
CPU time 167.73 seconds
Started Jan 21 12:42:05 PM PST 24
Finished Jan 21 12:44:53 PM PST 24
Peak memory 202160 kb
Host smart-f5cdbdc5-5c8b-4eea-bbd8-93b39be1d900
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359931954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_esc
alation.359931954
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.4246908711
Short name T740
Test name
Test status
Simulation time 727307884 ps
CPU time 31.75 seconds
Started Jan 21 01:12:36 PM PST 24
Finished Jan 21 01:13:08 PM PST 24
Peak memory 234932 kb
Host smart-ae2ae7e2-a3fb-4a59-8d91-9d293cb8ab7e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246908711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.4246908711
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.578520661
Short name T814
Test name
Test status
Simulation time 4421767676 ps
CPU time 144.99 seconds
Started Jan 21 01:01:46 PM PST 24
Finished Jan 21 01:04:11 PM PST 24
Peak memory 214652 kb
Host smart-f33e1847-d6dd-41e4-879c-868125a61876
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578520661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_mem_partial_access.578520661
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.4082444658
Short name T548
Test name
Test status
Simulation time 14205897552 ps
CPU time 275.64 seconds
Started Jan 21 12:42:12 PM PST 24
Finished Jan 21 12:46:49 PM PST 24
Peak memory 202232 kb
Host smart-715c5c8c-e0c9-486e-b3bd-e898e84463f7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082444658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.4082444658
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.256501713
Short name T897
Test name
Test status
Simulation time 14960726211 ps
CPU time 2206.34 seconds
Started Jan 21 12:41:58 PM PST 24
Finished Jan 21 01:18:45 PM PST 24
Peak memory 379020 kb
Host smart-47ddcad9-7b89-482a-9d1e-5bce8ad31b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256501713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip
le_keys.256501713
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.255532324
Short name T961
Test name
Test status
Simulation time 8944760075 ps
CPU time 19.61 seconds
Started Jan 21 12:42:00 PM PST 24
Finished Jan 21 12:42:21 PM PST 24
Peak memory 251336 kb
Host smart-b5f4d11f-776f-458f-8f20-14a60c0aac1d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255532324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s
ram_ctrl_partial_access.255532324
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.551002630
Short name T439
Test name
Test status
Simulation time 22187355064 ps
CPU time 332.34 seconds
Started Jan 21 12:41:55 PM PST 24
Finished Jan 21 12:47:29 PM PST 24
Peak memory 202156 kb
Host smart-9ba9a149-63dc-46c0-8946-46d20ad11e04
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551002630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.sram_ctrl_partial_access_b2b.551002630
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.2120358371
Short name T414
Test name
Test status
Simulation time 842505107 ps
CPU time 5.3 seconds
Started Jan 21 01:37:06 PM PST 24
Finished Jan 21 01:37:12 PM PST 24
Peak memory 202396 kb
Host smart-6dfba1cd-58d6-4c7f-9e7a-ca9bc7ab8389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120358371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2120358371
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.2293692784
Short name T616
Test name
Test status
Simulation time 946641571 ps
CPU time 127.05 seconds
Started Jan 21 12:42:12 PM PST 24
Finished Jan 21 12:44:19 PM PST 24
Peak memory 338032 kb
Host smart-16d67966-455b-4b33-a63d-7596270da910
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293692784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2293692784
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.2089319591
Short name T698
Test name
Test status
Simulation time 1362575525 ps
CPU time 14.05 seconds
Started Jan 21 12:41:55 PM PST 24
Finished Jan 21 12:42:10 PM PST 24
Peak memory 202044 kb
Host smart-fca1cbcd-9bd5-4e73-8aea-9e9b2baba418
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089319591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2089319591
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3356889565
Short name T28
Test name
Test status
Simulation time 7533196231 ps
CPU time 7233.45 seconds
Started Jan 21 01:21:28 PM PST 24
Finished Jan 21 03:22:02 PM PST 24
Peak memory 468140 kb
Host smart-f8c99f77-59ba-4297-ad43-ca26e584efec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3356889565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3356889565
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.106351022
Short name T764
Test name
Test status
Simulation time 7313825991 ps
CPU time 472.39 seconds
Started Jan 21 12:41:58 PM PST 24
Finished Jan 21 12:49:51 PM PST 24
Peak memory 202164 kb
Host smart-bfd24bb2-c927-44a9-8134-3cd84b36ba23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106351022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_stress_pipeline.106351022
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2403384677
Short name T734
Test name
Test status
Simulation time 1745772473 ps
CPU time 29.9 seconds
Started Jan 21 12:42:01 PM PST 24
Finished Jan 21 12:42:32 PM PST 24
Peak memory 224156 kb
Host smart-6f4b7e9f-4c01-493c-b630-d50ae44f1f6f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403384677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2403384677
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2312248447
Short name T743
Test name
Test status
Simulation time 7351853270 ps
CPU time 662.87 seconds
Started Jan 21 12:42:35 PM PST 24
Finished Jan 21 12:53:39 PM PST 24
Peak memory 367868 kb
Host smart-b5363449-8f70-4b6d-a724-b9c0846847a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312248447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.2312248447
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.1666853296
Short name T622
Test name
Test status
Simulation time 45698885 ps
CPU time 0.68 seconds
Started Jan 21 12:42:42 PM PST 24
Finished Jan 21 12:42:44 PM PST 24
Peak memory 202020 kb
Host smart-d6b2963a-029b-4525-b4fc-b8046c564feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666853296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.1666853296
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.386872575
Short name T657
Test name
Test status
Simulation time 61493788330 ps
CPU time 1001.63 seconds
Started Jan 21 12:42:28 PM PST 24
Finished Jan 21 12:59:10 PM PST 24
Peak memory 202156 kb
Host smart-6f0af89e-3fda-4c80-907d-22ccece40aa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386872575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.
386872575
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.2660679277
Short name T682
Test name
Test status
Simulation time 85003814548 ps
CPU time 899.77 seconds
Started Jan 21 12:42:37 PM PST 24
Finished Jan 21 12:57:37 PM PST 24
Peak memory 375004 kb
Host smart-17894280-d7f4-43c1-a044-39c74a8d85ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660679277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.2660679277
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.1733794963
Short name T645
Test name
Test status
Simulation time 3592802201 ps
CPU time 93.53 seconds
Started Jan 21 12:42:32 PM PST 24
Finished Jan 21 12:44:06 PM PST 24
Peak memory 202160 kb
Host smart-10b2e536-9008-45cf-8b88-9b8bcdd87980
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733794963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.1733794963
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.1872261045
Short name T317
Test name
Test status
Simulation time 14138634330 ps
CPU time 54.21 seconds
Started Jan 21 01:19:05 PM PST 24
Finished Jan 21 01:20:00 PM PST 24
Peak memory 271868 kb
Host smart-3e63fbfb-50aa-4a82-9947-65252dfa1bdc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872261045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.1872261045
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1599299458
Short name T282
Test name
Test status
Simulation time 1904361918 ps
CPU time 72.5 seconds
Started Jan 21 12:42:36 PM PST 24
Finished Jan 21 12:43:49 PM PST 24
Peak memory 211200 kb
Host smart-2a12fb55-9ff9-4211-a870-3d0cd7bf9c6d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599299458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1599299458
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.3256201531
Short name T245
Test name
Test status
Simulation time 4023439519 ps
CPU time 245.3 seconds
Started Jan 21 12:42:40 PM PST 24
Finished Jan 21 12:46:46 PM PST 24
Peak memory 202172 kb
Host smart-49c45522-b670-4607-9a2d-0d6f609be08e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256201531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.3256201531
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.2719446322
Short name T775
Test name
Test status
Simulation time 58066726730 ps
CPU time 1260.7 seconds
Started Jan 21 01:10:47 PM PST 24
Finished Jan 21 01:31:49 PM PST 24
Peak memory 377028 kb
Host smart-fd274dee-3554-437a-9516-432e1acc8c20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719446322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.2719446322
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.2055693522
Short name T807
Test name
Test status
Simulation time 3773172311 ps
CPU time 34.25 seconds
Started Jan 21 01:04:06 PM PST 24
Finished Jan 21 01:04:42 PM PST 24
Peak memory 268716 kb
Host smart-d384f2a6-a7ac-4a3b-9f59-675ed73c89ae
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055693522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.2055693522
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.3694878215
Short name T620
Test name
Test status
Simulation time 4839038463 ps
CPU time 287.83 seconds
Started Jan 21 01:03:27 PM PST 24
Finished Jan 21 01:08:16 PM PST 24
Peak memory 202284 kb
Host smart-57cbfe45-a2ab-441b-b6e0-d133d154e9ce
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694878215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.3694878215
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.3796483118
Short name T504
Test name
Test status
Simulation time 401785579 ps
CPU time 13.71 seconds
Started Jan 21 12:42:35 PM PST 24
Finished Jan 21 12:42:50 PM PST 24
Peak memory 202284 kb
Host smart-68f5282e-1f15-4d8f-ba52-6190fe66c1eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796483118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3796483118
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.3267581221
Short name T516
Test name
Test status
Simulation time 29621793234 ps
CPU time 779.54 seconds
Started Jan 21 12:42:37 PM PST 24
Finished Jan 21 12:55:37 PM PST 24
Peak memory 374780 kb
Host smart-5b892c63-645b-4843-98e1-75d03ed12cb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267581221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3267581221
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.1471130227
Short name T768
Test name
Test status
Simulation time 1739742064 ps
CPU time 13.83 seconds
Started Jan 21 01:39:32 PM PST 24
Finished Jan 21 01:39:49 PM PST 24
Peak memory 202160 kb
Host smart-02d8ea73-d642-49f4-a3dc-ffaa2edae6f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471130227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1471130227
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.3266523242
Short name T757
Test name
Test status
Simulation time 268204556039 ps
CPU time 7110.42 seconds
Started Jan 21 01:33:18 PM PST 24
Finished Jan 21 03:31:51 PM PST 24
Peak memory 380056 kb
Host smart-2d1a3b9d-91ca-4e43-aae8-34a15d3bdb39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266523242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.3266523242
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1997043732
Short name T691
Test name
Test status
Simulation time 1708386312 ps
CPU time 4892.88 seconds
Started Jan 21 12:42:41 PM PST 24
Finished Jan 21 02:04:16 PM PST 24
Peak memory 469200 kb
Host smart-704fe19d-d0f9-405a-ab70-50e2788b6fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1997043732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.1997043732
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3305055946
Short name T862
Test name
Test status
Simulation time 4343310859 ps
CPU time 324.41 seconds
Started Jan 21 01:25:59 PM PST 24
Finished Jan 21 01:31:25 PM PST 24
Peak memory 202268 kb
Host smart-5b4a0007-4db2-4f99-93f9-6510c167b71f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305055946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.3305055946
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.973167480
Short name T558
Test name
Test status
Simulation time 2986430218 ps
CPU time 44.64 seconds
Started Jan 21 01:10:41 PM PST 24
Finished Jan 21 01:11:28 PM PST 24
Peak memory 270952 kb
Host smart-c4a782a7-0187-46a2-aa67-948834db247d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973167480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.973167480
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2609559889
Short name T911
Test name
Test status
Simulation time 10843003608 ps
CPU time 1513.54 seconds
Started Jan 21 12:42:57 PM PST 24
Finished Jan 21 01:08:12 PM PST 24
Peak memory 377100 kb
Host smart-9e1da354-6338-40b1-b5a8-1486d59953d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609559889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2609559889
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.1925052531
Short name T270
Test name
Test status
Simulation time 11532398 ps
CPU time 0.62 seconds
Started Jan 21 12:43:05 PM PST 24
Finished Jan 21 12:43:07 PM PST 24
Peak memory 201864 kb
Host smart-2124434f-3838-4ffa-a0e3-af0e9b571eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925052531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.1925052531
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.2849053224
Short name T382
Test name
Test status
Simulation time 170883395207 ps
CPU time 753.21 seconds
Started Jan 21 12:42:43 PM PST 24
Finished Jan 21 12:55:21 PM PST 24
Peak memory 202140 kb
Host smart-d49d8cd6-d750-4db7-8de7-825f4b2b0a14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849053224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.2849053224
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.3866502692
Short name T376
Test name
Test status
Simulation time 15164676303 ps
CPU time 190.84 seconds
Started Jan 21 12:42:57 PM PST 24
Finished Jan 21 12:46:09 PM PST 24
Peak memory 210308 kb
Host smart-fbdbd5e4-7e69-4e1b-9ae0-cbe333a38ee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866502692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.3866502692
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.169035782
Short name T51
Test name
Test status
Simulation time 3197344869 ps
CPU time 149.99 seconds
Started Jan 21 12:42:49 PM PST 24
Finished Jan 21 12:45:21 PM PST 24
Peak memory 371800 kb
Host smart-aad9806c-e238-41a8-9fd6-cca2249d4883
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169035782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.sram_ctrl_max_throughput.169035782
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1249661724
Short name T903
Test name
Test status
Simulation time 19096195983 ps
CPU time 70.28 seconds
Started Jan 21 12:42:59 PM PST 24
Finished Jan 21 12:44:11 PM PST 24
Peak memory 211444 kb
Host smart-3c29d3e5-5af1-4df0-9380-a4532d4af9d7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249661724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.1249661724
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2790195449
Short name T708
Test name
Test status
Simulation time 3987376918 ps
CPU time 236.8 seconds
Started Jan 21 12:43:00 PM PST 24
Finished Jan 21 12:46:58 PM PST 24
Peak memory 202272 kb
Host smart-db5c7846-11fc-43d7-9f51-077e9dc0ec31
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790195449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2790195449
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.3520242588
Short name T699
Test name
Test status
Simulation time 5480048725 ps
CPU time 407.26 seconds
Started Jan 21 12:42:43 PM PST 24
Finished Jan 21 12:49:31 PM PST 24
Peak memory 371968 kb
Host smart-a2cb14c3-d4fc-4835-a2a9-0ad1371a2dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520242588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.3520242588
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.1779158445
Short name T193
Test name
Test status
Simulation time 3821758916 ps
CPU time 43.01 seconds
Started Jan 21 03:01:27 PM PST 24
Finished Jan 21 03:02:12 PM PST 24
Peak memory 202288 kb
Host smart-fc811153-a4b5-4503-8738-08cbfa0e4cf3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779158445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.1779158445
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.651482714
Short name T399
Test name
Test status
Simulation time 358690127 ps
CPU time 5.1 seconds
Started Jan 21 01:26:27 PM PST 24
Finished Jan 21 01:26:33 PM PST 24
Peak memory 202316 kb
Host smart-fd107cd1-c67b-4264-84be-2e8524ace886
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651482714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.651482714
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.2355817821
Short name T18
Test name
Test status
Simulation time 3034917040 ps
CPU time 829.61 seconds
Started Jan 21 12:43:00 PM PST 24
Finished Jan 21 12:56:51 PM PST 24
Peak memory 378084 kb
Host smart-56d5dcf6-5aab-4e5b-b224-1f1af4cac887
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355817821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2355817821
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.1309335511
Short name T767
Test name
Test status
Simulation time 13966095721 ps
CPU time 29.4 seconds
Started Jan 21 12:42:41 PM PST 24
Finished Jan 21 12:43:12 PM PST 24
Peak memory 202224 kb
Host smart-1f5ab727-3b4b-4bc9-8563-c034d2c820ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309335511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1309335511
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.208117525
Short name T617
Test name
Test status
Simulation time 1668345477 ps
CPU time 2774.28 seconds
Started Jan 21 01:07:02 PM PST 24
Finished Jan 21 01:53:20 PM PST 24
Peak memory 555860 kb
Host smart-3a72558a-afc5-4eb8-843a-f2a96ddca3da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=208117525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.208117525
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1151249539
Short name T865
Test name
Test status
Simulation time 10469001752 ps
CPU time 399.84 seconds
Started Jan 21 12:42:55 PM PST 24
Finished Jan 21 12:49:35 PM PST 24
Peak memory 202068 kb
Host smart-43820bcd-9870-442e-89f6-44af4f5b87c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151249539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.1151249539
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.22044998
Short name T933
Test name
Test status
Simulation time 797780460 ps
CPU time 130.09 seconds
Started Jan 21 12:42:51 PM PST 24
Finished Jan 21 12:45:03 PM PST 24
Peak memory 371940 kb
Host smart-68116cd1-4c17-45f8-96ee-65dd1857aac2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.sram_ctrl_throughput_w_partial_write.22044998
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.3810836341
Short name T448
Test name
Test status
Simulation time 9518862091 ps
CPU time 798.32 seconds
Started Jan 21 12:43:32 PM PST 24
Finished Jan 21 12:56:56 PM PST 24
Peak memory 369788 kb
Host smart-344373d1-3ef5-424a-a642-a8c9bedc4021
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810836341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.3810836341
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2693468649
Short name T905
Test name
Test status
Simulation time 34404233 ps
CPU time 0.62 seconds
Started Jan 21 12:43:47 PM PST 24
Finished Jan 21 12:43:48 PM PST 24
Peak memory 201448 kb
Host smart-bb602474-51b6-4699-95f0-a432627d30ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693468649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2693468649
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.3306839760
Short name T438
Test name
Test status
Simulation time 108060948347 ps
CPU time 2434.52 seconds
Started Jan 21 12:43:16 PM PST 24
Finished Jan 21 01:23:52 PM PST 24
Peak memory 202124 kb
Host smart-d9acf52b-356b-471a-8a2b-05382ad42542
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306839760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.3306839760
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.841766536
Short name T704
Test name
Test status
Simulation time 36618470545 ps
CPU time 505.96 seconds
Started Jan 21 12:43:33 PM PST 24
Finished Jan 21 12:52:03 PM PST 24
Peak memory 376968 kb
Host smart-0147d7de-475a-4bf2-a5aa-300718f6afa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841766536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executabl
e.841766536
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3948513447
Short name T194
Test name
Test status
Simulation time 62261898170 ps
CPU time 147.97 seconds
Started Jan 21 12:43:34 PM PST 24
Finished Jan 21 12:46:05 PM PST 24
Peak memory 210256 kb
Host smart-f72d4a65-8cdf-4cff-abb9-1b9121897a4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948513447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3948513447
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.901936518
Short name T877
Test name
Test status
Simulation time 758320169 ps
CPU time 142.93 seconds
Started Jan 21 12:43:34 PM PST 24
Finished Jan 21 12:46:00 PM PST 24
Peak memory 354448 kb
Host smart-87d2e965-bae0-4737-bbde-651aafbdb758
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901936518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.sram_ctrl_max_throughput.901936518
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.3309745071
Short name T527
Test name
Test status
Simulation time 10149704555 ps
CPU time 148.02 seconds
Started Jan 21 12:43:41 PM PST 24
Finished Jan 21 12:46:10 PM PST 24
Peak memory 214476 kb
Host smart-3a89b9e9-884b-495e-80bb-97e26fa78d71
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309745071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.3309745071
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.3718009776
Short name T250
Test name
Test status
Simulation time 49188672414 ps
CPU time 152.05 seconds
Started Jan 21 12:43:40 PM PST 24
Finished Jan 21 12:46:14 PM PST 24
Peak memory 202240 kb
Host smart-dfc8f6f9-1b66-4858-911c-04f355afde1d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718009776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.3718009776
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.742877279
Short name T455
Test name
Test status
Simulation time 2968961253 ps
CPU time 25.1 seconds
Started Jan 21 12:43:26 PM PST 24
Finished Jan 21 12:43:52 PM PST 24
Peak memory 202040 kb
Host smart-181d10bc-7729-4da7-a415-6fbe0995ce30
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742877279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s
ram_ctrl_partial_access.742877279
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3005494473
Short name T450
Test name
Test status
Simulation time 6548676263 ps
CPU time 386.28 seconds
Started Jan 21 12:43:26 PM PST 24
Finished Jan 21 12:49:53 PM PST 24
Peak memory 202148 kb
Host smart-1a453ece-0a95-4b64-b1b0-89cc6ef85f65
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005494473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3005494473
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.188132754
Short name T498
Test name
Test status
Simulation time 348094317 ps
CPU time 13.55 seconds
Started Jan 21 12:43:40 PM PST 24
Finished Jan 21 12:43:55 PM PST 24
Peak memory 202368 kb
Host smart-8e72edf9-8b83-48b9-abbf-4a5888b42f6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188132754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.188132754
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.918785899
Short name T552
Test name
Test status
Simulation time 11340012849 ps
CPU time 1155.56 seconds
Started Jan 21 12:43:41 PM PST 24
Finished Jan 21 01:02:58 PM PST 24
Peak memory 373888 kb
Host smart-f01afc13-8114-474d-b581-975c0ef3df96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918785899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.918785899
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3686563337
Short name T140
Test name
Test status
Simulation time 1350984086 ps
CPU time 21.95 seconds
Started Jan 21 12:43:07 PM PST 24
Finished Jan 21 12:43:31 PM PST 24
Peak memory 202076 kb
Host smart-df291b58-f1a6-4c0c-91c3-346cc6a43e9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686563337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3686563337
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.3882566780
Short name T835
Test name
Test status
Simulation time 60329228053 ps
CPU time 3158.38 seconds
Started Jan 21 12:43:47 PM PST 24
Finished Jan 21 01:36:27 PM PST 24
Peak memory 382116 kb
Host smart-492906c5-af2c-4931-b6b9-11f565ca72ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882566780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.3882566780
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2140553528
Short name T243
Test name
Test status
Simulation time 1442065606 ps
CPU time 3417.94 seconds
Started Jan 21 12:43:40 PM PST 24
Finished Jan 21 01:40:40 PM PST 24
Peak memory 630528 kb
Host smart-dc5bd223-18d8-4663-94ba-a3ecad912c8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2140553528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.2140553528
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.287025613
Short name T719
Test name
Test status
Simulation time 41806795936 ps
CPU time 268.61 seconds
Started Jan 21 12:43:18 PM PST 24
Finished Jan 21 12:47:48 PM PST 24
Peak memory 202132 kb
Host smart-80ceee6e-0ffa-406e-8240-5043dd65c032
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287025613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_stress_pipeline.287025613
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.551703075
Short name T220
Test name
Test status
Simulation time 801690140 ps
CPU time 153.87 seconds
Started Jan 21 12:43:33 PM PST 24
Finished Jan 21 12:46:11 PM PST 24
Peak memory 365748 kb
Host smart-e4ccd50a-29a6-4568-8dcf-49cff0b7bc51
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551703075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_throughput_w_partial_write.551703075
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2644916955
Short name T78
Test name
Test status
Simulation time 50228285272 ps
CPU time 1771.56 seconds
Started Jan 21 12:44:11 PM PST 24
Finished Jan 21 01:13:43 PM PST 24
Peak memory 379064 kb
Host smart-a1a0a833-8321-4af0-bdd3-8213fb011fd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644916955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.2644916955
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.257281205
Short name T761
Test name
Test status
Simulation time 21564767 ps
CPU time 0.63 seconds
Started Jan 21 12:44:37 PM PST 24
Finished Jan 21 12:44:39 PM PST 24
Peak memory 202104 kb
Host smart-0ffa3f2d-56a8-4e0d-a800-1fcc770e3853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257281205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.257281205
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.3404754759
Short name T253
Test name
Test status
Simulation time 49533506462 ps
CPU time 854.86 seconds
Started Jan 21 12:43:49 PM PST 24
Finished Jan 21 12:58:05 PM PST 24
Peak memory 202108 kb
Host smart-d8e35f23-20c9-4704-b9ed-6ae4ab2837d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404754759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.3404754759
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.2830936241
Short name T191
Test name
Test status
Simulation time 18220164398 ps
CPU time 1546.88 seconds
Started Jan 21 12:44:06 PM PST 24
Finished Jan 21 01:09:53 PM PST 24
Peak memory 368904 kb
Host smart-7fdf8bb4-671e-4f41-91f3-b421189663ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830936241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.2830936241
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.2912981328
Short name T332
Test name
Test status
Simulation time 9589183329 ps
CPU time 185.81 seconds
Started Jan 21 12:43:58 PM PST 24
Finished Jan 21 12:47:04 PM PST 24
Peak memory 210488 kb
Host smart-cb854e9d-d7c3-40f9-a6d8-bc9516f33a9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912981328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.2912981328
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.2363524026
Short name T312
Test name
Test status
Simulation time 3038114518 ps
CPU time 67.94 seconds
Started Jan 21 12:43:58 PM PST 24
Finished Jan 21 12:45:07 PM PST 24
Peak memory 310384 kb
Host smart-e64415c6-dd37-4128-9ad9-ac000d16e74f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363524026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.2363524026
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.285799843
Short name T572
Test name
Test status
Simulation time 4534094787 ps
CPU time 152.41 seconds
Started Jan 21 12:44:16 PM PST 24
Finished Jan 21 12:46:49 PM PST 24
Peak memory 211120 kb
Host smart-844fbcc3-c4f3-4647-ac72-add70753c828
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285799843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_mem_partial_access.285799843
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.2176682275
Short name T289
Test name
Test status
Simulation time 27547389930 ps
CPU time 138.55 seconds
Started Jan 21 12:44:18 PM PST 24
Finished Jan 21 12:46:37 PM PST 24
Peak memory 202248 kb
Host smart-b1af944c-07db-4ca1-98d8-813842989bde
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176682275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.2176682275
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3604007026
Short name T594
Test name
Test status
Simulation time 41498946603 ps
CPU time 1047.97 seconds
Started Jan 21 12:43:51 PM PST 24
Finished Jan 21 01:01:20 PM PST 24
Peak memory 379032 kb
Host smart-567f89ca-a765-4bdc-8d49-b2d8b8334e10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604007026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3604007026
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.911800110
Short name T209
Test name
Test status
Simulation time 1697934606 ps
CPU time 104.1 seconds
Started Jan 21 12:43:50 PM PST 24
Finished Jan 21 12:45:35 PM PST 24
Peak memory 330848 kb
Host smart-9523bae5-c837-4811-8837-bb5056c355e6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911800110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.911800110
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1938557149
Short name T828
Test name
Test status
Simulation time 6232991795 ps
CPU time 353.52 seconds
Started Jan 21 12:43:59 PM PST 24
Finished Jan 21 12:49:54 PM PST 24
Peak memory 202256 kb
Host smart-0def8f0a-6ca4-4747-8bce-196c8508a6ab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938557149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.1938557149
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.1602123164
Short name T717
Test name
Test status
Simulation time 360881249 ps
CPU time 6.2 seconds
Started Jan 21 12:44:17 PM PST 24
Finished Jan 21 12:44:24 PM PST 24
Peak memory 202252 kb
Host smart-3b827b7e-6406-4847-be12-5567df04892d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602123164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1602123164
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.937284366
Short name T771
Test name
Test status
Simulation time 3133059332 ps
CPU time 1912.17 seconds
Started Jan 21 12:44:05 PM PST 24
Finished Jan 21 01:15:58 PM PST 24
Peak memory 377132 kb
Host smart-e1f55f2f-2a7e-43d4-8173-0ca92a4bc875
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937284366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.937284366
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.2986884864
Short name T633
Test name
Test status
Simulation time 7459889141 ps
CPU time 27.46 seconds
Started Jan 21 12:43:51 PM PST 24
Finished Jan 21 12:44:20 PM PST 24
Peak memory 202256 kb
Host smart-456d12a9-78f1-4f65-8f4f-f7b4cc0868c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986884864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2986884864
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.3526913708
Short name T528
Test name
Test status
Simulation time 58350829282 ps
CPU time 4671.95 seconds
Started Jan 21 12:44:35 PM PST 24
Finished Jan 21 02:02:28 PM PST 24
Peak memory 380000 kb
Host smart-a710b423-609d-427e-962a-488aeeaed770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526913708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.sram_ctrl_stress_all.3526913708
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.437604449
Short name T433
Test name
Test status
Simulation time 295680705 ps
CPU time 1129.86 seconds
Started Jan 21 12:44:24 PM PST 24
Finished Jan 21 01:03:14 PM PST 24
Peak memory 398688 kb
Host smart-3b42f05c-9bde-46e7-a650-212dc3b4eca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=437604449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.437604449
Directory /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.31355095
Short name T918
Test name
Test status
Simulation time 13966595447 ps
CPU time 261.87 seconds
Started Jan 21 12:43:50 PM PST 24
Finished Jan 21 12:48:13 PM PST 24
Peak memory 202168 kb
Host smart-eaabf4ba-9ef0-4a37-b3f2-ac042fe45082
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31355095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_stress_pipeline.31355095
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2827322404
Short name T518
Test name
Test status
Simulation time 792253666 ps
CPU time 192.12 seconds
Started Jan 21 12:44:00 PM PST 24
Finished Jan 21 12:47:13 PM PST 24
Peak memory 363724 kb
Host smart-a6b2327d-b61c-48dc-a515-bd085382bbdb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827322404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2827322404
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.2769597774
Short name T604
Test name
Test status
Simulation time 5750614318 ps
CPU time 617.29 seconds
Started Jan 21 12:46:18 PM PST 24
Finished Jan 21 12:56:37 PM PST 24
Peak memory 375708 kb
Host smart-3789874a-617b-41ee-b523-984cc48e10dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769597774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.2769597774
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.3164226315
Short name T863
Test name
Test status
Simulation time 14659934 ps
CPU time 0.62 seconds
Started Jan 21 02:08:30 PM PST 24
Finished Jan 21 02:08:32 PM PST 24
Peak memory 202096 kb
Host smart-02623e11-e234-4c7d-b975-44b5c5c05f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164226315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.3164226315
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.4188574385
Short name T524
Test name
Test status
Simulation time 24273132375 ps
CPU time 1253.71 seconds
Started Jan 21 12:44:44 PM PST 24
Finished Jan 21 01:05:39 PM PST 24
Peak memory 202168 kb
Host smart-6bf97215-29ec-42a0-ba34-4b744dcd0f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188574385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.4188574385
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.3700079740
Short name T860
Test name
Test status
Simulation time 20005376845 ps
CPU time 883.41 seconds
Started Jan 21 12:44:52 PM PST 24
Finished Jan 21 12:59:36 PM PST 24
Peak memory 374984 kb
Host smart-02a47c34-ad85-49f9-991d-a9e89a2c8ca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700079740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3700079740
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3468490074
Short name T766
Test name
Test status
Simulation time 3598230758 ps
CPU time 121.99 seconds
Started Jan 21 12:44:45 PM PST 24
Finished Jan 21 12:46:47 PM PST 24
Peak memory 349424 kb
Host smart-849da728-9c32-4adc-9702-215e143af889
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468490074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3468490074
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2208149788
Short name T520
Test name
Test status
Simulation time 27197566115 ps
CPU time 80.93 seconds
Started Jan 21 02:28:14 PM PST 24
Finished Jan 21 02:29:36 PM PST 24
Peak memory 212360 kb
Host smart-f3c56d77-c03e-4826-a997-1cca6661709c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208149788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.2208149788
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.1305826499
Short name T198
Test name
Test status
Simulation time 38204835399 ps
CPU time 147.25 seconds
Started Jan 21 12:46:18 PM PST 24
Finished Jan 21 12:48:47 PM PST 24
Peak memory 200724 kb
Host smart-88c30356-d9c5-4190-b3a7-b0463264f1ed
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305826499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.1305826499
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.2989671867
Short name T144
Test name
Test status
Simulation time 5292175679 ps
CPU time 364.36 seconds
Started Jan 21 12:44:34 PM PST 24
Finished Jan 21 12:50:39 PM PST 24
Peak memory 357152 kb
Host smart-36c5da5b-e454-49a3-b381-056655472d13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989671867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.2989671867
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.3768245603
Short name T566
Test name
Test status
Simulation time 5766178791 ps
CPU time 22.93 seconds
Started Jan 21 12:44:44 PM PST 24
Finished Jan 21 12:45:07 PM PST 24
Peak memory 202160 kb
Host smart-5a556669-6372-45a2-948e-7414fdaf8ba9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768245603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.3768245603
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.4243865693
Short name T929
Test name
Test status
Simulation time 10084837949 ps
CPU time 229.22 seconds
Started Jan 21 12:44:44 PM PST 24
Finished Jan 21 12:48:34 PM PST 24
Peak memory 202100 kb
Host smart-caa1334a-ba98-4d1e-8c36-a1642b71547e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243865693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.4243865693
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.3010408144
Short name T310
Test name
Test status
Simulation time 356058657 ps
CPU time 13.02 seconds
Started Jan 21 12:46:18 PM PST 24
Finished Jan 21 12:46:33 PM PST 24
Peak memory 200628 kb
Host smart-eb7434b5-71ac-4759-83ca-77fbab3feecc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010408144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3010408144
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.1751280116
Short name T627
Test name
Test status
Simulation time 43903516483 ps
CPU time 561.64 seconds
Started Jan 21 12:53:31 PM PST 24
Finished Jan 21 01:02:54 PM PST 24
Peak memory 376088 kb
Host smart-2c95965d-9d09-4c61-ad2b-ecb59b6c5fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751280116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1751280116
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.1680268104
Short name T749
Test name
Test status
Simulation time 2974189395 ps
CPU time 31.04 seconds
Started Jan 21 12:44:37 PM PST 24
Finished Jan 21 12:45:10 PM PST 24
Peak memory 222692 kb
Host smart-e3acf763-4884-49f3-b084-2d48ff61534d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680268104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1680268104
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.1026239106
Short name T621
Test name
Test status
Simulation time 196982589792 ps
CPU time 4073.48 seconds
Started Jan 21 12:45:07 PM PST 24
Finished Jan 21 01:53:02 PM PST 24
Peak memory 381072 kb
Host smart-796570a6-da4c-4118-ac88-10a713ea0515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026239106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.1026239106
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2810166735
Short name T956
Test name
Test status
Simulation time 1335439472 ps
CPU time 2418.68 seconds
Started Jan 21 01:10:32 PM PST 24
Finished Jan 21 01:50:54 PM PST 24
Peak memory 386452 kb
Host smart-6b58c297-6335-4231-8230-3746ba720da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2810166735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2810166735
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2770392309
Short name T424
Test name
Test status
Simulation time 9098162435 ps
CPU time 194.97 seconds
Started Jan 21 12:44:43 PM PST 24
Finished Jan 21 12:47:59 PM PST 24
Peak memory 202200 kb
Host smart-459d8b62-6428-4a62-922a-fe11b8da1e08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770392309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.2770392309
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3108286332
Short name T325
Test name
Test status
Simulation time 3108823128 ps
CPU time 44.79 seconds
Started Jan 21 12:44:45 PM PST 24
Finished Jan 21 12:45:31 PM PST 24
Peak memory 268672 kb
Host smart-87e66519-b6fc-4170-8acb-3c4a5a85a455
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108286332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3108286332
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1155234509
Short name T628
Test name
Test status
Simulation time 4361681220 ps
CPU time 221.07 seconds
Started Jan 21 12:45:24 PM PST 24
Finished Jan 21 12:49:07 PM PST 24
Peak memory 372372 kb
Host smart-359193bd-f409-4660-8273-9e84f7c61b75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155234509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.1155234509
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.2371456314
Short name T793
Test name
Test status
Simulation time 171477972 ps
CPU time 0.63 seconds
Started Jan 21 12:45:38 PM PST 24
Finished Jan 21 12:45:43 PM PST 24
Peak memory 201488 kb
Host smart-c57a8bb8-003c-42e2-9a83-99f880234613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371456314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.2371456314
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.2361216478
Short name T251
Test name
Test status
Simulation time 274680689469 ps
CPU time 1167.43 seconds
Started Jan 21 12:45:07 PM PST 24
Finished Jan 21 01:04:35 PM PST 24
Peak memory 202316 kb
Host smart-cac39689-9a37-4904-b5a5-b5af4f701112
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361216478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.2361216478
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.304116897
Short name T837
Test name
Test status
Simulation time 23835875937 ps
CPU time 73.63 seconds
Started Jan 21 12:45:22 PM PST 24
Finished Jan 21 12:46:40 PM PST 24
Peak memory 210528 kb
Host smart-5cc26d88-28d1-4201-b3c5-4b4ca5927cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304116897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_esc
alation.304116897
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.1032969371
Short name T320
Test name
Test status
Simulation time 11811549604 ps
CPU time 53.7 seconds
Started Jan 21 12:45:25 PM PST 24
Finished Jan 21 12:46:20 PM PST 24
Peak memory 272720 kb
Host smart-669c4451-7ac8-4be0-b8bc-3314e369b788
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032969371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.1032969371
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1586540107
Short name T500
Test name
Test status
Simulation time 8010630524 ps
CPU time 143.85 seconds
Started Jan 21 12:45:32 PM PST 24
Finished Jan 21 12:47:56 PM PST 24
Peak memory 218564 kb
Host smart-7aea4960-5435-48fa-85fa-febc87a04396
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586540107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.1586540107
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1653465014
Short name T441
Test name
Test status
Simulation time 15754767167 ps
CPU time 236.39 seconds
Started Jan 21 12:46:42 PM PST 24
Finished Jan 21 12:50:39 PM PST 24
Peak memory 202216 kb
Host smart-e55ef57b-e5e0-4b55-97c9-a37ca98f7406
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653465014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1653465014
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.2397740199
Short name T608
Test name
Test status
Simulation time 151690876008 ps
CPU time 1474.58 seconds
Started Jan 21 01:24:05 PM PST 24
Finished Jan 21 01:48:40 PM PST 24
Peak memory 378116 kb
Host smart-18944f35-b464-4337-a17d-2c163bb29c7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397740199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.2397740199
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.4080910307
Short name T619
Test name
Test status
Simulation time 506481331 ps
CPU time 20.67 seconds
Started Jan 21 01:08:03 PM PST 24
Finished Jan 21 01:08:26 PM PST 24
Peak memory 202084 kb
Host smart-2e97d276-f9fc-4540-8c4b-65927cfbdfb4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080910307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.4080910307
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1436600492
Short name T748
Test name
Test status
Simulation time 3368484160 ps
CPU time 204.18 seconds
Started Jan 21 12:45:14 PM PST 24
Finished Jan 21 12:48:39 PM PST 24
Peak memory 202176 kb
Host smart-3366bad7-4a7d-4833-8774-9a153ae1dfde
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436600492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.1436600492
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.3207298140
Short name T856
Test name
Test status
Simulation time 711266389 ps
CPU time 5.74 seconds
Started Jan 21 12:45:25 PM PST 24
Finished Jan 21 12:45:32 PM PST 24
Peak memory 202244 kb
Host smart-ca98e5c9-598d-4c31-b6a8-413617e0e25b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207298140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3207298140
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.2810108520
Short name T730
Test name
Test status
Simulation time 46981221084 ps
CPU time 772.33 seconds
Started Jan 21 12:45:22 PM PST 24
Finished Jan 21 12:58:18 PM PST 24
Peak memory 377936 kb
Host smart-d304698c-e852-4956-8129-23a4015308c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810108520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2810108520
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.84851757
Short name T212
Test name
Test status
Simulation time 2970828144 ps
CPU time 21.78 seconds
Started Jan 21 01:42:04 PM PST 24
Finished Jan 21 01:42:26 PM PST 24
Peak memory 202296 kb
Host smart-e9b62a03-b931-4aee-a7cf-10c8629a1fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84851757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.84851757
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3840483542
Short name T361
Test name
Test status
Simulation time 1864124966 ps
CPU time 3402.86 seconds
Started Jan 21 12:45:31 PM PST 24
Finished Jan 21 01:42:15 PM PST 24
Peak memory 630904 kb
Host smart-173899fb-870f-405f-b8fb-cecab5046439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3840483542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3840483542
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3176554984
Short name T37
Test name
Test status
Simulation time 2852291402 ps
CPU time 217.05 seconds
Started Jan 21 12:45:15 PM PST 24
Finished Jan 21 12:48:53 PM PST 24
Peak memory 202276 kb
Host smart-4b541c88-b685-4ff7-bba7-76ebd7c161a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176554984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.3176554984
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.465702096
Short name T841
Test name
Test status
Simulation time 699880676 ps
CPU time 26.53 seconds
Started Jan 21 12:45:23 PM PST 24
Finished Jan 21 12:45:52 PM PST 24
Peak memory 202272 kb
Host smart-8f463c76-a166-4a54-bab6-c018aef49b7b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465702096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.465702096
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.659686423
Short name T655
Test name
Test status
Simulation time 8991342646 ps
CPU time 801.08 seconds
Started Jan 21 12:45:54 PM PST 24
Finished Jan 21 12:59:17 PM PST 24
Peak memory 375948 kb
Host smart-0a2ecc94-29e8-4a01-a4f6-20fca1bcf597
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659686423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.sram_ctrl_access_during_key_req.659686423
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.294578495
Short name T349
Test name
Test status
Simulation time 30142748 ps
CPU time 0.64 seconds
Started Jan 21 12:46:15 PM PST 24
Finished Jan 21 12:46:16 PM PST 24
Peak memory 201352 kb
Host smart-50341819-fa54-40e5-ba03-83e5c75fd45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294578495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.294578495
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.3200279481
Short name T547
Test name
Test status
Simulation time 331934042325 ps
CPU time 1447.04 seconds
Started Jan 21 02:22:36 PM PST 24
Finished Jan 21 02:46:44 PM PST 24
Peak memory 202308 kb
Host smart-b1815c42-aabc-43b7-b342-8e1ec22105a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200279481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.3200279481
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.2157205669
Short name T36
Test name
Test status
Simulation time 16898525324 ps
CPU time 54.43 seconds
Started Jan 21 12:45:53 PM PST 24
Finished Jan 21 12:46:50 PM PST 24
Peak memory 210404 kb
Host smart-620c20e6-1414-4a7b-9670-6f5740389621
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157205669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.2157205669
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3047213169
Short name T874
Test name
Test status
Simulation time 3236732273 ps
CPU time 132.54 seconds
Started Jan 21 12:45:55 PM PST 24
Finished Jan 21 12:48:09 PM PST 24
Peak memory 359088 kb
Host smart-d1834654-6c78-4a66-98b8-2c70a8bb5f25
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047213169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3047213169
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.331355117
Short name T330
Test name
Test status
Simulation time 3233107109 ps
CPU time 130.04 seconds
Started Jan 21 12:45:54 PM PST 24
Finished Jan 21 12:48:06 PM PST 24
Peak memory 214392 kb
Host smart-e8313646-7c8c-4ea4-9a1d-8d497d456f49
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331355117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_mem_partial_access.331355117
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.3270229896
Short name T963
Test name
Test status
Simulation time 15147662140 ps
CPU time 246 seconds
Started Jan 21 12:45:56 PM PST 24
Finished Jan 21 12:50:05 PM PST 24
Peak memory 202200 kb
Host smart-96949bdb-8a94-4352-b0a5-48a69dac6dc1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270229896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.3270229896
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2079395282
Short name T731
Test name
Test status
Simulation time 9537111310 ps
CPU time 1392.05 seconds
Started Jan 21 12:45:46 PM PST 24
Finished Jan 21 01:08:59 PM PST 24
Peak memory 378152 kb
Host smart-bb7e34c6-46df-4e5e-8c7f-3c729aa0ff8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079395282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2079395282
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.207442588
Short name T402
Test name
Test status
Simulation time 830325807 ps
CPU time 14.06 seconds
Started Jan 21 12:45:47 PM PST 24
Finished Jan 21 12:46:02 PM PST 24
Peak memory 202016 kb
Host smart-ebd3002f-30eb-4fdc-8072-96c7a6dc4fe3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207442588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s
ram_ctrl_partial_access.207442588
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.971510678
Short name T523
Test name
Test status
Simulation time 28381135552 ps
CPU time 351.35 seconds
Started Jan 21 12:45:56 PM PST 24
Finished Jan 21 12:51:50 PM PST 24
Peak memory 202140 kb
Host smart-a43932da-9bb7-4c06-b664-f519fe9b7bf7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971510678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.sram_ctrl_partial_access_b2b.971510678
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.2276963685
Short name T254
Test name
Test status
Simulation time 360897041 ps
CPU time 13.28 seconds
Started Jan 21 12:45:54 PM PST 24
Finished Jan 21 12:46:09 PM PST 24
Peak memory 202284 kb
Host smart-814140fc-d293-4039-aee7-3de86b726d98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276963685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2276963685
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.4037537191
Short name T854
Test name
Test status
Simulation time 4919563578 ps
CPU time 1189.95 seconds
Started Jan 21 01:07:35 PM PST 24
Finished Jan 21 01:27:26 PM PST 24
Peak memory 372056 kb
Host smart-6fd5a7d9-a6d8-41ee-ae43-f360a179c9ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037537191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.4037537191
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.2816050345
Short name T236
Test name
Test status
Simulation time 1264166628 ps
CPU time 23.47 seconds
Started Jan 21 12:46:45 PM PST 24
Finished Jan 21 12:47:09 PM PST 24
Peak memory 201072 kb
Host smart-15c69f54-2a73-4f80-b941-50b9a2e35ee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816050345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2816050345
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.3908167731
Short name T526
Test name
Test status
Simulation time 49663834698 ps
CPU time 2435.32 seconds
Started Jan 21 01:10:26 PM PST 24
Finished Jan 21 01:51:02 PM PST 24
Peak memory 377244 kb
Host smart-80080c05-8b5b-441e-88da-d690e2270d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908167731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.3908167731
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3397159077
Short name T729
Test name
Test status
Simulation time 1068609329 ps
CPU time 3144.12 seconds
Started Jan 21 12:45:55 PM PST 24
Finished Jan 21 01:38:21 PM PST 24
Peak memory 593068 kb
Host smart-89cac024-f824-4587-a236-d8ae6cb03e0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3397159077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3397159077
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.284468432
Short name T280
Test name
Test status
Simulation time 41208411940 ps
CPU time 447.49 seconds
Started Jan 21 12:46:42 PM PST 24
Finished Jan 21 12:54:10 PM PST 24
Peak memory 202088 kb
Host smart-41655832-7dda-4518-a795-6f89c791085d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284468432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_stress_pipeline.284468432
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3094792300
Short name T390
Test name
Test status
Simulation time 853690935 ps
CPU time 64.44 seconds
Started Jan 21 12:46:42 PM PST 24
Finished Jan 21 12:47:47 PM PST 24
Peak memory 307504 kb
Host smart-b59496c2-f7db-4317-9006-0c180c468505
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094792300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.3094792300
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1917725371
Short name T286
Test name
Test status
Simulation time 10243810018 ps
CPU time 996.36 seconds
Started Jan 21 12:32:09 PM PST 24
Finished Jan 21 12:49:02 PM PST 24
Peak memory 376988 kb
Host smart-8ce2a778-2a57-400a-91bb-878b137562d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917725371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.1917725371
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1829812388
Short name T421
Test name
Test status
Simulation time 30823686 ps
CPU time 0.6 seconds
Started Jan 21 12:32:23 PM PST 24
Finished Jan 21 12:32:30 PM PST 24
Peak memory 201948 kb
Host smart-5a4b1413-9d2a-457c-a7d4-2e2b868a063c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829812388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1829812388
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.635666650
Short name T214
Test name
Test status
Simulation time 50836841902 ps
CPU time 1109.97 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:50:54 PM PST 24
Peak memory 201876 kb
Host smart-74b41f4a-fd56-484d-98b0-c659c9d90d8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635666650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.635666650
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.1975948714
Short name T395
Test name
Test status
Simulation time 31760971583 ps
CPU time 302.11 seconds
Started Jan 21 12:32:19 PM PST 24
Finished Jan 21 12:37:31 PM PST 24
Peak memory 350516 kb
Host smart-b4295671-4107-4163-832e-d2e70a88c25c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975948714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.1975948714
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.418291280
Short name T307
Test name
Test status
Simulation time 25617289551 ps
CPU time 81.35 seconds
Started Jan 21 12:32:18 PM PST 24
Finished Jan 21 12:33:50 PM PST 24
Peak memory 210412 kb
Host smart-bc3a1277-9e69-4abe-a459-79a7e35bc7bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418291280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca
lation.418291280
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.2998538027
Short name T725
Test name
Test status
Simulation time 2885861467 ps
CPU time 36.59 seconds
Started Jan 21 12:32:11 PM PST 24
Finished Jan 21 12:33:03 PM PST 24
Peak memory 250992 kb
Host smart-62d8a90d-92ba-478b-ad88-73a5f19c0bad
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998538027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.2998538027
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.445614102
Short name T425
Test name
Test status
Simulation time 4702588261 ps
CPU time 139.17 seconds
Started Jan 21 12:32:09 PM PST 24
Finished Jan 21 12:34:44 PM PST 24
Peak memory 211560 kb
Host smart-ad76a377-4aa5-4756-875b-276a1f8399e5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445614102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_mem_partial_access.445614102
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.1719779962
Short name T277
Test name
Test status
Simulation time 14057184075 ps
CPU time 258.69 seconds
Started Jan 21 12:32:19 PM PST 24
Finished Jan 21 12:36:47 PM PST 24
Peak memory 202140 kb
Host smart-854b8822-0f6e-49d5-8e6b-5a90855effdc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719779962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl
_mem_walk.1719779962
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.3040607989
Short name T753
Test name
Test status
Simulation time 1686501914 ps
CPU time 32.53 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:32:57 PM PST 24
Peak memory 201764 kb
Host smart-7034903c-b2cf-464c-9b2e-ef727cc61f26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040607989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.3040607989
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.4138308830
Short name T257
Test name
Test status
Simulation time 711644822 ps
CPU time 11.77 seconds
Started Jan 21 12:32:21 PM PST 24
Finished Jan 21 12:32:41 PM PST 24
Peak memory 213584 kb
Host smart-97e7837c-9ef9-4614-b4ae-be05e6d6fac2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138308830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.4138308830
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2386755730
Short name T693
Test name
Test status
Simulation time 6643074772 ps
CPU time 400.38 seconds
Started Jan 21 12:32:12 PM PST 24
Finished Jan 21 12:39:07 PM PST 24
Peak memory 202240 kb
Host smart-d1decb5f-59f7-46c8-bf76-abbd23bd8e78
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386755730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.2386755730
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.4219690493
Short name T308
Test name
Test status
Simulation time 362945119 ps
CPU time 13.08 seconds
Started Jan 21 12:32:16 PM PST 24
Finished Jan 21 12:32:41 PM PST 24
Peak memory 202316 kb
Host smart-0fd24520-07e7-4790-b1bd-23bfd8fc449f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219690493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4219690493
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.172799076
Short name T945
Test name
Test status
Simulation time 1546925451 ps
CPU time 348.73 seconds
Started Jan 21 12:32:11 PM PST 24
Finished Jan 21 12:38:15 PM PST 24
Peak memory 369860 kb
Host smart-687ff5a5-791a-463f-a846-d2c43c19eb1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172799076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.172799076
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3731643191
Short name T33
Test name
Test status
Simulation time 1435477878 ps
CPU time 3.16 seconds
Started Jan 21 12:32:11 PM PST 24
Finished Jan 21 12:32:29 PM PST 24
Peak memory 221532 kb
Host smart-20503aed-37a6-4706-9e94-d64d01a386b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731643191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3731643191
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.2589039106
Short name T680
Test name
Test status
Simulation time 9453918218 ps
CPU time 137.18 seconds
Started Jan 21 12:32:06 PM PST 24
Finished Jan 21 12:34:41 PM PST 24
Peak memory 370924 kb
Host smart-a811dcf9-df71-4087-a1dd-8c36770d4795
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589039106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2589039106
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.4224866402
Short name T453
Test name
Test status
Simulation time 944935915816 ps
CPU time 3920.59 seconds
Started Jan 21 12:32:11 PM PST 24
Finished Jan 21 01:37:47 PM PST 24
Peak memory 376992 kb
Host smart-72b6df23-3095-4bd3-9deb-5cd9dcf5c7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224866402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.4224866402
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.798600722
Short name T873
Test name
Test status
Simulation time 421602128 ps
CPU time 2834.72 seconds
Started Jan 21 12:32:09 PM PST 24
Finished Jan 21 01:19:40 PM PST 24
Peak memory 519408 kb
Host smart-6bf4db8d-afd2-4bb5-a148-c66f08cc730a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=798600722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.798600722
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.1730255008
Short name T404
Test name
Test status
Simulation time 15399087433 ps
CPU time 268.7 seconds
Started Jan 21 12:32:22 PM PST 24
Finished Jan 21 12:36:58 PM PST 24
Peak memory 202092 kb
Host smart-1ae34397-d885-47ae-8d44-bce4c230f56e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730255008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.1730255008
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3761505637
Short name T538
Test name
Test status
Simulation time 791537545 ps
CPU time 153.54 seconds
Started Jan 21 12:32:12 PM PST 24
Finished Jan 21 12:35:00 PM PST 24
Peak memory 371896 kb
Host smart-dff8e360-7ae8-43ec-925e-860b0b51f255
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761505637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3761505637
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3897567674
Short name T592
Test name
Test status
Simulation time 100409351540 ps
CPU time 1121.43 seconds
Started Jan 21 12:46:28 PM PST 24
Finished Jan 21 01:05:10 PM PST 24
Peak memory 377016 kb
Host smart-42ee15df-69c0-4aa3-ba1b-a2c2bcdcf3ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897567674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.3897567674
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.3837346954
Short name T759
Test name
Test status
Simulation time 13190972 ps
CPU time 0.74 seconds
Started Jan 21 12:47:42 PM PST 24
Finished Jan 21 12:47:45 PM PST 24
Peak memory 199952 kb
Host smart-035d855d-1c46-4310-a0c9-06d7626ece7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837346954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.3837346954
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.1161391559
Short name T411
Test name
Test status
Simulation time 61570104595 ps
CPU time 1673.19 seconds
Started Jan 21 12:46:18 PM PST 24
Finished Jan 21 01:14:12 PM PST 24
Peak memory 202244 kb
Host smart-c5ec0922-4b1a-486c-98ed-5e507d98f806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161391559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.1161391559
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.451365113
Short name T890
Test name
Test status
Simulation time 4567083250 ps
CPU time 249.57 seconds
Started Jan 21 12:46:26 PM PST 24
Finished Jan 21 12:50:37 PM PST 24
Peak memory 372876 kb
Host smart-c1d2e383-e638-40c6-aa30-c830f64bb0ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451365113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executabl
e.451365113
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.2843231425
Short name T666
Test name
Test status
Simulation time 3575938861 ps
CPU time 73.62 seconds
Started Jan 21 12:47:42 PM PST 24
Finished Jan 21 12:48:58 PM PST 24
Peak memory 208916 kb
Host smart-2018545b-344e-43da-9e24-0fe60bb070f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843231425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.2843231425
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.3656290421
Short name T234
Test name
Test status
Simulation time 1652604015 ps
CPU time 151.37 seconds
Started Jan 21 12:46:20 PM PST 24
Finished Jan 21 12:48:52 PM PST 24
Peak memory 357612 kb
Host smart-a59e3932-20d1-487f-9292-d0850f7b4757
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656290421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.3656290421
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3434048335
Short name T288
Test name
Test status
Simulation time 3235732372 ps
CPU time 71.35 seconds
Started Jan 21 12:46:44 PM PST 24
Finished Jan 21 12:47:56 PM PST 24
Peak memory 218488 kb
Host smart-01fbe5c7-a78b-4c1b-a378-57e280f86188
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434048335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.3434048335
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.1303254125
Short name T707
Test name
Test status
Simulation time 16416385195 ps
CPU time 250.75 seconds
Started Jan 21 12:46:41 PM PST 24
Finished Jan 21 12:50:53 PM PST 24
Peak memory 202272 kb
Host smart-a9965681-f4ff-4fa4-8823-9b8f4151ae28
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303254125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.1303254125
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.379628411
Short name T244
Test name
Test status
Simulation time 8886542543 ps
CPU time 182.8 seconds
Started Jan 21 12:46:14 PM PST 24
Finished Jan 21 12:49:17 PM PST 24
Peak memory 349844 kb
Host smart-c2066040-3ad5-46c6-a4cc-4c5548d2f706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379628411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multip
le_keys.379628411
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.3556610516
Short name T505
Test name
Test status
Simulation time 22630089416 ps
CPU time 32.5 seconds
Started Jan 21 12:46:20 PM PST 24
Finished Jan 21 12:46:53 PM PST 24
Peak memory 202020 kb
Host smart-e8057384-cf91-441f-b6ad-a1b0b0a1230d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556610516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.3556610516
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1222180073
Short name T298
Test name
Test status
Simulation time 24844607778 ps
CPU time 301.7 seconds
Started Jan 21 12:46:19 PM PST 24
Finished Jan 21 12:51:22 PM PST 24
Peak memory 202088 kb
Host smart-a8902c30-90c1-4213-9c26-cf0c8470518c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222180073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.1222180073
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.1704580996
Short name T710
Test name
Test status
Simulation time 390709000 ps
CPU time 6.41 seconds
Started Jan 21 12:46:37 PM PST 24
Finished Jan 21 12:46:44 PM PST 24
Peak memory 202380 kb
Host smart-bea6dcd3-52e4-41b8-b6cf-f81983a3d842
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704580996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1704580996
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3859541306
Short name T50
Test name
Test status
Simulation time 45749347485 ps
CPU time 987.26 seconds
Started Jan 21 12:46:28 PM PST 24
Finished Jan 21 01:02:56 PM PST 24
Peak memory 374896 kb
Host smart-27532fa7-b03c-4868-99e1-0e5891a065cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859541306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3859541306
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.3475217416
Short name T199
Test name
Test status
Simulation time 1616675965 ps
CPU time 145.99 seconds
Started Jan 21 12:46:18 PM PST 24
Finished Jan 21 12:48:45 PM PST 24
Peak memory 364636 kb
Host smart-74456e20-f4b1-4403-b67a-6b3eda128873
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475217416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3475217416
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2048328395
Short name T715
Test name
Test status
Simulation time 1909393520 ps
CPU time 2471.55 seconds
Started Jan 21 12:47:42 PM PST 24
Finished Jan 21 01:28:56 PM PST 24
Peak memory 434588 kb
Host smart-79011e10-36c9-4076-b551-b641965ad0ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2048328395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2048328395
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2493829913
Short name T303
Test name
Test status
Simulation time 23803906203 ps
CPU time 342.79 seconds
Started Jan 21 12:46:13 PM PST 24
Finished Jan 21 12:51:56 PM PST 24
Peak memory 202216 kb
Host smart-51e04c99-1348-4900-bf21-bdc19b15d7aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493829913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2493829913
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3184861614
Short name T648
Test name
Test status
Simulation time 737731382 ps
CPU time 27.67 seconds
Started Jan 21 12:46:21 PM PST 24
Finished Jan 21 12:46:50 PM PST 24
Peak memory 223964 kb
Host smart-7ecba8d0-b090-4cbc-a8db-d32a0050e45c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184861614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3184861614
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1444653001
Short name T812
Test name
Test status
Simulation time 16848873692 ps
CPU time 685.7 seconds
Started Jan 21 01:20:09 PM PST 24
Finished Jan 21 01:31:37 PM PST 24
Peak memory 377072 kb
Host smart-b6ff5a8a-ea59-4690-84ec-41bab0ad79ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444653001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.1444653001
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.2854406051
Short name T23
Test name
Test status
Simulation time 24858632 ps
CPU time 0.68 seconds
Started Jan 21 01:27:17 PM PST 24
Finished Jan 21 01:27:18 PM PST 24
Peak memory 202384 kb
Host smart-767d0639-0c51-4771-b9e5-cb612a04879c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854406051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.2854406051
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.2439570878
Short name T826
Test name
Test status
Simulation time 48505216456 ps
CPU time 772.04 seconds
Started Jan 21 12:46:45 PM PST 24
Finished Jan 21 12:59:38 PM PST 24
Peak memory 202176 kb
Host smart-2e977f97-ddf0-4c58-a044-669d51dc0005
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439570878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.2439570878
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.729552278
Short name T406
Test name
Test status
Simulation time 8514635529 ps
CPU time 74.26 seconds
Started Jan 21 12:48:07 PM PST 24
Finished Jan 21 12:49:26 PM PST 24
Peak memory 210200 kb
Host smart-4b0065ae-591e-4dca-88ca-435734325835
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729552278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_esc
alation.729552278
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.2946323832
Short name T334
Test name
Test status
Simulation time 4456833765 ps
CPU time 47.27 seconds
Started Jan 21 12:48:07 PM PST 24
Finished Jan 21 12:48:59 PM PST 24
Peak memory 283516 kb
Host smart-6895225e-3406-41ac-96ca-ac20a4ae716b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946323832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.2946323832
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1984240784
Short name T671
Test name
Test status
Simulation time 2520792621 ps
CPU time 75.3 seconds
Started Jan 21 12:47:04 PM PST 24
Finished Jan 21 12:48:20 PM PST 24
Peak memory 211632 kb
Host smart-e147f068-6ecf-470d-9d0c-020fe1ce0e90
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984240784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1984240784
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.1547946827
Short name T205
Test name
Test status
Simulation time 21877843671 ps
CPU time 242.03 seconds
Started Jan 21 12:47:03 PM PST 24
Finished Jan 21 12:51:05 PM PST 24
Peak memory 202224 kb
Host smart-b2b6813f-0eb3-4016-a6ea-9e552617e75b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547946827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.1547946827
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.1440335353
Short name T583
Test name
Test status
Simulation time 5847476503 ps
CPU time 25.52 seconds
Started Jan 21 12:48:07 PM PST 24
Finished Jan 21 12:48:37 PM PST 24
Peak memory 201732 kb
Host smart-20ccb9f1-5766-4c84-b5d9-06b2bbf82d90
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440335353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.1440335353
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.395618310
Short name T668
Test name
Test status
Simulation time 74318644738 ps
CPU time 425.78 seconds
Started Jan 21 12:48:07 PM PST 24
Finished Jan 21 12:55:18 PM PST 24
Peak memory 201692 kb
Host smart-97dc62c0-51d9-4301-83ec-4d4f007a5360
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395618310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.395618310
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.369658640
Short name T305
Test name
Test status
Simulation time 683651895 ps
CPU time 6.31 seconds
Started Jan 21 01:11:54 PM PST 24
Finished Jan 21 01:12:01 PM PST 24
Peak memory 202456 kb
Host smart-621d16d7-f7bb-4896-a280-d8beb5c75f4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369658640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.369658640
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.3392541553
Short name T611
Test name
Test status
Simulation time 57415080258 ps
CPU time 725.83 seconds
Started Jan 21 12:47:04 PM PST 24
Finished Jan 21 12:59:11 PM PST 24
Peak memory 371948 kb
Host smart-70908054-2687-497d-9872-94d66700da64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392541553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3392541553
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.25549717
Short name T875
Test name
Test status
Simulation time 3742883208 ps
CPU time 108.8 seconds
Started Jan 21 12:46:45 PM PST 24
Finished Jan 21 12:48:35 PM PST 24
Peak memory 356500 kb
Host smart-ed905422-da14-4d02-a639-fad4a3c2ca53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.25549717
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2973433322
Short name T540
Test name
Test status
Simulation time 1745296455 ps
CPU time 2393.66 seconds
Started Jan 21 12:47:03 PM PST 24
Finished Jan 21 01:26:57 PM PST 24
Peak memory 433336 kb
Host smart-ef05b1af-eb0e-4cae-a82e-21d65fb22dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2973433322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2973433322
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.2040137426
Short name T727
Test name
Test status
Simulation time 4583524274 ps
CPU time 396.85 seconds
Started Jan 21 12:46:54 PM PST 24
Finished Jan 21 12:53:31 PM PST 24
Peak memory 210668 kb
Host smart-1fac60a0-f83f-4bdd-96a8-c9ecbb381b73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040137426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.2040137426
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.903985487
Short name T388
Test name
Test status
Simulation time 3160634670 ps
CPU time 29.5 seconds
Started Jan 21 01:09:55 PM PST 24
Finished Jan 21 01:10:25 PM PST 24
Peak memory 210560 kb
Host smart-61c5a6e0-dc06-465b-9dc7-78f21f334f85
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903985487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_throughput_w_partial_write.903985487
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.630005739
Short name T339
Test name
Test status
Simulation time 40085081528 ps
CPU time 1421.3 seconds
Started Jan 21 12:47:28 PM PST 24
Finished Jan 21 01:11:10 PM PST 24
Peak memory 378064 kb
Host smart-fa448660-c318-4c19-b813-22d61c35b413
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630005739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.sram_ctrl_access_during_key_req.630005739
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.3071821761
Short name T808
Test name
Test status
Simulation time 22261082 ps
CPU time 0.68 seconds
Started Jan 21 12:47:39 PM PST 24
Finished Jan 21 12:47:40 PM PST 24
Peak memory 201404 kb
Host smart-45882e61-e955-4dce-8283-fa74683507ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071821761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.3071821761
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.1557404055
Short name T925
Test name
Test status
Simulation time 116266152059 ps
CPU time 1803.72 seconds
Started Jan 21 01:15:50 PM PST 24
Finished Jan 21 01:45:54 PM PST 24
Peak memory 202352 kb
Host smart-58189168-5d2b-4be3-9eea-353366300827
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557404055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.1557404055
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.168079364
Short name T474
Test name
Test status
Simulation time 24057245333 ps
CPU time 394.05 seconds
Started Jan 21 12:47:31 PM PST 24
Finished Jan 21 12:54:05 PM PST 24
Peak memory 364544 kb
Host smart-7229798b-7534-4c22-a40a-5fa2cc057b32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168079364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl
e.168079364
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.3540958759
Short name T256
Test name
Test status
Simulation time 2795030095 ps
CPU time 28.2 seconds
Started Jan 21 12:47:32 PM PST 24
Finished Jan 21 12:48:01 PM PST 24
Peak memory 210776 kb
Host smart-a5525823-8048-43e1-ab1c-cfd49d59d2f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540958759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.3540958759
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.4024858082
Short name T726
Test name
Test status
Simulation time 2621271997 ps
CPU time 74.88 seconds
Started Jan 21 12:47:32 PM PST 24
Finished Jan 21 12:48:47 PM PST 24
Peak memory 211252 kb
Host smart-91ea3dc2-45bf-4fde-9613-6be3e6da1275
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024858082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.4024858082
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.269607812
Short name T365
Test name
Test status
Simulation time 38255961480 ps
CPU time 154.87 seconds
Started Jan 21 12:47:32 PM PST 24
Finished Jan 21 12:50:07 PM PST 24
Peak memory 202364 kb
Host smart-37152824-c7a3-40ba-a4e1-977878d1097c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269607812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl
_mem_walk.269607812
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.3535503219
Short name T652
Test name
Test status
Simulation time 15570949427 ps
CPU time 974.86 seconds
Started Jan 21 01:59:23 PM PST 24
Finished Jan 21 02:15:39 PM PST 24
Peak memory 378124 kb
Host smart-d93b1381-6cbc-45b1-a30c-afb288eeedaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535503219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.3535503219
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.4007153553
Short name T639
Test name
Test status
Simulation time 710461369 ps
CPU time 29.56 seconds
Started Jan 21 12:47:30 PM PST 24
Finished Jan 21 12:48:00 PM PST 24
Peak memory 294944 kb
Host smart-cb73fae0-ad2f-436e-bdb4-5254911fc27b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007153553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.4007153553
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1422153127
Short name T326
Test name
Test status
Simulation time 15630935784 ps
CPU time 269.28 seconds
Started Jan 21 12:47:28 PM PST 24
Finished Jan 21 12:51:58 PM PST 24
Peak memory 202068 kb
Host smart-8b2de5f2-4cf7-4f20-9b5d-0f4ed74d782d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422153127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1422153127
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3746077123
Short name T418
Test name
Test status
Simulation time 355501463 ps
CPU time 5.64 seconds
Started Jan 21 01:13:32 PM PST 24
Finished Jan 21 01:13:45 PM PST 24
Peak memory 202412 kb
Host smart-2f591f3e-b9a6-45cd-9f04-8b18f1c35167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746077123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3746077123
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.3597088504
Short name T52
Test name
Test status
Simulation time 11291050956 ps
CPU time 1011.54 seconds
Started Jan 21 01:27:56 PM PST 24
Finished Jan 21 01:44:49 PM PST 24
Peak memory 377184 kb
Host smart-2e5d8f4d-fee0-4297-a3cd-770a3a8861eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597088504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3597088504
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.2502425977
Short name T491
Test name
Test status
Simulation time 707043050 ps
CPU time 13.77 seconds
Started Jan 21 01:21:59 PM PST 24
Finished Jan 21 01:22:15 PM PST 24
Peak memory 202240 kb
Host smart-454f4395-7bad-41cb-a4d1-7b75717f937b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502425977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2502425977
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3927493489
Short name T368
Test name
Test status
Simulation time 23132008427 ps
CPU time 5533.88 seconds
Started Jan 21 12:47:38 PM PST 24
Finished Jan 21 02:19:53 PM PST 24
Peak memory 614488 kb
Host smart-548f1d51-d8cf-4267-bc5b-5ee95d0287a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3927493489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3927493489
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.1801145523
Short name T692
Test name
Test status
Simulation time 61162521276 ps
CPU time 308.54 seconds
Started Jan 21 01:25:51 PM PST 24
Finished Jan 21 01:31:00 PM PST 24
Peak memory 202312 kb
Host smart-aab55cec-cdef-4c86-9829-d6c729d7fd4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801145523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.1801145523
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3432047394
Short name T394
Test name
Test status
Simulation time 5164622945 ps
CPU time 27.56 seconds
Started Jan 21 01:03:31 PM PST 24
Finished Jan 21 01:03:59 PM PST 24
Peak memory 210524 kb
Host smart-5587cbef-1e91-4db2-83d1-1f297b5735bc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432047394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.3432047394
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2578139179
Short name T85
Test name
Test status
Simulation time 1945374748 ps
CPU time 374.91 seconds
Started Jan 21 12:47:42 PM PST 24
Finished Jan 21 12:53:58 PM PST 24
Peak memory 372820 kb
Host smart-a9abf153-baf2-406d-853f-a61968441336
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578139179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2578139179
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.849943909
Short name T635
Test name
Test status
Simulation time 40246423 ps
CPU time 0.65 seconds
Started Jan 21 12:47:55 PM PST 24
Finished Jan 21 12:47:58 PM PST 24
Peak memory 202012 kb
Host smart-24afc22e-0239-4506-9538-e6c76f91e265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849943909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.849943909
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.3134002136
Short name T884
Test name
Test status
Simulation time 32897604651 ps
CPU time 548.96 seconds
Started Jan 21 12:47:41 PM PST 24
Finished Jan 21 12:56:51 PM PST 24
Peak memory 202200 kb
Host smart-692dbfbf-94e3-4209-9380-cfb8733f9fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134002136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.3134002136
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.4287976351
Short name T240
Test name
Test status
Simulation time 123882432069 ps
CPU time 101.55 seconds
Started Jan 21 12:47:42 PM PST 24
Finished Jan 21 12:49:26 PM PST 24
Peak memory 210284 kb
Host smart-e8d93d4f-4ca6-420a-b9af-840f755c77a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287976351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.4287976351
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.3489779131
Short name T195
Test name
Test status
Simulation time 806813111 ps
CPU time 94 seconds
Started Jan 21 12:47:40 PM PST 24
Finished Jan 21 12:49:15 PM PST 24
Peak memory 327080 kb
Host smart-7370d430-18b4-4481-9edd-0ab96fe2a109
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489779131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.3489779131
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.394130660
Short name T588
Test name
Test status
Simulation time 991133164 ps
CPU time 74.51 seconds
Started Jan 21 12:47:54 PM PST 24
Finished Jan 21 12:49:12 PM PST 24
Peak memory 211184 kb
Host smart-239c5032-6893-4500-af70-d09dbf77d032
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394130660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.sram_ctrl_mem_partial_access.394130660
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.1883027153
Short name T939
Test name
Test status
Simulation time 2048508464 ps
CPU time 122.21 seconds
Started Jan 21 01:09:32 PM PST 24
Finished Jan 21 01:11:35 PM PST 24
Peak memory 202280 kb
Host smart-794d274f-2224-48bf-b39e-1e62d36e4464
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883027153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.1883027153
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.717774060
Short name T713
Test name
Test status
Simulation time 1827697890 ps
CPU time 41.3 seconds
Started Jan 21 12:47:41 PM PST 24
Finished Jan 21 12:48:23 PM PST 24
Peak memory 207252 kb
Host smart-2b95986c-daca-469a-be8f-c4512325180d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717774060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip
le_keys.717774060
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.2144974354
Short name T696
Test name
Test status
Simulation time 404130976 ps
CPU time 23.86 seconds
Started Jan 21 01:08:49 PM PST 24
Finished Jan 21 01:09:14 PM PST 24
Peak memory 244188 kb
Host smart-502d1cac-e30e-4a26-84a1-d20864444888
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144974354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.2144974354
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2712789544
Short name T571
Test name
Test status
Simulation time 25911527839 ps
CPU time 395.9 seconds
Started Jan 21 12:47:41 PM PST 24
Finished Jan 21 12:54:17 PM PST 24
Peak memory 202120 kb
Host smart-ae0fdfb0-1440-46d2-ad00-955f619c160b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712789544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.2712789544
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.765132475
Short name T329
Test name
Test status
Simulation time 345644167 ps
CPU time 5.03 seconds
Started Jan 21 12:47:54 PM PST 24
Finished Jan 21 12:48:02 PM PST 24
Peak memory 202260 kb
Host smart-7fcceca3-0288-47d5-b5d8-6ed533513d6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765132475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.765132475
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.402227632
Short name T795
Test name
Test status
Simulation time 30110664581 ps
CPU time 734.34 seconds
Started Jan 21 01:21:14 PM PST 24
Finished Jan 21 01:33:29 PM PST 24
Peak memory 370232 kb
Host smart-325ba9b2-448d-4b33-870a-9c34b337703b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402227632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.402227632
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.1837746187
Short name T362
Test name
Test status
Simulation time 5573010428 ps
CPU time 29.25 seconds
Started Jan 21 12:47:38 PM PST 24
Finished Jan 21 12:48:08 PM PST 24
Peak memory 202124 kb
Host smart-07208f52-6225-4300-b16f-bd260dd5aeaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837746187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1837746187
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1256858875
Short name T116
Test name
Test status
Simulation time 607727398 ps
CPU time 439.09 seconds
Started Jan 21 12:47:55 PM PST 24
Finished Jan 21 12:55:16 PM PST 24
Peak memory 377740 kb
Host smart-e2a813e0-7a14-4c08-9352-74e7ac8a68ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1256858875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1256858875
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1629678686
Short name T850
Test name
Test status
Simulation time 10076735834 ps
CPU time 171.69 seconds
Started Jan 21 12:47:39 PM PST 24
Finished Jan 21 12:50:31 PM PST 24
Peak memory 202228 kb
Host smart-655ce2bb-8cb7-45db-8ba4-f17538556904
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629678686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1629678686
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1037791630
Short name T141
Test name
Test status
Simulation time 970480074 ps
CPU time 154.3 seconds
Started Jan 21 12:47:40 PM PST 24
Finished Jan 21 12:50:15 PM PST 24
Peak memory 363540 kb
Host smart-1ed96b28-3298-40a9-8114-55f9598dda56
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037791630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.1037791630
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3514243221
Short name T565
Test name
Test status
Simulation time 11654325357 ps
CPU time 685.84 seconds
Started Jan 21 12:48:31 PM PST 24
Finished Jan 21 01:00:00 PM PST 24
Peak memory 358784 kb
Host smart-6c31df15-6c5c-42ba-958e-2f26ecdc970c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514243221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.3514243221
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.3909591938
Short name T342
Test name
Test status
Simulation time 111054265 ps
CPU time 0.66 seconds
Started Jan 21 12:48:48 PM PST 24
Finished Jan 21 12:48:50 PM PST 24
Peak memory 202100 kb
Host smart-02dbc5eb-a3c5-4d8d-8506-ac69e242dbb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909591938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.3909591938
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.2462558183
Short name T943
Test name
Test status
Simulation time 110969882918 ps
CPU time 2039.31 seconds
Started Jan 21 01:14:28 PM PST 24
Finished Jan 21 01:48:29 PM PST 24
Peak memory 202272 kb
Host smart-fb750487-147f-46a0-a5e9-2db70d752ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462558183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.2462558183
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.2913174366
Short name T428
Test name
Test status
Simulation time 76905862934 ps
CPU time 1129.79 seconds
Started Jan 21 12:48:32 PM PST 24
Finished Jan 21 01:07:26 PM PST 24
Peak memory 376000 kb
Host smart-8f67cb44-3f3d-4e5b-95a7-846131a6f031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913174366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.2913174366
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.4167687689
Short name T953
Test name
Test status
Simulation time 41928499681 ps
CPU time 119.29 seconds
Started Jan 21 01:26:23 PM PST 24
Finished Jan 21 01:28:23 PM PST 24
Peak memory 210388 kb
Host smart-fcefcdd2-c65b-4f8e-a8be-a201808e1f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167687689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.4167687689
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3375357723
Short name T13
Test name
Test status
Simulation time 4309907245 ps
CPU time 36.79 seconds
Started Jan 21 01:16:34 PM PST 24
Finished Jan 21 01:17:12 PM PST 24
Peak memory 240444 kb
Host smart-8492eeb1-6435-452d-b786-5eda4108919a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375357723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3375357723
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3726837946
Short name T87
Test name
Test status
Simulation time 2722776996 ps
CPU time 76.24 seconds
Started Jan 21 12:48:39 PM PST 24
Finished Jan 21 12:49:57 PM PST 24
Peak memory 211068 kb
Host smart-42d3ecb5-a9b1-4a91-a87c-82a67cbf4b04
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726837946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.3726837946
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.1182836455
Short name T426
Test name
Test status
Simulation time 29912140526 ps
CPU time 141.12 seconds
Started Jan 21 12:48:30 PM PST 24
Finished Jan 21 12:50:55 PM PST 24
Peak memory 202224 kb
Host smart-268c2741-7300-4415-8ccc-142727e9205e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182836455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.1182836455
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.2855788126
Short name T914
Test name
Test status
Simulation time 22858975690 ps
CPU time 355.68 seconds
Started Jan 21 01:42:43 PM PST 24
Finished Jan 21 01:48:39 PM PST 24
Peak memory 354524 kb
Host smart-df63556a-a61c-4ce2-9946-e73433d53016
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855788126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.2855788126
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.148907571
Short name T374
Test name
Test status
Simulation time 670618631 ps
CPU time 10.9 seconds
Started Jan 21 12:48:03 PM PST 24
Finished Jan 21 12:48:15 PM PST 24
Peak memory 202008 kb
Host smart-a6794124-1bf0-427d-8342-a6746b992002
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148907571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.s
ram_ctrl_partial_access.148907571
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2460583496
Short name T213
Test name
Test status
Simulation time 11948835771 ps
CPU time 377.6 seconds
Started Jan 21 02:35:38 PM PST 24
Finished Jan 21 02:41:56 PM PST 24
Peak memory 202280 kb
Host smart-5462f721-1bb9-4bda-8080-fb57b502be85
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460583496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.2460583496
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.737289094
Short name T718
Test name
Test status
Simulation time 1400790000 ps
CPU time 14.7 seconds
Started Jan 21 12:48:31 PM PST 24
Finished Jan 21 12:48:49 PM PST 24
Peak memory 202356 kb
Host smart-492e593a-38f1-4e1b-8ca2-b5259334f3ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737289094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.737289094
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.3960534942
Short name T218
Test name
Test status
Simulation time 10620165682 ps
CPU time 858.41 seconds
Started Jan 21 12:48:30 PM PST 24
Finished Jan 21 01:02:53 PM PST 24
Peak memory 378036 kb
Host smart-988bbdbc-bc5e-4861-b61a-de4f5f901316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960534942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3960534942
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.2016419885
Short name T554
Test name
Test status
Simulation time 1374920371 ps
CPU time 143.08 seconds
Started Jan 21 12:47:58 PM PST 24
Finished Jan 21 12:50:26 PM PST 24
Peak memory 367748 kb
Host smart-946fbeae-88b2-4572-b82f-d73957c8f9aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016419885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2016419885
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1327250559
Short name T789
Test name
Test status
Simulation time 2038170342 ps
CPU time 3371.76 seconds
Started Jan 21 12:48:39 PM PST 24
Finished Jan 21 01:44:53 PM PST 24
Peak memory 431936 kb
Host smart-8329b56c-f73b-4da1-b4ce-97d65e86b354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1327250559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1327250559
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2207723951
Short name T39
Test name
Test status
Simulation time 3316491781 ps
CPU time 208.24 seconds
Started Jan 21 01:11:13 PM PST 24
Finished Jan 21 01:14:43 PM PST 24
Peak memory 202184 kb
Host smart-7cb215cb-3f74-4ce9-8876-1b54c6db42e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207723951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.2207723951
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2543016291
Short name T139
Test name
Test status
Simulation time 785426324 ps
CPU time 81.59 seconds
Started Jan 21 01:29:13 PM PST 24
Finished Jan 21 01:30:35 PM PST 24
Peak memory 321856 kb
Host smart-7f8b072f-cc22-4ac7-8c70-8a3176bde36b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543016291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2543016291
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3729991340
Short name T920
Test name
Test status
Simulation time 57251066448 ps
CPU time 1465.16 seconds
Started Jan 21 02:06:14 PM PST 24
Finished Jan 21 02:30:40 PM PST 24
Peak memory 375008 kb
Host smart-e6ad026e-7a4a-4a51-adc7-955d52958385
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729991340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.3729991340
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2734527575
Short name T471
Test name
Test status
Simulation time 52576089 ps
CPU time 0.7 seconds
Started Jan 21 12:49:00 PM PST 24
Finished Jan 21 12:49:01 PM PST 24
Peak memory 201992 kb
Host smart-0eaa7be4-4b1a-430b-b6cf-825b691e595b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734527575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2734527575
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.1647808152
Short name T489
Test name
Test status
Simulation time 121951754715 ps
CPU time 2221.56 seconds
Started Jan 21 12:48:51 PM PST 24
Finished Jan 21 01:25:54 PM PST 24
Peak memory 202232 kb
Host smart-9d134ce7-ee42-427f-8cba-d09cf448029e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647808152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.1647808152
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.1146422530
Short name T801
Test name
Test status
Simulation time 6550642808 ps
CPU time 23.33 seconds
Started Jan 21 12:48:48 PM PST 24
Finished Jan 21 12:49:13 PM PST 24
Peak memory 210320 kb
Host smart-5bda68c0-3a67-461e-8454-2be9fbe694e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146422530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es
calation.1146422530
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.815737989
Short name T864
Test name
Test status
Simulation time 2819536598 ps
CPU time 27.72 seconds
Started Jan 21 12:48:48 PM PST 24
Finished Jan 21 12:49:18 PM PST 24
Peak memory 218648 kb
Host smart-02cc36e8-e10d-46e0-9ef0-35fd6811fa97
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815737989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.sram_ctrl_max_throughput.815737989
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3521916733
Short name T595
Test name
Test status
Simulation time 9784683697 ps
CPU time 80.54 seconds
Started Jan 21 12:49:03 PM PST 24
Finished Jan 21 12:50:25 PM PST 24
Peak memory 211016 kb
Host smart-4bde3079-c025-4786-8421-d80a1a5f36fe
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521916733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3521916733
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.2135628251
Short name T535
Test name
Test status
Simulation time 6922511335 ps
CPU time 142.89 seconds
Started Jan 21 12:48:59 PM PST 24
Finished Jan 21 12:51:23 PM PST 24
Peak memory 202232 kb
Host smart-4bbd4ef5-a4ab-4c5d-9b50-be627700850a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135628251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.2135628251
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.1599192577
Short name T275
Test name
Test status
Simulation time 29058497821 ps
CPU time 482.1 seconds
Started Jan 21 12:48:53 PM PST 24
Finished Jan 21 12:56:56 PM PST 24
Peak memory 377432 kb
Host smart-d2cc817e-3e6b-467a-b07f-86392f85500d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599192577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.1599192577
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.2330429809
Short name T575
Test name
Test status
Simulation time 18356566779 ps
CPU time 18.23 seconds
Started Jan 21 12:48:49 PM PST 24
Finished Jan 21 12:49:09 PM PST 24
Peak memory 202168 kb
Host smart-b765c0fa-ecd3-4293-9d25-857c49517851
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330429809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.2330429809
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.516589803
Short name T351
Test name
Test status
Simulation time 127324774157 ps
CPU time 439.63 seconds
Started Jan 21 12:48:49 PM PST 24
Finished Jan 21 12:56:10 PM PST 24
Peak memory 202092 kb
Host smart-1552b2d1-16ff-4e69-a6e5-cc11ad14201f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516589803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_partial_access_b2b.516589803
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.3476540042
Short name T385
Test name
Test status
Simulation time 695742647 ps
CPU time 5.65 seconds
Started Jan 21 12:48:59 PM PST 24
Finished Jan 21 12:49:05 PM PST 24
Peak memory 202372 kb
Host smart-a8bff440-5b12-49d3-bdb6-a5bec4d6e253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476540042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3476540042
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.1911483933
Short name T331
Test name
Test status
Simulation time 22212631303 ps
CPU time 322.31 seconds
Started Jan 21 12:48:48 PM PST 24
Finished Jan 21 12:54:12 PM PST 24
Peak memory 377088 kb
Host smart-6c225e31-606c-4bb5-87f3-ea418b9f66c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911483933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1911483933
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.3266532079
Short name T817
Test name
Test status
Simulation time 707663687 ps
CPU time 35.81 seconds
Started Jan 21 12:48:51 PM PST 24
Finished Jan 21 12:49:28 PM PST 24
Peak memory 280756 kb
Host smart-1eebd19b-df87-4355-9298-f0e9b7da31be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266532079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3266532079
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.4023379562
Short name T818
Test name
Test status
Simulation time 112233972887 ps
CPU time 2872.23 seconds
Started Jan 21 12:49:00 PM PST 24
Finished Jan 21 01:36:54 PM PST 24
Peak memory 379012 kb
Host smart-d89c7b46-7f33-40ee-9245-b417a065225c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023379562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.4023379562
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1909095204
Short name T287
Test name
Test status
Simulation time 355629179 ps
CPU time 2924.41 seconds
Started Jan 21 12:48:58 PM PST 24
Finished Jan 21 01:37:44 PM PST 24
Peak memory 521448 kb
Host smart-bff88984-087f-44e0-910b-0de510fcd890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1909095204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1909095204
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2159166532
Short name T311
Test name
Test status
Simulation time 8874337996 ps
CPU time 312.03 seconds
Started Jan 21 12:48:49 PM PST 24
Finished Jan 21 12:54:02 PM PST 24
Peak memory 202276 kb
Host smart-2617db9c-b187-44f8-98d6-48cb810d0184
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159166532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.2159166532
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3884074638
Short name T562
Test name
Test status
Simulation time 781152543 ps
CPU time 126.98 seconds
Started Jan 21 12:48:46 PM PST 24
Finished Jan 21 12:50:55 PM PST 24
Peak memory 360452 kb
Host smart-843ed8d4-c560-4dda-aa81-f11b2e5c08eb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884074638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3884074638
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.784371948
Short name T415
Test name
Test status
Simulation time 37354080569 ps
CPU time 1476.83 seconds
Started Jan 21 12:49:25 PM PST 24
Finished Jan 21 01:14:02 PM PST 24
Peak memory 378504 kb
Host smart-5681bcb5-f602-483a-b1d5-30deb509ae5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784371948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 46.sram_ctrl_access_during_key_req.784371948
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.4245868950
Short name T913
Test name
Test status
Simulation time 15888614 ps
CPU time 0.62 seconds
Started Jan 21 12:49:33 PM PST 24
Finished Jan 21 12:49:35 PM PST 24
Peak memory 202044 kb
Host smart-6a05fd68-5e73-426a-a6ad-0dbe7e45863c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245868950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.4245868950
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.2688670619
Short name T867
Test name
Test status
Simulation time 566588630600 ps
CPU time 2581 seconds
Started Jan 21 12:49:16 PM PST 24
Finished Jan 21 01:32:18 PM PST 24
Peak memory 202072 kb
Host smart-5a07f90e-63f1-4c25-8e50-342be6786d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688670619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.2688670619
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.1596424782
Short name T797
Test name
Test status
Simulation time 699185107 ps
CPU time 26.97 seconds
Started Jan 21 12:49:14 PM PST 24
Finished Jan 21 12:49:42 PM PST 24
Peak memory 212004 kb
Host smart-020b7d1d-5165-4a82-bed4-43402ff6adb9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596424782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.1596424782
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3867167046
Short name T880
Test name
Test status
Simulation time 24476859326 ps
CPU time 152.42 seconds
Started Jan 21 12:49:30 PM PST 24
Finished Jan 21 12:52:03 PM PST 24
Peak memory 211388 kb
Host smart-0eb59f5d-1765-4380-be54-71b21788a7a0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867167046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.3867167046
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.576255723
Short name T295
Test name
Test status
Simulation time 8046585413 ps
CPU time 236.38 seconds
Started Jan 21 12:49:24 PM PST 24
Finished Jan 21 12:53:21 PM PST 24
Peak memory 202224 kb
Host smart-815e055d-84f7-4bde-9501-a09269e3d889
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576255723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_mem_walk.576255723
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.2951344111
Short name T190
Test name
Test status
Simulation time 10965238044 ps
CPU time 664.12 seconds
Started Jan 21 12:49:16 PM PST 24
Finished Jan 21 01:00:21 PM PST 24
Peak memory 364732 kb
Host smart-e1ea34a8-55b6-4741-80ba-1c37e215c1f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951344111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.2951344111
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.158198681
Short name T490
Test name
Test status
Simulation time 2818294517 ps
CPU time 12.73 seconds
Started Jan 21 01:19:44 PM PST 24
Finished Jan 21 01:19:59 PM PST 24
Peak memory 203252 kb
Host smart-7fc6dd7a-2f2c-4e55-a246-be3e139e5a6a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158198681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.s
ram_ctrl_partial_access.158198681
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4025430812
Short name T669
Test name
Test status
Simulation time 51202986828 ps
CPU time 290.9 seconds
Started Jan 21 01:04:58 PM PST 24
Finished Jan 21 01:09:55 PM PST 24
Peak memory 202140 kb
Host smart-4b01ede0-69c9-4410-9fc2-5ded4fba7ced
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025430812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.4025430812
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.1637353258
Short name T408
Test name
Test status
Simulation time 347742839 ps
CPU time 14.09 seconds
Started Jan 21 01:31:37 PM PST 24
Finished Jan 21 01:31:52 PM PST 24
Peak memory 202300 kb
Host smart-0a51e1e7-d6ed-4a7b-8c3b-d0668164c340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637353258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1637353258
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.1307498615
Short name T722
Test name
Test status
Simulation time 8488560584 ps
CPU time 1159.96 seconds
Started Jan 21 12:49:27 PM PST 24
Finished Jan 21 01:08:48 PM PST 24
Peak memory 378060 kb
Host smart-920fcd53-90ad-4e82-8800-d48973d9e44d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307498615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.1307498615
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.1532948435
Short name T509
Test name
Test status
Simulation time 1575817903 ps
CPU time 86.53 seconds
Started Jan 21 12:49:17 PM PST 24
Finished Jan 21 12:50:45 PM PST 24
Peak memory 334952 kb
Host smart-8b9fed4f-0584-4ae2-a949-da22ee65397d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532948435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1532948435
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.1371265606
Short name T223
Test name
Test status
Simulation time 236930917680 ps
CPU time 4881.59 seconds
Started Jan 21 02:22:38 PM PST 24
Finished Jan 21 03:44:00 PM PST 24
Peak memory 379368 kb
Host smart-01ff2425-2259-4881-a3ee-02217ffedb31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371265606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.sram_ctrl_stress_all.1371265606
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.341580918
Short name T522
Test name
Test status
Simulation time 1188873743 ps
CPU time 3944.13 seconds
Started Jan 21 12:49:31 PM PST 24
Finished Jan 21 01:55:16 PM PST 24
Peak memory 420280 kb
Host smart-4fbf3197-6b98-42ae-8fa0-17fec737e49a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=341580918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.341580918
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2307891626
Short name T783
Test name
Test status
Simulation time 3776174031 ps
CPU time 208.25 seconds
Started Jan 21 12:49:17 PM PST 24
Finished Jan 21 12:52:47 PM PST 24
Peak memory 202128 kb
Host smart-cdc8d523-c19c-4b58-b1f5-4a3b3e9004d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307891626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.2307891626
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.881335395
Short name T549
Test name
Test status
Simulation time 742762243 ps
CPU time 52.29 seconds
Started Jan 21 12:49:15 PM PST 24
Finished Jan 21 12:50:08 PM PST 24
Peak memory 285904 kb
Host smart-69e6939d-6ede-4da7-ba99-1b69a8df3a63
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881335395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_throughput_w_partial_write.881335395
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1306592079
Short name T292
Test name
Test status
Simulation time 4297009632 ps
CPU time 818.37 seconds
Started Jan 21 12:49:47 PM PST 24
Finished Jan 21 01:03:26 PM PST 24
Peak memory 374876 kb
Host smart-dcd6e998-3fe7-465e-bb31-5990a442510b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306592079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.1306592079
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.700059642
Short name T261
Test name
Test status
Simulation time 44006563 ps
CPU time 0.64 seconds
Started Jan 21 01:21:13 PM PST 24
Finished Jan 21 01:21:15 PM PST 24
Peak memory 201424 kb
Host smart-80fcd464-bc4b-4a4f-8392-350fb06888b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700059642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.700059642
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.2147486755
Short name T597
Test name
Test status
Simulation time 275935058104 ps
CPU time 2416.17 seconds
Started Jan 21 01:11:04 PM PST 24
Finished Jan 21 01:51:25 PM PST 24
Peak memory 202272 kb
Host smart-25ce9b55-b5a6-43e6-9abe-53ee4a60eb2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147486755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.2147486755
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.4131994546
Short name T5
Test name
Test status
Simulation time 30201071485 ps
CPU time 826.32 seconds
Started Jan 21 12:49:47 PM PST 24
Finished Jan 21 01:03:34 PM PST 24
Peak memory 374032 kb
Host smart-b6bc8f17-b979-4e7d-a8ac-35b82cbe50f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131994546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.4131994546
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.1651093237
Short name T664
Test name
Test status
Simulation time 15387224505 ps
CPU time 355.83 seconds
Started Jan 21 12:49:47 PM PST 24
Finished Jan 21 12:55:44 PM PST 24
Peak memory 210480 kb
Host smart-5d956714-ece3-4f3b-a512-82c126805248
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651093237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.1651093237
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.404664994
Short name T513
Test name
Test status
Simulation time 1511263802 ps
CPU time 124.48 seconds
Started Jan 21 01:04:14 PM PST 24
Finished Jan 21 01:06:20 PM PST 24
Peak memory 348616 kb
Host smart-87ad3f74-91b6-4b9c-8347-8dea3efaa7c7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404664994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sram_ctrl_max_throughput.404664994
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.709051291
Short name T895
Test name
Test status
Simulation time 44394920709 ps
CPU time 144.81 seconds
Started Jan 21 12:49:48 PM PST 24
Finished Jan 21 12:52:13 PM PST 24
Peak memory 218480 kb
Host smart-faa930bb-56f1-489c-b793-4ff4402779ce
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709051291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.sram_ctrl_mem_partial_access.709051291
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1990041595
Short name T750
Test name
Test status
Simulation time 1999571569 ps
CPU time 120.82 seconds
Started Jan 21 12:49:47 PM PST 24
Finished Jan 21 12:51:49 PM PST 24
Peak memory 202104 kb
Host smart-6ac18f76-5fbb-451b-abb5-7b426a2820ba
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990041595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1990041595
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.551346662
Short name T200
Test name
Test status
Simulation time 18249079037 ps
CPU time 1277.49 seconds
Started Jan 21 12:49:33 PM PST 24
Finished Jan 21 01:10:51 PM PST 24
Peak memory 378104 kb
Host smart-56b3292f-388c-4b64-af0d-fd4183f29907
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551346662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip
le_keys.551346662
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.3700648440
Short name T746
Test name
Test status
Simulation time 1636618967 ps
CPU time 10.69 seconds
Started Jan 21 12:49:40 PM PST 24
Finished Jan 21 12:49:52 PM PST 24
Peak memory 220636 kb
Host smart-e8299fc5-5461-404f-9b1c-60d6669f184f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700648440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.3700648440
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2462142296
Short name T869
Test name
Test status
Simulation time 32182915478 ps
CPU time 502.5 seconds
Started Jan 21 01:31:32 PM PST 24
Finished Jan 21 01:39:56 PM PST 24
Peak memory 202348 kb
Host smart-9019d991-e79a-4b45-8586-10415a6b81fb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462142296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2462142296
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.4167593133
Short name T948
Test name
Test status
Simulation time 369695543 ps
CPU time 13.78 seconds
Started Jan 21 12:49:47 PM PST 24
Finished Jan 21 12:50:02 PM PST 24
Peak memory 202276 kb
Host smart-7b7156f9-524f-4476-b256-90c24a3cc7fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167593133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.4167593133
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.1710746824
Short name T435
Test name
Test status
Simulation time 21878139218 ps
CPU time 984.32 seconds
Started Jan 21 12:49:47 PM PST 24
Finished Jan 21 01:06:12 PM PST 24
Peak memory 379128 kb
Host smart-8425859b-f10a-4313-9429-651640ff596b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710746824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1710746824
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.1118840187
Short name T519
Test name
Test status
Simulation time 3487043730 ps
CPU time 17.81 seconds
Started Jan 21 01:45:26 PM PST 24
Finished Jan 21 01:45:45 PM PST 24
Peak memory 202216 kb
Host smart-a352570f-a031-4c03-9986-ac1e339022b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118840187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1118840187
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.973616959
Short name T25
Test name
Test status
Simulation time 997650418337 ps
CPU time 3076.36 seconds
Started Jan 21 12:49:59 PM PST 24
Finished Jan 21 01:41:18 PM PST 24
Peak memory 210324 kb
Host smart-d16b3b76-e8cb-4f25-8cf6-bfe127f73d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973616959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_stress_all.973616959
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1131825530
Short name T803
Test name
Test status
Simulation time 1444502523 ps
CPU time 6354.6 seconds
Started Jan 21 12:49:47 PM PST 24
Finished Jan 21 02:35:43 PM PST 24
Peak memory 619436 kb
Host smart-7a2d4a55-a452-4067-a4a1-69f4d3ef9896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1131825530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1131825530
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3644487318
Short name T225
Test name
Test status
Simulation time 20864808789 ps
CPU time 319.18 seconds
Started Jan 21 01:41:22 PM PST 24
Finished Jan 21 01:46:42 PM PST 24
Peak memory 202336 kb
Host smart-b86df3b0-ab0e-44b9-9dc8-d8839a9d396b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644487318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.3644487318
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3341047772
Short name T379
Test name
Test status
Simulation time 2692069113 ps
CPU time 26.19 seconds
Started Jan 21 12:49:39 PM PST 24
Finished Jan 21 12:50:06 PM PST 24
Peak memory 210496 kb
Host smart-1b43eca9-c9b7-40aa-b699-de2ae01f36cb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341047772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3341047772
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2055332939
Short name T762
Test name
Test status
Simulation time 28506290239 ps
CPU time 674 seconds
Started Jan 21 01:10:16 PM PST 24
Finished Jan 21 01:21:31 PM PST 24
Peak memory 332028 kb
Host smart-a06be02b-f6aa-4d48-97a5-ba4600ff9d4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055332939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.2055332939
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.2616320171
Short name T208
Test name
Test status
Simulation time 14246090 ps
CPU time 0.63 seconds
Started Jan 21 02:06:36 PM PST 24
Finished Jan 21 02:06:37 PM PST 24
Peak memory 202176 kb
Host smart-442503f5-c2d2-474b-9f89-fe2fdf6ab848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616320171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.2616320171
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.2188265965
Short name T786
Test name
Test status
Simulation time 719553523516 ps
CPU time 2712.34 seconds
Started Jan 21 12:49:57 PM PST 24
Finished Jan 21 01:35:10 PM PST 24
Peak memory 202196 kb
Host smart-d650105b-6cfe-424a-bfa7-cc34130bdbb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188265965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.2188265965
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.2798771673
Short name T267
Test name
Test status
Simulation time 57796002144 ps
CPU time 132.65 seconds
Started Jan 21 12:50:04 PM PST 24
Finished Jan 21 12:52:17 PM PST 24
Peak memory 210316 kb
Host smart-b7453516-12c6-4aa3-843e-9e9acd45e4f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798771673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.2798771673
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2065220664
Short name T484
Test name
Test status
Simulation time 2889204798 ps
CPU time 64.08 seconds
Started Jan 21 12:49:56 PM PST 24
Finished Jan 21 12:51:01 PM PST 24
Peak memory 300424 kb
Host smart-9ee19020-0c3c-461a-8cb5-6b606d1c1a74
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065220664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2065220664
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1558811864
Short name T784
Test name
Test status
Simulation time 1971173128 ps
CPU time 70.86 seconds
Started Jan 21 12:50:06 PM PST 24
Finished Jan 21 12:51:18 PM PST 24
Peak memory 210940 kb
Host smart-451aabff-e48f-4b32-a95d-1553d1831b9a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558811864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.1558811864
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.105301120
Short name T959
Test name
Test status
Simulation time 26496527120 ps
CPU time 159.46 seconds
Started Jan 21 01:23:57 PM PST 24
Finished Jan 21 01:26:37 PM PST 24
Peak memory 202332 kb
Host smart-664c40f7-dc76-4e7d-8e99-4c6f362ca6be
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105301120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl
_mem_walk.105301120
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.944749479
Short name T206
Test name
Test status
Simulation time 15324386753 ps
CPU time 980.3 seconds
Started Jan 21 12:49:55 PM PST 24
Finished Jan 21 01:06:17 PM PST 24
Peak memory 377056 kb
Host smart-0a86fb2d-cc2e-4c5a-b9bb-6a24c4e6a15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944749479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip
le_keys.944749479
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.448368397
Short name T658
Test name
Test status
Simulation time 1470664809 ps
CPU time 26.08 seconds
Started Jan 21 12:49:57 PM PST 24
Finished Jan 21 12:50:24 PM PST 24
Peak memory 201904 kb
Host smart-bc162f62-3c80-4a8d-8b3a-bea949f9df26
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448368397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s
ram_ctrl_partial_access.448368397
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4213894604
Short name T779
Test name
Test status
Simulation time 34958917127 ps
CPU time 376.73 seconds
Started Jan 21 12:49:57 PM PST 24
Finished Jan 21 12:56:15 PM PST 24
Peak memory 201960 kb
Host smart-e5d7e54b-8f9b-420d-9c1a-f7aa2c40dd5a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213894604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.4213894604
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2129211948
Short name T477
Test name
Test status
Simulation time 349632411 ps
CPU time 5.43 seconds
Started Jan 21 01:21:16 PM PST 24
Finished Jan 21 01:21:22 PM PST 24
Peak memory 202436 kb
Host smart-7bdc571c-4a47-4a7c-bac5-bcda77b6ee36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129211948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2129211948
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.3597411328
Short name T356
Test name
Test status
Simulation time 25433532015 ps
CPU time 195.52 seconds
Started Jan 21 12:50:04 PM PST 24
Finished Jan 21 12:53:20 PM PST 24
Peak memory 344764 kb
Host smart-2669222e-1645-4010-bdfd-6deb04aa8dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597411328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3597411328
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.1274834034
Short name T461
Test name
Test status
Simulation time 531289421 ps
CPU time 14.28 seconds
Started Jan 21 01:11:50 PM PST 24
Finished Jan 21 01:12:06 PM PST 24
Peak memory 240284 kb
Host smart-ce210f2d-d55a-44ad-aee5-f088b7c65d54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274834034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1274834034
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3458846012
Short name T391
Test name
Test status
Simulation time 2104407340 ps
CPU time 6165.05 seconds
Started Jan 21 12:50:11 PM PST 24
Finished Jan 21 02:32:57 PM PST 24
Peak memory 435976 kb
Host smart-e1c76e73-7682-4473-88ff-e38032a56c90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3458846012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3458846012
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2193961938
Short name T507
Test name
Test status
Simulation time 18865365977 ps
CPU time 356.9 seconds
Started Jan 21 12:49:57 PM PST 24
Finished Jan 21 12:55:54 PM PST 24
Peak memory 202236 kb
Host smart-3a387bdb-6e59-496c-b8b7-7f22a8f2a828
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193961938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.2193961938
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3204251436
Short name T393
Test name
Test status
Simulation time 5314427646 ps
CPU time 35.36 seconds
Started Jan 21 12:49:58 PM PST 24
Finished Jan 21 12:50:34 PM PST 24
Peak memory 234944 kb
Host smart-515ecea9-e1ec-4401-92c2-2e3461fe3b77
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204251436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3204251436
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2124686929
Short name T849
Test name
Test status
Simulation time 51947003266 ps
CPU time 1699.48 seconds
Started Jan 21 12:50:27 PM PST 24
Finished Jan 21 01:18:48 PM PST 24
Peak memory 375920 kb
Host smart-317cc0fb-d5b7-4e2f-accc-9a97a641c5f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124686929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.2124686929
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.4086300400
Short name T732
Test name
Test status
Simulation time 40713131 ps
CPU time 0.66 seconds
Started Jan 21 12:50:35 PM PST 24
Finished Jan 21 12:50:37 PM PST 24
Peak memory 202020 kb
Host smart-f56b1ef8-516e-4993-a70c-42cfe9149e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086300400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.4086300400
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.390910643
Short name T346
Test name
Test status
Simulation time 34166972695 ps
CPU time 563.78 seconds
Started Jan 21 12:50:20 PM PST 24
Finished Jan 21 12:59:45 PM PST 24
Peak memory 202212 kb
Host smart-c34deebf-d7b8-4012-b066-680fe6c08eca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390910643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.
390910643
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.3387979246
Short name T827
Test name
Test status
Simulation time 16928514883 ps
CPU time 951.16 seconds
Started Jan 21 12:50:35 PM PST 24
Finished Jan 21 01:06:27 PM PST 24
Peak memory 370864 kb
Host smart-22efe2ef-7c36-4072-8e66-1272b450d1d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387979246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.3387979246
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.3838684342
Short name T7
Test name
Test status
Simulation time 32468476585 ps
CPU time 77.66 seconds
Started Jan 21 12:50:35 PM PST 24
Finished Jan 21 12:51:53 PM PST 24
Peak memory 210504 kb
Host smart-5169d2d8-f2aa-4df7-afa2-032ef73a1a69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838684342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.3838684342
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.3565748609
Short name T600
Test name
Test status
Simulation time 1504747090 ps
CPU time 59.95 seconds
Started Jan 21 12:50:27 PM PST 24
Finished Jan 21 12:51:28 PM PST 24
Peak memory 297304 kb
Host smart-accdc73a-3ba2-42e8-a1c9-14b99ed77683
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565748609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.3565748609
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4163412281
Short name T541
Test name
Test status
Simulation time 10154949024 ps
CPU time 151.25 seconds
Started Jan 21 01:19:19 PM PST 24
Finished Jan 21 01:21:58 PM PST 24
Peak memory 213924 kb
Host smart-573ff815-e039-41e4-ba21-6cf373fdfd71
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163412281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.4163412281
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.3295399180
Short name T791
Test name
Test status
Simulation time 2059650240 ps
CPU time 119.67 seconds
Started Jan 21 01:50:53 PM PST 24
Finished Jan 21 01:52:55 PM PST 24
Peak memory 202188 kb
Host smart-7ceaf3d5-5182-4a8e-af36-76a2d31d467e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295399180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.3295399180
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.3682994067
Short name T224
Test name
Test status
Simulation time 50977648279 ps
CPU time 1250.75 seconds
Started Jan 21 01:44:21 PM PST 24
Finished Jan 21 02:05:16 PM PST 24
Peak memory 372356 kb
Host smart-0eebbbf8-8057-4a38-b9f3-5259ce40fd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682994067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.3682994067
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.3910988592
Short name T472
Test name
Test status
Simulation time 1171819212 ps
CPU time 15 seconds
Started Jan 21 12:50:20 PM PST 24
Finished Jan 21 12:50:36 PM PST 24
Peak memory 202164 kb
Host smart-1c0116ed-1f67-472b-b7d7-3c2312b411ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910988592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.3910988592
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.791062288
Short name T17
Test name
Test status
Simulation time 38922628772 ps
CPU time 560.96 seconds
Started Jan 21 12:50:19 PM PST 24
Finished Jan 21 12:59:40 PM PST 24
Peak memory 202120 kb
Host smart-6d163863-7947-44d4-a02a-416d661cbb92
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791062288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.sram_ctrl_partial_access_b2b.791062288
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.1333187040
Short name T375
Test name
Test status
Simulation time 1356169431 ps
CPU time 13.39 seconds
Started Jan 21 01:05:41 PM PST 24
Finished Jan 21 01:05:56 PM PST 24
Peak memory 202304 kb
Host smart-18ad983a-8a2f-4d2d-8aca-0287c64f1191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333187040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1333187040
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.176220343
Short name T804
Test name
Test status
Simulation time 17702073741 ps
CPU time 1434.11 seconds
Started Jan 21 12:50:30 PM PST 24
Finished Jan 21 01:14:25 PM PST 24
Peak memory 377016 kb
Host smart-a71c4a51-ef0b-4ea4-bd55-d9fced01377f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176220343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.176220343
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.567897354
Short name T1
Test name
Test status
Simulation time 3323923316 ps
CPU time 36.62 seconds
Started Jan 21 12:50:21 PM PST 24
Finished Jan 21 12:50:58 PM PST 24
Peak memory 247328 kb
Host smart-b7ece453-f5ca-4fd6-ba07-a50710b99441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567897354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.567897354
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3737687333
Short name T742
Test name
Test status
Simulation time 3240550939 ps
CPU time 2099.37 seconds
Started Jan 21 12:50:36 PM PST 24
Finished Jan 21 01:25:36 PM PST 24
Peak memory 623164 kb
Host smart-373d5531-aa2f-46e7-941b-078d717e9718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3737687333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3737687333
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.223225599
Short name T690
Test name
Test status
Simulation time 7283716316 ps
CPU time 271.31 seconds
Started Jan 21 01:32:14 PM PST 24
Finished Jan 21 01:36:46 PM PST 24
Peak memory 202168 kb
Host smart-8d441ef0-242a-4104-90b6-c2ea81665645
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223225599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.223225599
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1250377328
Short name T735
Test name
Test status
Simulation time 2862816017 ps
CPU time 30.5 seconds
Started Jan 21 12:50:35 PM PST 24
Finished Jan 21 12:51:07 PM PST 24
Peak memory 234836 kb
Host smart-6433a594-3888-44fc-806b-c5c1253a4fe0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250377328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1250377328
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2372953002
Short name T700
Test name
Test status
Simulation time 23811007220 ps
CPU time 746.18 seconds
Started Jan 21 12:32:19 PM PST 24
Finished Jan 21 12:44:55 PM PST 24
Peak memory 358632 kb
Host smart-98fb8f16-3b91-4d94-957c-ea37695f7feb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372953002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.2372953002
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.3049986707
Short name T201
Test name
Test status
Simulation time 14839194 ps
CPU time 0.65 seconds
Started Jan 21 12:32:25 PM PST 24
Finished Jan 21 12:32:30 PM PST 24
Peak memory 202124 kb
Host smart-5df33e0a-bda5-4fdc-a008-945f970708dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049986707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.3049986707
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.247836782
Short name T942
Test name
Test status
Simulation time 620581078148 ps
CPU time 2126.73 seconds
Started Jan 21 12:32:22 PM PST 24
Finished Jan 21 01:07:56 PM PST 24
Peak memory 202132 kb
Host smart-a70bf36f-f951-4a1a-b4ff-2fd5eea8ba2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247836782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.247836782
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.3467463693
Short name T714
Test name
Test status
Simulation time 23932780711 ps
CPU time 105.51 seconds
Started Jan 21 12:32:18 PM PST 24
Finished Jan 21 12:34:14 PM PST 24
Peak memory 210300 kb
Host smart-1c4d7be9-ba55-491c-a1ef-2e694bddf0b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467463693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.3467463693
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.731091439
Short name T452
Test name
Test status
Simulation time 798604349 ps
CPU time 149.53 seconds
Started Jan 21 12:32:24 PM PST 24
Finished Jan 21 12:34:59 PM PST 24
Peak memory 356588 kb
Host smart-d8d10565-a968-45cf-8b78-8ecf9e04eda3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731091439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.sram_ctrl_max_throughput.731091439
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2268572161
Short name T871
Test name
Test status
Simulation time 39474430945 ps
CPU time 155.75 seconds
Started Jan 21 12:32:26 PM PST 24
Finished Jan 21 12:35:06 PM PST 24
Peak memory 218436 kb
Host smart-2dc78f26-6b6f-435a-ac24-be1609707a5a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268572161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2268572161
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.2085836082
Short name T584
Test name
Test status
Simulation time 7188521541 ps
CPU time 131.29 seconds
Started Jan 21 12:32:18 PM PST 24
Finished Jan 21 12:34:40 PM PST 24
Peak memory 202244 kb
Host smart-89939beb-6e20-4a13-b156-01f2a7ec06f8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085836082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.2085836082
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1181308675
Short name T65
Test name
Test status
Simulation time 22495480118 ps
CPU time 781.17 seconds
Started Jan 21 12:32:09 PM PST 24
Finished Jan 21 12:45:26 PM PST 24
Peak memory 369008 kb
Host smart-9186a4d7-5fba-4239-aba2-6e08a466f21f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181308675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1181308675
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.2244580980
Short name T810
Test name
Test status
Simulation time 1009832372 ps
CPU time 76.53 seconds
Started Jan 21 12:32:22 PM PST 24
Finished Jan 21 12:33:46 PM PST 24
Peak memory 326808 kb
Host smart-a2038a29-f222-43bb-b387-c64acb351560
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244580980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.2244580980
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3224466496
Short name T555
Test name
Test status
Simulation time 6533506030 ps
CPU time 407.01 seconds
Started Jan 21 12:32:27 PM PST 24
Finished Jan 21 12:39:17 PM PST 24
Peak memory 202152 kb
Host smart-de8d8e57-8e06-4899-a19c-b1034ea040c0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224466496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.3224466496
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.2123067755
Short name T451
Test name
Test status
Simulation time 3751448309 ps
CPU time 7.19 seconds
Started Jan 21 12:32:20 PM PST 24
Finished Jan 21 12:32:36 PM PST 24
Peak memory 202416 kb
Host smart-4eea1f3f-8786-4c8d-8836-c5e0c6845253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123067755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2123067755
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.680810500
Short name T825
Test name
Test status
Simulation time 10104925309 ps
CPU time 192.82 seconds
Started Jan 21 12:32:14 PM PST 24
Finished Jan 21 12:35:39 PM PST 24
Peak memory 374936 kb
Host smart-98523923-b46e-489b-96e3-cee7f69c64b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680810500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.680810500
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.383087169
Short name T774
Test name
Test status
Simulation time 1032077946 ps
CPU time 35.23 seconds
Started Jan 21 12:32:17 PM PST 24
Finished Jan 21 12:33:03 PM PST 24
Peak memory 286912 kb
Host smart-e60cd213-ab5f-4904-8ed5-9565d54b857f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383087169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.383087169
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.1332319465
Short name T596
Test name
Test status
Simulation time 666725973733 ps
CPU time 3928.89 seconds
Started Jan 21 12:32:23 PM PST 24
Finished Jan 21 01:37:59 PM PST 24
Peak memory 385204 kb
Host smart-f53b8b4d-314b-4e5f-9322-0dfee786bfab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332319465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.1332319465
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2893789733
Short name T623
Test name
Test status
Simulation time 1788080259 ps
CPU time 4690.29 seconds
Started Jan 21 12:32:35 PM PST 24
Finished Jan 21 01:50:46 PM PST 24
Peak memory 632744 kb
Host smart-045c7655-ea04-4a7f-857a-59be74f5ba62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2893789733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2893789733
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1989484628
Short name T525
Test name
Test status
Simulation time 5637619243 ps
CPU time 379.93 seconds
Started Jan 21 12:32:24 PM PST 24
Finished Jan 21 12:38:49 PM PST 24
Peak memory 202264 kb
Host smart-a8137919-d7f8-47ef-93cb-6ebd9481ffb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989484628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.1989484628
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2506579362
Short name T579
Test name
Test status
Simulation time 2894904432 ps
CPU time 163.39 seconds
Started Jan 21 12:32:19 PM PST 24
Finished Jan 21 12:35:12 PM PST 24
Peak memory 364624 kb
Host smart-2ff4f1fa-868a-4117-ac91-326093658a44
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506579362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2506579362
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1788178515
Short name T641
Test name
Test status
Simulation time 2979208605 ps
CPU time 806.29 seconds
Started Jan 21 12:32:32 PM PST 24
Finished Jan 21 12:45:59 PM PST 24
Peak memory 375948 kb
Host smart-6a8d5569-5ddc-4a67-bd0b-76574c3d463f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788178515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.1788178515
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.1264741946
Short name T651
Test name
Test status
Simulation time 52441089 ps
CPU time 0.64 seconds
Started Jan 21 12:32:39 PM PST 24
Finished Jan 21 12:32:40 PM PST 24
Peak memory 202096 kb
Host smart-52fd88e0-9674-4f67-9cdb-9f89483b1766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264741946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.1264741946
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.1637066809
Short name T802
Test name
Test status
Simulation time 28711429141 ps
CPU time 458.95 seconds
Started Jan 21 12:32:30 PM PST 24
Finished Jan 21 12:40:10 PM PST 24
Peak memory 202104 kb
Host smart-e43e0e88-d8a9-455a-92bd-f6c964eb070e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637066809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
1637066809
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.4201693827
Short name T858
Test name
Test status
Simulation time 67844308759 ps
CPU time 1382.59 seconds
Started Jan 21 12:32:32 PM PST 24
Finished Jan 21 12:55:35 PM PST 24
Peak memory 378360 kb
Host smart-1dd7bb2f-da36-4561-9677-74190ad3fa44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201693827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.4201693827
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.1665173589
Short name T389
Test name
Test status
Simulation time 754578015 ps
CPU time 77.69 seconds
Started Jan 21 12:32:35 PM PST 24
Finished Jan 21 12:33:53 PM PST 24
Peak memory 311712 kb
Host smart-0951aaca-55ab-4907-88fd-a0036081a1eb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665173589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.1665173589
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1667763567
Short name T263
Test name
Test status
Simulation time 7283107873 ps
CPU time 71.03 seconds
Started Jan 21 12:32:40 PM PST 24
Finished Jan 21 12:33:52 PM PST 24
Peak memory 211496 kb
Host smart-118dfebe-332e-4c57-bb91-a8c2c6ade6a3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667763567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.1667763567
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3904334690
Short name T661
Test name
Test status
Simulation time 28653954987 ps
CPU time 143.59 seconds
Started Jan 21 12:32:42 PM PST 24
Finished Jan 21 12:35:07 PM PST 24
Peak memory 202412 kb
Host smart-c33607b6-dc1d-4bc5-b65e-0d59062b370a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904334690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3904334690
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.98004792
Short name T246
Test name
Test status
Simulation time 69410963864 ps
CPU time 1404.88 seconds
Started Jan 21 12:32:25 PM PST 24
Finished Jan 21 12:55:55 PM PST 24
Peak memory 380184 kb
Host smart-c8d6a3c8-e8b0-4613-86d8-9ab9d211845d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98004792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple
_keys.98004792
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.975036058
Short name T302
Test name
Test status
Simulation time 5298219198 ps
CPU time 130.94 seconds
Started Jan 21 12:32:35 PM PST 24
Finished Jan 21 12:34:46 PM PST 24
Peak memory 357596 kb
Host smart-4ad38afb-0f97-4e2a-9d4e-7a4a73776967
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975036058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sr
am_ctrl_partial_access.975036058
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1028683439
Short name T470
Test name
Test status
Simulation time 5319050545 ps
CPU time 314.07 seconds
Started Jan 21 12:32:35 PM PST 24
Finished Jan 21 12:37:49 PM PST 24
Peak memory 201712 kb
Host smart-dc9c3019-6e67-4a7f-97cd-d460cab10361
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028683439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.1028683439
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.4011038592
Short name T32
Test name
Test status
Simulation time 362895747 ps
CPU time 13.54 seconds
Started Jan 21 12:32:37 PM PST 24
Finished Jan 21 12:32:52 PM PST 24
Peak memory 202220 kb
Host smart-6054c116-d0d9-4da7-99dd-54c86b5fa073
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011038592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.4011038592
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3048947036
Short name T309
Test name
Test status
Simulation time 7636499630 ps
CPU time 567.93 seconds
Started Jan 21 12:32:40 PM PST 24
Finished Jan 21 12:42:09 PM PST 24
Peak memory 370288 kb
Host smart-d8632878-f32b-4e7b-9a5e-05ca7773e422
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048947036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3048947036
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.2456016813
Short name T143
Test name
Test status
Simulation time 781725468 ps
CPU time 14.76 seconds
Started Jan 21 12:32:23 PM PST 24
Finished Jan 21 12:32:44 PM PST 24
Peak memory 202016 kb
Host smart-4aed5e7b-b376-4eb3-bc9e-70297cb0e524
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456016813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2456016813
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3206671435
Short name T751
Test name
Test status
Simulation time 2162673274 ps
CPU time 2015.3 seconds
Started Jan 21 12:32:41 PM PST 24
Finished Jan 21 01:06:18 PM PST 24
Peak memory 558036 kb
Host smart-ae93a8c0-a385-426b-8eb3-1ccaf992bb7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3206671435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3206671435
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3220632549
Short name T304
Test name
Test status
Simulation time 22381249893 ps
CPU time 389.38 seconds
Started Jan 21 12:32:35 PM PST 24
Finished Jan 21 12:39:05 PM PST 24
Peak memory 202172 kb
Host smart-6aa47f2b-74e6-432d-af56-86ad5d52b726
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220632549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.3220632549
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2876159987
Short name T587
Test name
Test status
Simulation time 4031813412 ps
CPU time 30.36 seconds
Started Jan 21 12:32:30 PM PST 24
Finished Jan 21 12:33:02 PM PST 24
Peak memory 226772 kb
Host smart-80dded44-9ad8-4946-8071-dd118d3bd807
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876159987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.2876159987
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3745287074
Short name T2
Test name
Test status
Simulation time 8935195413 ps
CPU time 394.55 seconds
Started Jan 21 12:33:03 PM PST 24
Finished Jan 21 12:39:39 PM PST 24
Peak memory 326916 kb
Host smart-ede2bd3a-1471-422a-83d8-2a439c6e4598
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745287074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3745287074
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.3806204058
Short name T593
Test name
Test status
Simulation time 38740012 ps
CPU time 0.65 seconds
Started Jan 21 12:33:09 PM PST 24
Finished Jan 21 12:33:10 PM PST 24
Peak memory 201656 kb
Host smart-05840631-63c4-44bd-9778-e641ea22975e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806204058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.3806204058
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.4206356089
Short name T459
Test name
Test status
Simulation time 59539911369 ps
CPU time 948.91 seconds
Started Jan 21 12:32:58 PM PST 24
Finished Jan 21 12:48:48 PM PST 24
Peak memory 202180 kb
Host smart-144773f8-e381-4a5b-9b95-3d7fec645bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206356089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
4206356089
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.2315406292
Short name T777
Test name
Test status
Simulation time 29043988079 ps
CPU time 143.6 seconds
Started Jan 21 12:32:54 PM PST 24
Finished Jan 21 12:35:20 PM PST 24
Peak memory 213804 kb
Host smart-25b5feb0-e54e-4207-9158-d3833ffe0ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315406292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.2315406292
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.2557009038
Short name T964
Test name
Test status
Simulation time 802302179 ps
CPU time 34.53 seconds
Started Jan 21 12:32:56 PM PST 24
Finished Jan 21 12:33:32 PM PST 24
Peak memory 252992 kb
Host smart-16c701c7-055e-4ff2-a0ea-35835674acbb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557009038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.2557009038
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.57637764
Short name T84
Test name
Test status
Simulation time 1013739118 ps
CPU time 67.82 seconds
Started Jan 21 12:33:09 PM PST 24
Finished Jan 21 12:34:18 PM PST 24
Peak memory 218460 kb
Host smart-d724e524-a25c-450f-9650-48519218b30d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57637764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_mem_partial_access.57637764
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.616516270
Short name T852
Test name
Test status
Simulation time 6903443426 ps
CPU time 138.53 seconds
Started Jan 21 12:33:08 PM PST 24
Finished Jan 21 12:35:28 PM PST 24
Peak memory 202268 kb
Host smart-c0e9372b-8a55-4298-88f7-772bb3b5275b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616516270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_
mem_walk.616516270
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.2571084780
Short name T900
Test name
Test status
Simulation time 39122394014 ps
CPU time 944.98 seconds
Started Jan 21 12:52:55 PM PST 24
Finished Jan 21 01:08:41 PM PST 24
Peak memory 376036 kb
Host smart-a049d10a-a1a5-45ec-9a69-837308aac184
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571084780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.2571084780
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1036281338
Short name T232
Test name
Test status
Simulation time 538674732 ps
CPU time 24.3 seconds
Started Jan 21 12:32:54 PM PST 24
Finished Jan 21 12:33:20 PM PST 24
Peak memory 202088 kb
Host smart-a8aa064c-c61e-4b92-9485-2989118d18cc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036281338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1036281338
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.246768146
Short name T207
Test name
Test status
Simulation time 63505970704 ps
CPU time 390.4 seconds
Started Jan 21 12:32:56 PM PST 24
Finished Jan 21 12:39:27 PM PST 24
Peak memory 202060 kb
Host smart-4507fdc2-c7a2-47b9-bea7-231ded03ea86
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246768146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.sram_ctrl_partial_access_b2b.246768146
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3355568521
Short name T285
Test name
Test status
Simulation time 3341947547 ps
CPU time 13.87 seconds
Started Jan 21 12:33:07 PM PST 24
Finished Jan 21 12:33:22 PM PST 24
Peak memory 202348 kb
Host smart-8e8550d9-148e-4be8-8a5e-75b2e319d9f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355568521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3355568521
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.3983563413
Short name T805
Test name
Test status
Simulation time 18891255179 ps
CPU time 996.96 seconds
Started Jan 21 12:33:00 PM PST 24
Finished Jan 21 12:49:38 PM PST 24
Peak memory 377024 kb
Host smart-1373491c-e0c6-46eb-9b1c-b57911f53915
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983563413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3983563413
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.85321082
Short name T476
Test name
Test status
Simulation time 5024763553 ps
CPU time 22.07 seconds
Started Jan 21 12:32:45 PM PST 24
Finished Jan 21 12:33:13 PM PST 24
Peak memory 202116 kb
Host smart-59846361-ca47-4798-9c20-aa9a9fd6d575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85321082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.85321082
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.2208636640
Short name T373
Test name
Test status
Simulation time 96331369334 ps
CPU time 7219.29 seconds
Started Jan 21 12:33:07 PM PST 24
Finished Jan 21 02:33:28 PM PST 24
Peak memory 379048 kb
Host smart-ae77e091-7e86-4beb-ac1b-c8075c77454c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208636640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.2208636640
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3833437367
Short name T222
Test name
Test status
Simulation time 1156541213 ps
CPU time 1375.27 seconds
Started Jan 21 12:33:08 PM PST 24
Finished Jan 21 12:56:04 PM PST 24
Peak memory 389792 kb
Host smart-0f53afdf-5f2e-45f2-a462-646d9bce145a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3833437367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3833437367
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3595797348
Short name T598
Test name
Test status
Simulation time 8959474094 ps
CPU time 187.17 seconds
Started Jan 21 12:32:53 PM PST 24
Finished Jan 21 12:36:03 PM PST 24
Peak memory 202140 kb
Host smart-c6efcd18-a9f1-4e71-b14b-7e299fe0d9c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595797348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.3595797348
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2772763009
Short name T712
Test name
Test status
Simulation time 2690675298 ps
CPU time 29.46 seconds
Started Jan 21 12:32:59 PM PST 24
Finished Jan 21 12:33:29 PM PST 24
Peak memory 214908 kb
Host smart-2235d983-b21e-49dc-b280-b6a6a0febd59
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772763009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.2772763009
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1658768869
Short name T380
Test name
Test status
Simulation time 101267561167 ps
CPU time 2377.52 seconds
Started Jan 21 12:33:15 PM PST 24
Finished Jan 21 01:12:53 PM PST 24
Peak memory 378020 kb
Host smart-76642bae-02fc-43a7-a4a3-c7b59312f67d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658768869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.1658768869
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.3467428505
Short name T868
Test name
Test status
Simulation time 25321579 ps
CPU time 0.63 seconds
Started Jan 21 12:33:15 PM PST 24
Finished Jan 21 12:33:16 PM PST 24
Peak memory 201400 kb
Host smart-eabeb97d-25f2-48e9-a5ca-6711158dca5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467428505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.3467428505
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.3927842348
Short name T958
Test name
Test status
Simulation time 52588430791 ps
CPU time 1772.58 seconds
Started Jan 21 12:33:09 PM PST 24
Finished Jan 21 01:02:43 PM PST 24
Peak memory 202184 kb
Host smart-bf572c4d-09ff-408f-94a4-6c38fe5cada7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927842348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
3927842348
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.1545698592
Short name T454
Test name
Test status
Simulation time 8990109052 ps
CPU time 81.96 seconds
Started Jan 21 12:33:11 PM PST 24
Finished Jan 21 12:34:34 PM PST 24
Peak memory 210400 kb
Host smart-dd4a30b7-5fe1-4d5f-8f40-965d159d9756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545698592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.1545698592
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2331085205
Short name T335
Test name
Test status
Simulation time 3518203320 ps
CPU time 192.3 seconds
Started Jan 21 12:33:09 PM PST 24
Finished Jan 21 12:36:22 PM PST 24
Peak memory 372976 kb
Host smart-2f7e75e8-50f7-42bd-b836-95c3d300a8e6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331085205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2331085205
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.928117266
Short name T510
Test name
Test status
Simulation time 4941010837 ps
CPU time 144.83 seconds
Started Jan 21 12:33:17 PM PST 24
Finished Jan 21 12:35:43 PM PST 24
Peak memory 214720 kb
Host smart-f749fdd9-473a-48aa-b452-b7019294511e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928117266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_mem_partial_access.928117266
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.717006171
Short name T697
Test name
Test status
Simulation time 18235726162 ps
CPU time 142.8 seconds
Started Jan 21 12:33:16 PM PST 24
Finished Jan 21 12:35:40 PM PST 24
Peak memory 202140 kb
Host smart-4a7becdc-87d7-45a9-830c-02ac56507ea6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717006171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
mem_walk.717006171
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.3877924006
Short name T834
Test name
Test status
Simulation time 16848266635 ps
CPU time 1165.43 seconds
Started Jan 21 12:33:10 PM PST 24
Finished Jan 21 12:52:36 PM PST 24
Peak memory 379100 kb
Host smart-00dd6df6-8862-4985-a7a2-d47809915e09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877924006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.3877924006
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.1432010288
Short name T534
Test name
Test status
Simulation time 5592260648 ps
CPU time 15.5 seconds
Started Jan 21 12:33:09 PM PST 24
Finished Jan 21 12:33:25 PM PST 24
Peak memory 202136 kb
Host smart-6e3e6df2-153e-44a2-9847-5db1639d7083
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432010288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.1432010288
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4184181035
Short name T247
Test name
Test status
Simulation time 4356844987 ps
CPU time 281.95 seconds
Started Jan 21 12:33:10 PM PST 24
Finished Jan 21 12:37:53 PM PST 24
Peak memory 202056 kb
Host smart-a91aa28e-f824-41a4-aa30-910b6bb5dc13
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184181035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.4184181035
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.2079030451
Short name T283
Test name
Test status
Simulation time 676559104 ps
CPU time 5.4 seconds
Started Jan 21 12:33:20 PM PST 24
Finished Jan 21 12:33:26 PM PST 24
Peak memory 202240 kb
Host smart-3c0c2b48-9bf5-4a2e-947f-449ccacebbd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079030451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2079030451
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3643487203
Short name T215
Test name
Test status
Simulation time 58131767414 ps
CPU time 1242.93 seconds
Started Jan 21 12:33:14 PM PST 24
Finished Jan 21 12:53:58 PM PST 24
Peak memory 373956 kb
Host smart-19ffcde1-7180-4591-9f6c-701b00679e2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643487203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3643487203
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.934933003
Short name T397
Test name
Test status
Simulation time 1370852423 ps
CPU time 11.92 seconds
Started Jan 21 12:33:09 PM PST 24
Finished Jan 21 12:33:21 PM PST 24
Peak memory 202048 kb
Host smart-a1d36e3c-7297-4a52-92fb-5f2f383a1360
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934933003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.934933003
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1526296375
Short name T293
Test name
Test status
Simulation time 38120334436 ps
CPU time 6383.86 seconds
Started Jan 21 12:33:16 PM PST 24
Finished Jan 21 02:19:42 PM PST 24
Peak memory 625328 kb
Host smart-05763989-fed0-4afa-9e70-9775177beadb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1526296375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1526296375
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2552904864
Short name T667
Test name
Test status
Simulation time 4171280481 ps
CPU time 300.92 seconds
Started Jan 21 12:33:10 PM PST 24
Finished Jan 21 12:38:12 PM PST 24
Peak memory 202140 kb
Host smart-c53abe1a-e7d5-4f70-9e29-7e23a6790619
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552904864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2552904864
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1644343024
Short name T556
Test name
Test status
Simulation time 3073378003 ps
CPU time 98.88 seconds
Started Jan 21 12:33:09 PM PST 24
Finished Jan 21 12:34:48 PM PST 24
Peak memory 348576 kb
Host smart-50c6acea-e5a3-4ffb-9fe5-f69294e5f823
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644343024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1644343024
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3119021722
Short name T601
Test name
Test status
Simulation time 18611721328 ps
CPU time 434.35 seconds
Started Jan 21 12:33:22 PM PST 24
Finished Jan 21 12:40:37 PM PST 24
Peak memory 376844 kb
Host smart-ab536bbb-cc8f-4714-84c7-021616a4ddfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119021722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.3119021722
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.2163191409
Short name T799
Test name
Test status
Simulation time 23109785 ps
CPU time 0.61 seconds
Started Jan 21 12:33:30 PM PST 24
Finished Jan 21 12:33:32 PM PST 24
Peak memory 201980 kb
Host smart-08ec425a-8026-49b1-8545-22c4ad72733d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163191409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.2163191409
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.3299229715
Short name T226
Test name
Test status
Simulation time 116229595411 ps
CPU time 2504.73 seconds
Started Jan 21 12:33:28 PM PST 24
Finished Jan 21 01:15:13 PM PST 24
Peak memory 202156 kb
Host smart-a59cef09-45f9-4e5b-b6e2-f0e42ed545f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299229715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
3299229715
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.3844754505
Short name T137
Test name
Test status
Simulation time 5266975333 ps
CPU time 136.19 seconds
Started Jan 21 12:33:23 PM PST 24
Finished Jan 21 12:35:40 PM PST 24
Peak memory 210408 kb
Host smart-26344b8d-5c39-4c7a-afee-8c442b59f2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844754505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.3844754505
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.4176035522
Short name T603
Test name
Test status
Simulation time 3153502781 ps
CPU time 34.99 seconds
Started Jan 21 12:33:24 PM PST 24
Finished Jan 21 12:33:59 PM PST 24
Peak memory 251300 kb
Host smart-4f4356f5-7dfd-4000-bd3a-ce85babc9df2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176035522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.4176035522
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4235669342
Short name T574
Test name
Test status
Simulation time 1670946774 ps
CPU time 126.68 seconds
Started Jan 21 12:33:29 PM PST 24
Finished Jan 21 12:35:36 PM PST 24
Peak memory 211140 kb
Host smart-dfa6f48a-6548-48d4-a0a3-bc22743bc3e3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235669342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.4235669342
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.3507062906
Short name T551
Test name
Test status
Simulation time 43956974625 ps
CPU time 305.52 seconds
Started Jan 21 12:33:20 PM PST 24
Finished Jan 21 12:38:26 PM PST 24
Peak memory 202200 kb
Host smart-acf369e0-a828-4ca0-992f-3f2bbda129f0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507062906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.3507062906
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.4071888574
Short name T811
Test name
Test status
Simulation time 7598748624 ps
CPU time 500.72 seconds
Started Jan 21 12:33:14 PM PST 24
Finished Jan 21 12:41:36 PM PST 24
Peak memory 315304 kb
Host smart-30a6633a-b0b0-4f85-8f35-3b855fb8e840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071888574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.4071888574
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.3224403190
Short name T494
Test name
Test status
Simulation time 1889926265 ps
CPU time 37.56 seconds
Started Jan 21 12:33:21 PM PST 24
Finished Jan 21 12:33:59 PM PST 24
Peak memory 202024 kb
Host smart-4cf764bf-0925-454a-90b1-aa2965eb968d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224403190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s
ram_ctrl_partial_access.3224403190
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2972560513
Short name T738
Test name
Test status
Simulation time 5687076273 ps
CPU time 338.81 seconds
Started Jan 21 12:33:22 PM PST 24
Finished Jan 21 12:39:02 PM PST 24
Peak memory 202144 kb
Host smart-7fe264d9-c6b0-48a5-812f-efa2adce7131
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972560513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2972560513
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.2546007779
Short name T31
Test name
Test status
Simulation time 697644721 ps
CPU time 13.95 seconds
Started Jan 21 12:33:26 PM PST 24
Finished Jan 21 12:33:40 PM PST 24
Peak memory 202324 kb
Host smart-b72cc16b-3618-4562-83fd-b3148a829f40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546007779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2546007779
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.613487509
Short name T22
Test name
Test status
Simulation time 21293973275 ps
CPU time 1365.02 seconds
Started Jan 21 12:33:22 PM PST 24
Finished Jan 21 12:56:08 PM PST 24
Peak memory 380472 kb
Host smart-b47186f0-f378-4fe9-89b9-cf8e1da18b29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613487509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.613487509
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.18364564
Short name T486
Test name
Test status
Simulation time 2860212358 ps
CPU time 13.21 seconds
Started Jan 21 12:33:18 PM PST 24
Finished Jan 21 12:33:32 PM PST 24
Peak memory 202208 kb
Host smart-5fbee818-5aad-4ab4-975e-b805fa6a8266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18364564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.18364564
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.509326016
Short name T416
Test name
Test status
Simulation time 223193331788 ps
CPU time 5033.52 seconds
Started Jan 21 12:33:30 PM PST 24
Finished Jan 21 01:57:25 PM PST 24
Peak memory 380056 kb
Host smart-ba9f27d7-bfb7-47e1-93ee-17a3646a161c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509326016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_stress_all.509326016
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2404155596
Short name T487
Test name
Test status
Simulation time 3802265187 ps
CPU time 4284.44 seconds
Started Jan 21 12:33:29 PM PST 24
Finished Jan 21 01:44:54 PM PST 24
Peak memory 712792 kb
Host smart-551460aa-2975-49c7-ae18-a6e1e0f660b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2404155596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.2404155596
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.2615476367
Short name T268
Test name
Test status
Simulation time 9169293826 ps
CPU time 320.55 seconds
Started Jan 21 12:33:28 PM PST 24
Finished Jan 21 12:38:49 PM PST 24
Peak memory 202176 kb
Host smart-887f466a-557e-4c7f-8d0a-067880655ea7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615476367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.2615476367
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3751119008
Short name T787
Test name
Test status
Simulation time 773523960 ps
CPU time 63.45 seconds
Started Jan 21 12:33:23 PM PST 24
Finished Jan 21 12:34:28 PM PST 24
Peak memory 301112 kb
Host smart-46714205-146d-478c-9d66-8bc88c8503f3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751119008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.3751119008
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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