Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	306517403	1			T2	97620		T3	118428		T4	130246
instr_valid_dis	271449256	1			T2	97620		T3	118428		T4	130246
instr_en	29816635	1			T10	80928		T18	30998		T19	121122

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11479156	1			T10	108966		T18	166580		T19	173276
sram_ifetch_valid_disable	266580773	1			T2	97620		T3	118428		T4	130246
sram_ifetch_enable	28457474	1			T10	186124		T18	121670		T19	69982

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	306517403	1			T2	97620		T3	118428		T4	130246
hw_debug_en_valid_off	269762005	1			T2	97620		T3	118428		T4	130246
hw_debug_en_on	26673770	1			T10	153344		T18	223362		T19	66768

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	266580773	1			T2	97620		T3	118428		T4	130246
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	255248542	1			T2	97620		T3	118428		T4	130246
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9163565	1			T19	18758		T43	96		T44	72
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6522330	1			T10	63708		T18	49228		T19	13280
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4007826	1			T10	4704		T18	49228		T19	13280
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2151374	1			T10	59004		T120	16176		T125	41218
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3497614	1			T10	15408		T18	117352		T19	57632
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1236758	1			T10	15408		T18	86354		T19	57632
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1477694	1			T18	30998		T128	38046		T125	72338
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8190262	1			T10	55424		T18	28908		T19	9136
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1820124	1			T10	55424		T18	28908		T19	9136
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5527552	1			T120	73886		T125	104844		T124	31876

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	16431224	1			T10	21924		T117	2750		T120	36608
lc_exec_en	14985894	1			T10	82512		T18	77102		T23	44310
valid_exec_dis	265681819	1			T2	97620		T3	118428		T4	130246
invalid_exec_dis	39936630	1			T10	295090		T18	288250		T19	243258