| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1415836026 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1023084393 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1732235022 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2765075680 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.831947777 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3858963626 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3579117128 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2770210351 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3461385254 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1156621396 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2331585880 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3144314427 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1784013772 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.898091931 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.893707560 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2180190728 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4116842814 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2477230169 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1470411676 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1670524837 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4199992685 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1084843984 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1545138189 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1987521787 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.954377418 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2352537162 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.839000683 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1740634679 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4062330608 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1698158183 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2160114645 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1839152370 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.799564994 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4156991363 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2474955396 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2832530628 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1819429527 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3113146687 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.617556307 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2718271250 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3294517921 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1054190381 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.17977985 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2396970228 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3450991418 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3662303080 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1565493070 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4177936608 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.606694427 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1503995654 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1377982391 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.756712305 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2981357536 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1825178786 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3961207158 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2555110332 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.977496420 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1760773904 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4128789295 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.769974408 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1125975621 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1370756804 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4074416974 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1652733148 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.620244965 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1991417409 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.171634717 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1215676357 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2743416853 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3400462204 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2378717517 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4041167003 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2002117078 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1470675509 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.966995072 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1560233148 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3980176668 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.646884850 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3750406891 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.624813575 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1505869044 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.702382033 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3289598565 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1842471773 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1353579356 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3159290779 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2067820667 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3648739318 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2657659287 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2718614506 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3238055504 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3721849315 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2947091314 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1185487063 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3859491072 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1980080450 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2559354304 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3408239676 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.677695463 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1241087575 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1852366306 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2482244037 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1745547624 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1619378555 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2415534569 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.457570345 |
| /workspace/coverage/default/0.sram_ctrl_bijection.4190369053 |
| /workspace/coverage/default/0.sram_ctrl_executable.2098242828 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.3934164527 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1181518453 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.526386552 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.1309520518 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.1846067518 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.279191363 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2475548142 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1822639170 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.552994035 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3460821142 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.3540289681 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3329998334 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1320189894 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.816436490 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2640369587 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2279850912 |
| /workspace/coverage/default/1.sram_ctrl_bijection.4066927736 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1500327058 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.4026528898 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.422483936 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.3778660345 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.2659558172 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3984163348 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.3898215388 |
| /workspace/coverage/default/1.sram_ctrl_regwen.4062089914 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.1716325851 |
| /workspace/coverage/default/1.sram_ctrl_smoke.708449554 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.3152996857 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1955494793 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2103878738 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1379629557 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1479722218 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2555622479 |
| /workspace/coverage/default/10.sram_ctrl_bijection.3446900748 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.2033963526 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.1099231037 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.288578246 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3242114727 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.2411785706 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2397074503 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3745502366 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1859355268 |
| /workspace/coverage/default/10.sram_ctrl_regwen.50327785 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2030549197 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.4021952631 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2871329166 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.261773317 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1372672013 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3754442323 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.3725776333 |
| /workspace/coverage/default/11.sram_ctrl_bijection.956950410 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1025176067 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3765530835 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.391592512 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1883779265 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3491118545 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3026572256 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2803699258 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2954115 |
| /workspace/coverage/default/11.sram_ctrl_smoke.227940249 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2039648800 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.275095135 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1349575292 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2541160080 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3087930194 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.1080405346 |
| /workspace/coverage/default/12.sram_ctrl_bijection.455298018 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.4078144074 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.59305245 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2096291630 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.857260473 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3113790746 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.2474618012 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2727882787 |
| /workspace/coverage/default/12.sram_ctrl_smoke.668100733 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1318831441 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.677545417 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3001075547 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.973774574 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1968548001 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.4215212092 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2607081619 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.2743024421 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3646552282 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3716775738 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.1236535902 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.599523528 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.2526402135 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3542685009 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1615670333 |
| /workspace/coverage/default/13.sram_ctrl_regwen.1536028865 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1769022224 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.1736093542 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.695259615 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3653709697 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1791234767 |
| /workspace/coverage/default/14.sram_ctrl_bijection.478862089 |
| /workspace/coverage/default/14.sram_ctrl_executable.3385523384 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.2522177163 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3266456884 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1879221841 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3075941977 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.1972823513 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.1933229318 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1659633779 |
| /workspace/coverage/default/14.sram_ctrl_smoke.2897031840 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.900014754 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.984856431 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4029443625 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2793260115 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.1714745861 |
| /workspace/coverage/default/15.sram_ctrl_bijection.4010200010 |
| /workspace/coverage/default/15.sram_ctrl_executable.309365777 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.1924799493 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.4125054128 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2088403699 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.155425459 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.3932732704 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.1224929371 |
| /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1391194497 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.1147716329 |
| /workspace/coverage/default/15.sram_ctrl_regwen.1552833937 |
| /workspace/coverage/default/15.sram_ctrl_smoke.3121081614 |
| /workspace/coverage/default/15.sram_ctrl_stress_all.1568513795 |
| /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1383605210 |
| /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2861365425 |
| /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1980244478 |
| /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2625690868 |
| /workspace/coverage/default/16.sram_ctrl_alert_test.3297593746 |
| /workspace/coverage/default/16.sram_ctrl_bijection.653099355 |
| /workspace/coverage/default/16.sram_ctrl_lc_escalation.919092869 |
| /workspace/coverage/default/16.sram_ctrl_max_throughput.3974836863 |
| /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1604214849 |
| /workspace/coverage/default/16.sram_ctrl_mem_walk.212995640 |
| /workspace/coverage/default/16.sram_ctrl_multiple_keys.3933365881 |
| /workspace/coverage/default/16.sram_ctrl_partial_access.2399928932 |
| /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3674773998 |
| /workspace/coverage/default/16.sram_ctrl_ram_cfg.2564644943 |
| /workspace/coverage/default/16.sram_ctrl_regwen.2555187788 |
| /workspace/coverage/default/16.sram_ctrl_smoke.4037763966 |
| /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3294256449 |
| /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1486131107 |
| /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2105980974 |
| /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3842789577 |
| /workspace/coverage/default/17.sram_ctrl_alert_test.3285921138 |
| /workspace/coverage/default/17.sram_ctrl_bijection.2400411709 |
| /workspace/coverage/default/17.sram_ctrl_executable.3487327042 |
| /workspace/coverage/default/17.sram_ctrl_max_throughput.597546588 |
| /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3750669172 |
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| /workspace/coverage/default/47.sram_ctrl_multiple_keys.459370248 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.1215905158 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3509336758 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.955248331 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3336269888 |
| /workspace/coverage/default/47.sram_ctrl_smoke.331535720 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.247701205 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1048562583 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2236894872 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1976320948 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.291413047 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.3524868270 |
| /workspace/coverage/default/48.sram_ctrl_bijection.1128812149 |
| /workspace/coverage/default/48.sram_ctrl_executable.522776825 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1507729690 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1793043793 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.3042112623 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.959240217 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.1701473924 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3586400100 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3173408735 |
| /workspace/coverage/default/48.sram_ctrl_regwen.1907153695 |
| /workspace/coverage/default/48.sram_ctrl_smoke.2676469995 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1058877399 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3047799961 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1103672051 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3842799634 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.2201775796 |
| /workspace/coverage/default/49.sram_ctrl_bijection.2428094759 |
| /workspace/coverage/default/49.sram_ctrl_executable.465283807 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.2472731968 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2953146689 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.41684268 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.2494289875 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.3812760094 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.369954986 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2755657529 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.4240063201 |
| /workspace/coverage/default/49.sram_ctrl_regwen.1561284117 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1934759531 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.2780074022 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2285462896 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2389471940 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1127448895 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.223971501 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.18237290 |
| /workspace/coverage/default/5.sram_ctrl_bijection.1078911828 |
| /workspace/coverage/default/5.sram_ctrl_executable.2481343661 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3284059515 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.37058189 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4193384930 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.1844602593 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.3845838479 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.3551042550 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3225435476 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1546024100 |
| /workspace/coverage/default/5.sram_ctrl_regwen.2970895505 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2836648685 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.2330489881 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.765409348 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3268665457 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2180707941 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1754001776 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3236149774 |
| /workspace/coverage/default/6.sram_ctrl_bijection.2567734391 |
| /workspace/coverage/default/6.sram_ctrl_executable.970230036 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2486065359 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.856004240 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4093220853 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.545612294 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.1902829326 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.1185179522 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2509884829 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.768427271 |
| /workspace/coverage/default/6.sram_ctrl_regwen.534290898 |
| /workspace/coverage/default/6.sram_ctrl_smoke.62722506 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.3673358713 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.519214745 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.424816198 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1722054752 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.842515561 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.1813076201 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2477496751 |
| /workspace/coverage/default/7.sram_ctrl_executable.201095161 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.401382359 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3721582104 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.752706509 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1291740596 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.4025811846 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.385423652 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.1692638052 |
| /workspace/coverage/default/7.sram_ctrl_regwen.767211298 |
| /workspace/coverage/default/7.sram_ctrl_smoke.158541355 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2692897304 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1088640136 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.2958960892 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1574339138 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2033647921 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1734470784 |
| /workspace/coverage/default/8.sram_ctrl_bijection.133825503 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.1127713070 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.2946857157 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2304042346 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.3732612257 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2746485481 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3069785091 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2388915304 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.14824206 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2736204305 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3796632892 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.457881121 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1011817201 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2703899535 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1408092211 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1947249859 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.279881417 |
| /workspace/coverage/default/9.sram_ctrl_bijection.1353683209 |
| /workspace/coverage/default/9.sram_ctrl_executable.128866324 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.425195590 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.2999684494 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.990203814 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.2442901478 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.1274970008 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.4079727515 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.669651305 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.700111166 |
| /workspace/coverage/default/9.sram_ctrl_regwen.745321324 |
| /workspace/coverage/default/9.sram_ctrl_smoke.981508472 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.2656298748 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3324845250 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1295389997 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2504322663 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3343397327 |
|
|
Jan 24 08:16:27 PM PST 24 |
Jan 24 08:16:35 PM PST 24 |
5574368006 ps |
| T2 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.645983815 |
|
|
Jan 24 08:19:25 PM PST 24 |
Jan 24 08:26:27 PM PST 24 |
9772491126 ps |
| T3 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.2474845728 |
|
|
Jan 24 08:06:19 PM PST 24 |
Jan 24 08:11:50 PM PST 24 |
4512703718 ps |
| T4 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1623421289 |
|
|
Jan 24 08:36:52 PM PST 24 |
Jan 24 08:39:23 PM PST 24 |
8734380221 ps |
| T5 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2602983574 |
|
|
Jan 24 08:19:05 PM PST 24 |
Jan 24 08:20:22 PM PST 24 |
1406307591 ps |
| T10 |
/workspace/coverage/default/45.sram_ctrl_regwen.169502271 |
|
|
Jan 24 08:27:40 PM PST 24 |
Jan 24 08:45:16 PM PST 24 |
190275419180 ps |
| T11 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.3990848957 |
|
|
Jan 24 08:20:38 PM PST 24 |
Jan 24 08:21:44 PM PST 24 |
1483135488 ps |
| T12 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1663209216 |
|
|
Jan 24 08:08:22 PM PST 24 |
Jan 24 08:22:27 PM PST 24 |
71091785075 ps |
| T13 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.4186521093 |
|
|
Jan 24 08:22:45 PM PST 24 |
Jan 24 08:30:47 PM PST 24 |
26179289815 ps |
| T14 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1461902348 |
|
|
Jan 24 08:10:00 PM PST 24 |
Jan 24 08:10:24 PM PST 24 |
445103212 ps |
| T16 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.92064035 |
|
|
Jan 24 07:57:35 PM PST 24 |
Jan 24 08:10:24 PM PST 24 |
3929940826 ps |
| T17 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2016431089 |
|
|
Jan 24 09:30:30 PM PST 24 |
Jan 24 09:31:46 PM PST 24 |
3512945886 ps |
| T94 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2832765724 |
|
|
Jan 24 08:06:59 PM PST 24 |
Jan 24 08:11:16 PM PST 24 |
4293346141 ps |
| T18 |
/workspace/coverage/default/4.sram_ctrl_regwen.3445143310 |
|
|
Jan 24 07:58:01 PM PST 24 |
Jan 24 08:23:29 PM PST 24 |
12277820317 ps |
| T15 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4061214633 |
|
|
Jan 24 08:24:28 PM PST 24 |
Jan 24 08:31:54 PM PST 24 |
79383681977 ps |
| T25 |
/workspace/coverage/default/9.sram_ctrl_alert_test.279881417 |
|
|
Jan 24 08:24:13 PM PST 24 |
Jan 24 08:24:21 PM PST 24 |
38576596 ps |
| T95 |
/workspace/coverage/default/8.sram_ctrl_smoke.3796632892 |
|
|
Jan 24 07:59:28 PM PST 24 |
Jan 24 07:59:52 PM PST 24 |
4451186585 ps |
| T6 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3914506754 |
|
|
Jan 24 08:05:13 PM PST 24 |
Jan 24 08:06:52 PM PST 24 |
19583449868 ps |
| T130 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1647860552 |
|
|
Jan 24 08:20:10 PM PST 24 |
Jan 24 08:22:33 PM PST 24 |
3112635793 ps |
| T131 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.658161422 |
|
|
Jan 24 08:26:07 PM PST 24 |
Jan 24 08:28:53 PM PST 24 |
2729395107 ps |
| T132 |
/workspace/coverage/default/47.sram_ctrl_smoke.331535720 |
|
|
Jan 24 09:19:57 PM PST 24 |
Jan 24 09:20:27 PM PST 24 |
1099150535 ps |
| T33 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1546024100 |
|
|
Jan 24 07:58:28 PM PST 24 |
Jan 24 07:58:43 PM PST 24 |
708378515 ps |
| T20 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2645780590 |
|
|
Jan 24 09:06:01 PM PST 24 |
Jan 24 09:18:11 PM PST 24 |
25271729652 ps |
| T19 |
/workspace/coverage/default/15.sram_ctrl_regwen.1552833937 |
|
|
Jan 24 08:03:38 PM PST 24 |
Jan 24 08:10:49 PM PST 24 |
10341889399 ps |
| T65 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1247203635 |
|
|
Jan 24 08:16:26 PM PST 24 |
Jan 24 08:26:31 PM PST 24 |
33517372770 ps |
| T66 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1178754081 |
|
|
Jan 24 09:07:10 PM PST 24 |
Jan 24 09:12:22 PM PST 24 |
17445999461 ps |
| T30 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1149108206 |
|
|
Jan 24 08:20:14 PM PST 24 |
Jan 24 09:06:51 PM PST 24 |
2078301039 ps |
| T53 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.2442901478 |
|
|
Jan 24 08:00:22 PM PST 24 |
Jan 24 08:04:34 PM PST 24 |
30316908575 ps |
| T54 |
/workspace/coverage/default/16.sram_ctrl_bijection.653099355 |
|
|
Jan 24 08:03:53 PM PST 24 |
Jan 24 08:29:57 PM PST 24 |
276588906458 ps |
| T9 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1706153061 |
|
|
Jan 24 07:58:05 PM PST 24 |
Jan 24 07:58:08 PM PST 24 |
86221694 ps |
| T26 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3236149774 |
|
|
Jan 24 07:59:01 PM PST 24 |
Jan 24 07:59:03 PM PST 24 |
32467268 ps |
| T37 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.752706509 |
|
|
Jan 24 07:59:18 PM PST 24 |
Jan 24 08:01:40 PM PST 24 |
14046465953 ps |
| T27 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3936338536 |
|
|
Jan 24 08:13:15 PM PST 24 |
Jan 24 08:13:16 PM PST 24 |
27953078 ps |
| T38 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.459890958 |
|
|
Jan 24 08:11:20 PM PST 24 |
Jan 24 08:13:56 PM PST 24 |
35785826162 ps |
| T34 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3310841711 |
|
|
Jan 24 08:14:03 PM PST 24 |
Jan 24 08:14:11 PM PST 24 |
360509416 ps |
| T39 |
/workspace/coverage/default/46.sram_ctrl_bijection.1488944798 |
|
|
Jan 24 08:54:38 PM PST 24 |
Jan 24 09:13:50 PM PST 24 |
64267477749 ps |
| T40 |
/workspace/coverage/default/46.sram_ctrl_stress_all.150222773 |
|
|
Jan 24 08:28:57 PM PST 24 |
Jan 24 10:12:59 PM PST 24 |
187578836751 ps |
| T41 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3654548700 |
|
|
Jan 24 08:25:51 PM PST 24 |
Jan 24 08:30:59 PM PST 24 |
2067820398 ps |
| T42 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3932732704 |
|
|
Jan 24 08:03:07 PM PST 24 |
Jan 24 08:25:17 PM PST 24 |
96197105927 ps |
| T100 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.4145593002 |
|
|
Jan 24 08:48:58 PM PST 24 |
Jan 24 08:53:25 PM PST 24 |
15769447286 ps |
| T133 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1764564740 |
|
|
Jan 24 08:24:56 PM PST 24 |
Jan 24 08:26:16 PM PST 24 |
2970665145 ps |
| T134 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2421437015 |
|
|
Jan 24 08:16:07 PM PST 24 |
Jan 24 08:16:09 PM PST 24 |
36715207 ps |
| T127 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.2933666478 |
|
|
Jan 24 08:10:56 PM PST 24 |
Jan 24 08:31:00 PM PST 24 |
105292056066 ps |
| T31 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2285462896 |
|
|
Jan 24 08:31:51 PM PST 24 |
Jan 24 09:25:34 PM PST 24 |
552560936 ps |
| T135 |
/workspace/coverage/default/41.sram_ctrl_bijection.3631199688 |
|
|
Jan 24 08:23:32 PM PST 24 |
Jan 24 08:50:31 PM PST 24 |
47160784533 ps |
| T32 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3753402627 |
|
|
Jan 24 09:08:18 PM PST 24 |
Jan 24 10:30:33 PM PST 24 |
7140159884 ps |
| T101 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2752188536 |
|
|
Jan 24 08:09:26 PM PST 24 |
Jan 24 08:15:42 PM PST 24 |
29459493016 ps |
| T23 |
/workspace/coverage/default/22.sram_ctrl_regwen.394598664 |
|
|
Jan 24 08:08:36 PM PST 24 |
Jan 24 08:22:28 PM PST 24 |
9331392846 ps |
| T45 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3961207158 |
|
|
Jan 24 04:29:29 PM PST 24 |
Jan 24 04:29:36 PM PST 24 |
1306170746 ps |
| T56 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2718271250 |
|
|
Jan 24 04:29:06 PM PST 24 |
Jan 24 04:29:08 PM PST 24 |
18355627 ps |
| T57 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1370756804 |
|
|
Jan 24 04:27:44 PM PST 24 |
Jan 24 04:27:47 PM PST 24 |
51347016 ps |
| T58 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3713951407 |
|
|
Jan 24 04:28:28 PM PST 24 |
Jan 24 04:28:30 PM PST 24 |
13656372 ps |
| T59 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1549074681 |
|
|
Jan 24 04:29:13 PM PST 24 |
Jan 24 04:29:16 PM PST 24 |
17133840 ps |
| T43 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1497058672 |
|
|
Jan 24 04:28:19 PM PST 24 |
Jan 24 04:28:23 PM PST 24 |
265220474 ps |
| T60 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.624813575 |
|
|
Jan 24 04:27:58 PM PST 24 |
Jan 24 04:28:02 PM PST 24 |
22026237 ps |
| T46 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1991417409 |
|
|
Jan 24 04:27:48 PM PST 24 |
Jan 24 04:27:53 PM PST 24 |
47854799 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1156621396 |
|
|
Jan 24 04:33:48 PM PST 24 |
Jan 24 04:33:57 PM PST 24 |
41270073 ps |
| T97 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4156991363 |
|
|
Jan 24 04:28:59 PM PST 24 |
Jan 24 04:29:01 PM PST 24 |
16035370 ps |
| T47 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2067820667 |
|
|
Jan 24 04:28:17 PM PST 24 |
Jan 24 04:28:24 PM PST 24 |
359214574 ps |
| T44 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2945167682 |
|
|
Jan 24 04:29:13 PM PST 24 |
Jan 24 04:29:17 PM PST 24 |
596865402 ps |
| T61 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3648739318 |
|
|
Jan 24 04:28:19 PM PST 24 |
Jan 24 04:28:21 PM PST 24 |
26039538 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3750406891 |
|
|
Jan 24 04:28:03 PM PST 24 |
Jan 24 04:28:10 PM PST 24 |
14542622 ps |
| T48 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1745547624 |
|
|
Jan 24 04:28:35 PM PST 24 |
Jan 24 04:28:38 PM PST 24 |
66522782 ps |
| T63 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3461385254 |
|
|
Jan 24 05:18:01 PM PST 24 |
Jan 24 05:18:06 PM PST 24 |
28113066 ps |
| T64 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.617556307 |
|
|
Jan 24 04:29:08 PM PST 24 |
Jan 24 04:29:10 PM PST 24 |
11275462 ps |
| T49 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1852366306 |
|
|
Jan 24 04:28:36 PM PST 24 |
Jan 24 04:28:42 PM PST 24 |
687259789 ps |
| T50 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1505869044 |
|
|
Jan 24 04:27:52 PM PST 24 |
Jan 24 04:27:59 PM PST 24 |
39662476 ps |
| T136 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.898091931 |
|
|
Jan 24 04:28:39 PM PST 24 |
Jan 24 04:28:46 PM PST 24 |
355163755 ps |
| T51 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1084843984 |
|
|
Jan 24 04:37:05 PM PST 24 |
Jan 24 04:37:09 PM PST 24 |
577989326 ps |
| T137 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.769974408 |
|
|
Jan 24 04:27:57 PM PST 24 |
Jan 24 04:28:00 PM PST 24 |
64112718 ps |
| T129 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1054190381 |
|
|
Jan 24 04:29:12 PM PST 24 |
Jan 24 04:29:26 PM PST 24 |
704158443 ps |
| T67 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1842471773 |
|
|
Jan 24 04:28:07 PM PST 24 |
Jan 24 04:28:13 PM PST 24 |
13808804 ps |
| T98 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.17977985 |
|
|
Jan 24 04:29:16 PM PST 24 |
Jan 24 04:29:19 PM PST 24 |
27164295 ps |
| T99 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3721849315 |
|
|
Jan 24 04:28:20 PM PST 24 |
Jan 24 04:28:23 PM PST 24 |
122047162 ps |
| T52 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1353579356 |
|
|
Jan 24 04:28:15 PM PST 24 |
Jan 24 04:28:18 PM PST 24 |
44558553 ps |
| T55 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2396970228 |
|
|
Jan 24 04:29:11 PM PST 24 |
Jan 24 04:29:16 PM PST 24 |
149362679 ps |
| T138 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.893707560 |
|
|
Jan 24 04:28:39 PM PST 24 |
Jan 24 04:28:40 PM PST 24 |
112759669 ps |
| T139 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1760773904 |
|
|
Jan 24 04:29:26 PM PST 24 |
Jan 24 04:29:29 PM PST 24 |
29006833 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3845153786 |
|
|
Jan 24 04:27:51 PM PST 24 |
Jan 24 04:27:55 PM PST 24 |
291491098 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2482244037 |
|
|
Jan 24 04:28:30 PM PST 24 |
Jan 24 04:28:32 PM PST 24 |
32790966 ps |
| T105 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3289598565 |
|
|
Jan 24 04:43:25 PM PST 24 |
Jan 24 04:43:31 PM PST 24 |
973791445 ps |
| T108 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1545138189 |
|
|
Jan 24 04:28:48 PM PST 24 |
Jan 24 04:28:51 PM PST 24 |
624681511 ps |
| T140 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2352537162 |
|
|
Jan 24 04:28:51 PM PST 24 |
Jan 24 04:28:54 PM PST 24 |
50985717 ps |
| T141 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3980176668 |
|
|
Jan 24 04:27:58 PM PST 24 |
Jan 24 04:28:02 PM PST 24 |
12784928 ps |
| T68 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2743416853 |
|
|
Jan 24 05:12:29 PM PST 24 |
Jan 24 05:12:33 PM PST 24 |
18413650 ps |
| T71 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4074416974 |
|
|
Jan 24 04:42:33 PM PST 24 |
Jan 24 04:42:43 PM PST 24 |
714371710 ps |
| T72 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3450991418 |
|
|
Jan 24 04:29:11 PM PST 24 |
Jan 24 04:29:15 PM PST 24 |
179564490 ps |
| T73 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1839152370 |
|
|
Jan 24 04:28:51 PM PST 24 |
Jan 24 04:28:54 PM PST 24 |
152160643 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2832530628 |
|
|
Jan 24 04:28:54 PM PST 24 |
Jan 24 04:28:59 PM PST 24 |
424552634 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.966995072 |
|
|
Jan 24 04:28:03 PM PST 24 |
Jan 24 04:28:10 PM PST 24 |
24424536 ps |
| T70 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.977496420 |
|
|
Jan 24 04:29:27 PM PST 24 |
Jan 24 04:29:29 PM PST 24 |
53369777 ps |
| T85 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1825178786 |
|
|
Jan 24 05:17:41 PM PST 24 |
Jan 24 05:17:46 PM PST 24 |
158673421 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1652733148 |
|
|
Jan 24 04:38:22 PM PST 24 |
Jan 24 04:38:29 PM PST 24 |
33164509 ps |
| T142 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4062330608 |
|
|
Jan 24 04:28:46 PM PST 24 |
Jan 24 04:28:47 PM PST 24 |
12673881 ps |
| T143 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2718614506 |
|
|
Jan 24 04:28:20 PM PST 24 |
Jan 24 04:28:25 PM PST 24 |
1314267735 ps |
| T144 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4128789295 |
|
|
Jan 24 04:29:27 PM PST 24 |
Jan 24 04:29:29 PM PST 24 |
245037731 ps |
| T111 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1784013772 |
|
|
Jan 24 04:27:48 PM PST 24 |
Jan 24 04:27:52 PM PST 24 |
302241790 ps |
| T145 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2947091314 |
|
|
Jan 24 04:28:22 PM PST 24 |
Jan 24 04:28:25 PM PST 24 |
22566896 ps |
| T146 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2378717517 |
|
|
Jan 24 04:28:00 PM PST 24 |
Jan 24 04:28:05 PM PST 24 |
20777067 ps |
| T147 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3113146687 |
|
|
Jan 24 04:29:11 PM PST 24 |
Jan 24 04:29:27 PM PST 24 |
767466787 ps |
| T148 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2002117078 |
|
|
Jan 24 04:27:54 PM PST 24 |
Jan 24 04:27:59 PM PST 24 |
382124596 ps |
| T149 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4116842814 |
|
|
Jan 24 04:48:38 PM PST 24 |
Jan 24 04:48:47 PM PST 24 |
265918665 ps |
| T112 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.702382033 |
|
|
Jan 24 06:25:30 PM PST 24 |
Jan 24 06:25:32 PM PST 24 |
193627241 ps |
| T150 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3662303080 |
|
|
Jan 24 04:29:11 PM PST 24 |
Jan 24 04:29:19 PM PST 24 |
353527709 ps |
| T151 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2555110332 |
|
|
Jan 24 04:29:26 PM PST 24 |
Jan 24 04:29:28 PM PST 24 |
16756110 ps |
| T152 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1125975621 |
|
|
Jan 24 04:27:48 PM PST 24 |
Jan 24 04:27:52 PM PST 24 |
46864693 ps |
| T153 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4199992685 |
|
|
Jan 24 04:28:49 PM PST 24 |
Jan 24 04:28:52 PM PST 24 |
71786954 ps |
| T154 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3400462204 |
|
|
Jan 24 04:27:54 PM PST 24 |
Jan 24 04:28:03 PM PST 24 |
367674624 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1819429527 |
|
|
Jan 24 04:28:57 PM PST 24 |
Jan 24 04:29:01 PM PST 24 |
202195492 ps |
| T155 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3858963626 |
|
|
Jan 24 05:44:32 PM PST 24 |
Jan 24 05:44:34 PM PST 24 |
11959462 ps |
| T156 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2477230169 |
|
|
Jan 24 04:32:44 PM PST 24 |
Jan 24 04:32:48 PM PST 24 |
453817298 ps |
| T157 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2657659287 |
|
|
Jan 24 04:28:19 PM PST 24 |
Jan 24 04:28:21 PM PST 24 |
15066197 ps |
| T109 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2449947841 |
|
|
Jan 24 04:29:04 PM PST 24 |
Jan 24 04:29:07 PM PST 24 |
644689683 ps |
| T158 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1560233148 |
|
|
Jan 24 04:28:02 PM PST 24 |
Jan 24 04:28:09 PM PST 24 |
338862040 ps |
| T159 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2770210351 |
|
|
Jan 24 04:27:50 PM PST 24 |
Jan 24 04:27:54 PM PST 24 |
64474223 ps |
| T160 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1732235022 |
|
|
Jan 24 04:27:36 PM PST 24 |
Jan 24 04:27:37 PM PST 24 |
15108060 ps |
| T161 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2160114645 |
|
|
Jan 24 05:06:52 PM PST 24 |
Jan 24 05:07:01 PM PST 24 |
1136057333 ps |
| T162 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1740634679 |
|
|
Jan 24 04:28:53 PM PST 24 |
Jan 24 04:29:00 PM PST 24 |
1440071515 ps |
| T163 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.674887990 |
|
|
Jan 24 06:06:34 PM PST 24 |
Jan 24 06:06:48 PM PST 24 |
359106223 ps |
| T164 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.954377418 |
|
|
Jan 24 04:28:47 PM PST 24 |
Jan 24 04:28:49 PM PST 24 |
195059028 ps |
| T165 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3144314427 |
|
|
Jan 24 04:27:51 PM PST 24 |
Jan 24 04:27:56 PM PST 24 |
91703369 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1023084393 |
|
|
Jan 24 04:27:46 PM PST 24 |
Jan 24 04:27:50 PM PST 24 |
105870618 ps |
| T86 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4041167003 |
|
|
Jan 24 04:49:39 PM PST 24 |
Jan 24 04:49:42 PM PST 24 |
16825326 ps |
| T87 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3294517921 |
|
|
Jan 24 04:29:06 PM PST 24 |
Jan 24 04:29:09 PM PST 24 |
44593604 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.171634717 |
|
|
Jan 24 04:27:52 PM PST 24 |
Jan 24 04:27:55 PM PST 24 |
41646601 ps |
| T75 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1415836026 |
|
|
Jan 24 04:30:42 PM PST 24 |
Jan 24 04:30:57 PM PST 24 |
22974658 ps |
| T89 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.620244965 |
|
|
Jan 24 04:28:01 PM PST 24 |
Jan 24 04:28:07 PM PST 24 |
23310604 ps |
| T90 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3159290779 |
|
|
Jan 24 04:28:14 PM PST 24 |
Jan 24 04:28:18 PM PST 24 |
141327259 ps |
| T91 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1185487063 |
|
|
Jan 24 04:28:19 PM PST 24 |
Jan 24 04:28:23 PM PST 24 |
513784126 ps |
| T92 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3408239676 |
|
|
Jan 24 04:28:35 PM PST 24 |
Jan 24 04:28:37 PM PST 24 |
26893761 ps |
| T166 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4177936608 |
|
|
Jan 24 04:29:14 PM PST 24 |
Jan 24 04:29:16 PM PST 24 |
50977283 ps |
| T167 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.646884850 |
|
|
Jan 24 04:28:12 PM PST 24 |
Jan 24 04:28:28 PM PST 24 |
1378162804 ps |
| T168 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2559354304 |
|
|
Jan 24 04:28:30 PM PST 24 |
Jan 24 04:28:32 PM PST 24 |
24603166 ps |
| T169 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1241087575 |
|
|
Jan 24 04:28:28 PM PST 24 |
Jan 24 04:28:31 PM PST 24 |
255131691 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1470675509 |
|
|
Jan 24 04:27:55 PM PST 24 |
Jan 24 04:27:59 PM PST 24 |
77915017 ps |
| T114 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4035689884 |
|
|
Jan 24 06:01:27 PM PST 24 |
Jan 24 06:01:29 PM PST 24 |
90089379 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1987521787 |
|
|
Jan 24 04:28:46 PM PST 24 |
Jan 24 04:28:47 PM PST 24 |
16729129 ps |
| T170 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2765075680 |
|
|
Jan 24 06:23:28 PM PST 24 |
Jan 24 06:23:44 PM PST 24 |
3837983298 ps |
| T171 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2474955396 |
|
|
Jan 24 04:29:07 PM PST 24 |
Jan 24 04:29:09 PM PST 24 |
22571477 ps |
| T172 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1377982391 |
|
|
Jan 24 04:29:26 PM PST 24 |
Jan 24 04:29:27 PM PST 24 |
12428084 ps |
| T173 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1980080450 |
|
|
Jan 24 04:28:25 PM PST 24 |
Jan 24 04:28:33 PM PST 24 |
358662078 ps |
| T174 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.839000683 |
|
|
Jan 24 04:28:50 PM PST 24 |
Jan 24 04:28:53 PM PST 24 |
74894663 ps |
| T175 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2981357536 |
|
|
Jan 24 04:41:53 PM PST 24 |
Jan 24 04:42:00 PM PST 24 |
142654963 ps |
| T176 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3579117128 |
|
|
Jan 24 04:27:46 PM PST 24 |
Jan 24 04:27:49 PM PST 24 |
33025267 ps |
| T177 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.606694427 |
|
|
Jan 24 04:29:14 PM PST 24 |
Jan 24 04:29:18 PM PST 24 |
321347696 ps |
| T178 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2331585880 |
|
|
Jan 24 07:17:02 PM PST 24 |
Jan 24 07:17:04 PM PST 24 |
15329551 ps |
| T179 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1619378555 |
|
|
Jan 24 04:28:30 PM PST 24 |
Jan 24 04:28:33 PM PST 24 |
715715570 ps |
| T180 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3238055504 |
|
|
Jan 24 04:28:18 PM PST 24 |
Jan 24 04:28:25 PM PST 24 |
343722202 ps |
| T181 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.831947777 |
|
|
Jan 24 04:27:43 PM PST 24 |
Jan 24 04:27:46 PM PST 24 |
73324293 ps |
| T182 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1698158183 |
|
|
Jan 24 04:28:53 PM PST 24 |
Jan 24 04:28:55 PM PST 24 |
71268663 ps |
| T183 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.677695463 |
|
|
Jan 24 04:28:28 PM PST 24 |
Jan 24 04:28:32 PM PST 24 |
69329597 ps |
| T184 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2180190728 |
|
|
Jan 24 04:28:38 PM PST 24 |
Jan 24 04:28:39 PM PST 24 |
50073529 ps |
| T185 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1565493070 |
|
|
Jan 24 04:29:11 PM PST 24 |
Jan 24 04:29:14 PM PST 24 |
44451369 ps |
| T186 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1470411676 |
|
|
Jan 24 04:28:46 PM PST 24 |
Jan 24 04:28:52 PM PST 24 |
343211676 ps |
| T187 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.799564994 |
|
|
Jan 24 04:29:06 PM PST 24 |
Jan 24 04:29:19 PM PST 24 |
723001824 ps |
| T188 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.756712305 |
|
|
Jan 24 04:29:27 PM PST 24 |
Jan 24 04:29:29 PM PST 24 |
25356663 ps |
| T189 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1215676357 |
|
|
Jan 24 04:27:59 PM PST 24 |
Jan 24 04:28:04 PM PST 24 |
183046153 ps |
| T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3859491072 |
|
|
Jan 24 04:28:20 PM PST 24 |
Jan 24 04:28:25 PM PST 24 |
390081156 ps |
| T76 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1670524837 |
|
|
Jan 24 04:28:50 PM PST 24 |
Jan 24 04:28:52 PM PST 24 |
214934030 ps |
| T190 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1503995654 |
|
|
Jan 24 04:29:24 PM PST 24 |
Jan 24 04:29:30 PM PST 24 |
1424050056 ps |
| T103 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1941436108 |
|
|
Jan 24 08:08:22 PM PST 24 |
Jan 24 08:12:58 PM PST 24 |
11946399133 ps |
| T7 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2607589120 |
|
|
Jan 24 08:08:33 PM PST 24 |
Jan 24 08:09:05 PM PST 24 |
4541684298 ps |
| T191 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2889867380 |
|
|
Jan 24 08:09:08 PM PST 24 |
Jan 24 08:09:10 PM PST 24 |
22800033 ps |
| T192 |
/workspace/coverage/default/37.sram_ctrl_bijection.1329208618 |
|
|
Jan 24 08:20:29 PM PST 24 |
Jan 24 08:44:57 PM PST 24 |
21320801724 ps |
| T193 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.669572544 |
|
|
Jan 24 08:52:44 PM PST 24 |
Jan 24 08:54:15 PM PST 24 |
741085868 ps |
| T77 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.1943029136 |
|
|
Jan 25 01:19:26 AM PST 24 |
Jan 25 01:39:32 AM PST 24 |
14710527519 ps |
| T194 |
/workspace/coverage/default/23.sram_ctrl_alert_test.1114753001 |
|
|
Jan 24 10:20:01 PM PST 24 |
Jan 24 10:20:07 PM PST 24 |
15083699 ps |
| T195 |
/workspace/coverage/default/29.sram_ctrl_smoke.1790918943 |
|
|
Jan 24 08:26:50 PM PST 24 |
Jan 24 08:29:20 PM PST 24 |
1851582484 ps |
| T196 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1102398580 |
|
|
Jan 24 08:26:06 PM PST 24 |
Jan 24 10:33:42 PM PST 24 |
2464185986 ps |
| T197 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.3056913303 |
|
|
Jan 24 07:58:04 PM PST 24 |
Jan 24 07:58:12 PM PST 24 |
1355464926 ps |
| T117 |
/workspace/coverage/default/18.sram_ctrl_regwen.1834841190 |
|
|
Jan 24 08:05:27 PM PST 24 |
Jan 24 08:26:03 PM PST 24 |
12784473864 ps |
| T198 |
/workspace/coverage/default/2.sram_ctrl_smoke.3848248222 |
|
|
Jan 24 07:57:18 PM PST 24 |
Jan 24 07:57:57 PM PST 24 |
867259013 ps |
| T78 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.2088403699 |
|
|
Jan 24 09:53:07 PM PST 24 |
Jan 24 09:54:26 PM PST 24 |
3941689260 ps |
| T120 |
/workspace/coverage/default/15.sram_ctrl_executable.309365777 |
|
|
Jan 24 08:03:35 PM PST 24 |
Jan 24 08:40:18 PM PST 24 |
48131028314 ps |
| T24 |
/workspace/coverage/default/26.sram_ctrl_regwen.3649520908 |
|
|
Jan 24 08:11:15 PM PST 24 |
Jan 24 08:34:25 PM PST 24 |
15359571084 ps |
| T199 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2505952517 |
|
|
Jan 24 08:29:44 PM PST 24 |
Jan 24 08:32:28 PM PST 24 |
10338767249 ps |
| T200 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4240063201 |
|
|
Jan 24 08:43:40 PM PST 24 |
Jan 24 08:44:13 PM PST 24 |
756617926 ps |
| T201 |
/workspace/coverage/default/21.sram_ctrl_smoke.2258219632 |
|
|
Jan 24 09:03:03 PM PST 24 |
Jan 24 09:03:33 PM PST 24 |
1120416639 ps |
| T79 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2206935836 |
|
|
Jan 24 09:01:33 PM PST 24 |
Jan 24 09:18:22 PM PST 24 |
7720755304 ps |
| T202 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1295389997 |
|
|
Jan 24 08:00:10 PM PST 24 |
Jan 24 08:05:19 PM PST 24 |
3714111928 ps |
| T203 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2835884280 |
|
|
Jan 24 08:10:00 PM PST 24 |
Jan 24 08:10:32 PM PST 24 |
3071507264 ps |
| T204 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2838388013 |
|
|
Jan 24 08:10:27 PM PST 24 |
Jan 24 08:17:31 PM PST 24 |
22920800508 ps |
| T205 |
/workspace/coverage/default/40.sram_ctrl_partial_access.3081708428 |
|
|
Jan 24 09:03:03 PM PST 24 |
Jan 24 09:03:22 PM PST 24 |
1070163138 ps |
| T128 |
/workspace/coverage/default/47.sram_ctrl_executable.2413088534 |
|
|
Jan 24 08:29:34 PM PST 24 |
Jan 24 08:37:22 PM PST 24 |
26860117870 ps |
| T206 |
/workspace/coverage/default/47.sram_ctrl_bijection.1703256711 |
|
|
Jan 24 08:29:17 PM PST 24 |
Jan 24 08:57:44 PM PST 24 |
207193685042 ps |
| T126 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.669651305 |
|
|
Jan 24 08:00:10 PM PST 24 |
Jan 24 08:05:27 PM PST 24 |
20253397712 ps |
| T80 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2974726500 |
|
|
Jan 24 08:56:10 PM PST 24 |
Jan 24 08:57:26 PM PST 24 |
1986629571 ps |
| T123 |
/workspace/coverage/default/7.sram_ctrl_regwen.767211298 |
|
|
Jan 24 07:59:12 PM PST 24 |
Jan 24 08:10:11 PM PST 24 |
31531770302 ps |
| T207 |
/workspace/coverage/default/18.sram_ctrl_partial_access.3424656239 |
|
|
Jan 24 09:22:19 PM PST 24 |
Jan 24 09:23:04 PM PST 24 |
3875845470 ps |
| T208 |
/workspace/coverage/default/27.sram_ctrl_alert_test.516630123 |
|
|
Jan 24 08:47:53 PM PST 24 |
Jan 24 08:47:55 PM PST 24 |
20388126 ps |
| T209 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1615670333 |
|
|
Jan 24 08:02:33 PM PST 24 |
Jan 24 08:02:58 PM PST 24 |
348075976 ps |
| T210 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2793730052 |
|
|
Jan 24 08:19:38 PM PST 24 |
Jan 24 08:19:45 PM PST 24 |
360590016 ps |
| T211 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.159224582 |
|
|
Jan 24 08:09:27 PM PST 24 |
Jan 24 08:09:37 PM PST 24 |
366811556 ps |
| T212 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.4023139581 |
|
|
Jan 24 09:55:23 PM PST 24 |
Jan 24 10:02:34 PM PST 24 |
16422690998 ps |
| T125 |
/workspace/coverage/default/30.sram_ctrl_regwen.4049288299 |
|
|
Jan 24 08:14:57 PM PST 24 |
Jan 24 08:33:11 PM PST 24 |
52195778400 ps |
| T213 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1256811582 |
|
|
Jan 24 08:08:10 PM PST 24 |
Jan 24 08:30:06 PM PST 24 |
73692880575 ps |
| T214 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3618333585 |
|
|
Jan 24 08:23:21 PM PST 24 |
Jan 24 09:32:46 PM PST 24 |
939802235 ps |
| T215 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.2407130557 |
|
|
Jan 24 10:04:45 PM PST 24 |
Jan 24 10:04:56 PM PST 24 |
2591529319 ps |
| T216 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3130234637 |
|
|
Jan 24 08:27:20 PM PST 24 |
Jan 24 08:33:21 PM PST 24 |
4781578389 ps |
| T217 |
/workspace/coverage/default/10.sram_ctrl_smoke.2030549197 |
|
|
Jan 24 08:00:23 PM PST 24 |
Jan 24 08:01:36 PM PST 24 |
12655737685 ps |
| T218 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4017956368 |
|
|
Jan 25 12:06:10 AM PST 24 |
Jan 25 12:15:34 AM PST 24 |
33598463537 ps |
| T219 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3704621188 |
|
|
Jan 24 08:20:48 PM PST 24 |
Jan 24 08:25:17 PM PST 24 |
6643221639 ps |
| T220 |
/workspace/coverage/default/3.sram_ctrl_bijection.2481684431 |
|
|
Jan 24 07:57:36 PM PST 24 |
Jan 24 08:34:16 PM PST 24 |
101925978766 ps |
| T221 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.325702878 |
|
|
Jan 24 08:22:40 PM PST 24 |
Jan 24 08:59:38 PM PST 24 |
3067914693 ps |
| T121 |
/workspace/coverage/default/44.sram_ctrl_executable.1363268904 |
|
|
Jan 24 08:29:52 PM PST 24 |
Jan 24 08:47:54 PM PST 24 |
137324749367 ps |
| T222 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3278054374 |
|
|
Jan 24 07:57:33 PM PST 24 |
Jan 24 08:00:50 PM PST 24 |
44451626895 ps |
| T223 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3162980471 |
|
|
Jan 24 08:29:28 PM PST 24 |
Jan 24 08:31:13 PM PST 24 |
3109179210 ps |
| T224 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3042112623 |
|
|
Jan 24 08:30:30 PM PST 24 |
Jan 24 08:35:44 PM PST 24 |
172170175858 ps |
| T118 |
/workspace/coverage/default/28.sram_ctrl_regwen.3344126560 |
|
|
Jan 24 08:12:50 PM PST 24 |
Jan 24 08:22:42 PM PST 24 |
25244981684 ps |
| T225 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3294256449 |
|
|
Jan 24 08:04:17 PM PST 24 |
Jan 24 08:34:34 PM PST 24 |
1358100522 ps |
| T226 |
/workspace/coverage/default/15.sram_ctrl_bijection.4010200010 |
|
|
Jan 24 08:03:30 PM PST 24 |
Jan 24 08:28:28 PM PST 24 |
285695070539 ps |
| T227 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2727882787 |
|
|
Jan 24 08:01:47 PM PST 24 |
Jan 24 08:07:04 PM PST 24 |
68183716660 ps |
| T228 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1274970008 |
|
|
Jan 24 11:32:14 PM PST 24 |
Jan 24 11:54:32 PM PST 24 |
18199066505 ps |
| T229 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2242203626 |
|
|
Jan 24 08:05:17 PM PST 24 |
Jan 24 08:06:00 PM PST 24 |
2621452967 ps |
| T230 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.1754001776 |
|
|
Jan 24 07:58:49 PM PST 24 |
Jan 24 08:19:32 PM PST 24 |
36449718042 ps |
| T231 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.519214745 |
|
|
Jan 24 07:58:59 PM PST 24 |
Jan 24 08:44:05 PM PST 24 |
367169831 ps |
| T232 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3044653361 |
|
|
Jan 24 08:44:53 PM PST 24 |
Jan 24 08:47:10 PM PST 24 |
1613340759 ps |
| T233 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3464567163 |
|
|
Jan 24 08:03:06 PM PST 24 |
Jan 24 08:03:18 PM PST 24 |
147037216 ps |
| T234 |
/workspace/coverage/default/47.sram_ctrl_regwen.3336269888 |
|
|
Jan 24 08:49:39 PM PST 24 |
Jan 24 09:00:05 PM PST 24 |
32373407998 ps |
| T235 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.4093220853 |
|
|
Jan 24 08:53:01 PM PST 24 |
Jan 24 08:55:14 PM PST 24 |
1895383690 ps |
| T124 |
/workspace/coverage/default/7.sram_ctrl_executable.201095161 |
|
|
Jan 24 07:59:11 PM PST 24 |
Jan 24 08:04:20 PM PST 24 |
7156689764 ps |
| T119 |
/workspace/coverage/default/30.sram_ctrl_stress_all.471180571 |
|
|
Jan 24 08:15:06 PM PST 24 |
Jan 24 10:24:19 PM PST 24 |
77823986129 ps |
| T236 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1127448895 |
|
|
Jan 24 09:30:12 PM PST 24 |
Jan 24 09:30:56 PM PST 24 |
3750231541 ps |
| T237 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2528955549 |
|
|
Jan 24 08:15:31 PM PST 24 |
Jan 24 08:15:45 PM PST 24 |
1001722418 ps |
| T238 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2596856761 |
|
|
Jan 24 09:35:40 PM PST 24 |
Jan 24 09:41:05 PM PST 24 |
18857711659 ps |
| T239 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1340693564 |
|
|
Jan 24 08:25:13 PM PST 24 |
Jan 24 08:27:46 PM PST 24 |
10357246302 ps |
| T240 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.677545417 |
|
|
Jan 24 08:46:20 PM PST 24 |
Jan 24 10:10:19 PM PST 24 |
2498820427 ps |
| T241 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.424893791 |
|
|
Jan 24 07:57:15 PM PST 24 |
Jan 24 08:17:56 PM PST 24 |
39998577795 ps |
| T242 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.1980244478 |
|
|
Jan 24 08:03:32 PM PST 24 |
Jan 24 08:03:59 PM PST 24 |
2682545505 ps |
| T243 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1256129616 |
|
|
Jan 24 08:17:29 PM PST 24 |
Jan 24 08:26:01 PM PST 24 |
20700268687 ps |
| T244 |
/workspace/coverage/default/19.sram_ctrl_regwen.37469343 |
|
|
Jan 24 08:06:18 PM PST 24 |
Jan 24 08:22:24 PM PST 24 |
59846214159 ps |
| T245 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2103878738 |
|
|
Jan 24 08:02:32 PM PST 24 |
Jan 24 08:08:30 PM PST 24 |
17004412822 ps |
| T246 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1504506024 |
|
|
Jan 24 08:09:39 PM PST 24 |
Jan 24 08:12:46 PM PST 24 |
99567611390 ps |
| T247 |
/workspace/coverage/default/44.sram_ctrl_smoke.1650188641 |
|
|
Jan 24 08:26:16 PM PST 24 |
Jan 24 08:28:58 PM PST 24 |
777449885 ps |
| T248 |
/workspace/coverage/default/13.sram_ctrl_bijection.2607081619 |
|
|
Jan 24 09:37:15 PM PST 24 |
Jan 24 09:51:42 PM PST 24 |
63871092623 ps |
| T8 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.157733777 |
|
|
Jan 24 08:14:48 PM PST 24 |
Jan 24 08:20:05 PM PST 24 |
54369611954 ps |
| T249 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.247350872 |
|
|
Jan 24 08:11:49 PM PST 24 |
Jan 24 08:13:24 PM PST 24 |
785461429 ps |
| T250 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2541160080 |
|
|
Jan 24 08:01:11 PM PST 24 |
Jan 24 08:02:30 PM PST 24 |
3097476009 ps |
| T251 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.459370248 |
|
|
Jan 24 08:29:14 PM PST 24 |
Jan 24 08:43:04 PM PST 24 |
18967711408 ps |
| T252 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.387405014 |
|
|
Jan 24 08:16:35 PM PST 24 |
Jan 24 08:17:04 PM PST 24 |
2602613052 ps |
| T253 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2304042346 |
|
|
Jan 24 07:59:50 PM PST 24 |
Jan 24 08:02:22 PM PST 24 |
5318563871 ps |
| T254 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2861365425 |
|
|
Jan 24 11:50:34 PM PST 24 |
Jan 24 11:54:35 PM PST 24 |
2792798255 ps |
| T255 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2692945541 |
|
|
Jan 24 08:06:18 PM PST 24 |
Jan 24 08:06:53 PM PST 24 |
681723684 ps |
| T256 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.391568981 |
|
|
Jan 24 08:02:57 PM PST 24 |
Jan 24 08:13:43 PM PST 24 |
109114937964 ps |
| T257 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.3001075547 |
|
|
Jan 24 08:01:33 PM PST 24 |
Jan 24 08:07:45 PM PST 24 |
11564175928 ps |
| T258 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1147716329 |
|
|
Jan 24 08:03:46 PM PST 24 |
Jan 24 08:03:55 PM PST 24 |
344076610 ps |
| T259 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1644675861 |
|
|
Jan 24 08:04:53 PM PST 24 |
Jan 24 09:34:41 PM PST 24 |
1514674467 ps |
| T260 |
/workspace/coverage/default/35.sram_ctrl_bijection.679088121 |
|
|
Jan 24 08:19:04 PM PST 24 |
Jan 24 08:47:07 PM PST 24 |
107720952866 ps |
| T116 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3630090928 |
|
|
Jan 24 08:10:13 PM PST 24 |
Jan 24 08:11:06 PM PST 24 |
5870959483 ps |
| T261 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.155425459 |
|
|
Jan 24 08:03:44 PM PST 24 |
Jan 24 08:08:58 PM PST 24 |
121506023274 ps |