Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	129064246	1			T2	44474		T3	53774		T4	3237
triple_byte_access	2628672	1			T2	875		T3	1035		T4	7305
halfword_access	4039774	1			T2	1254		T3	1701		T4	13752
byte_access	5673805	1			T2	1752		T3	2133		T4	25641
zero_access	1736109	1			T2	455		T3	571		T4	15188

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71061784

1

T2

24426

T3

29782

T4

32505

auto[1]

72080822

1

T2

24384

T3

29432

T4

32618

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	63912813	1			T2	22216		T3	27037		T4	300
auto[0]	triple_byte_access	1244096	1			T2	445		T3	506		T4	1383
auto[0]	halfword_access	1962251	1			T2	619		T3	846		T4	4787
auto[0]	byte_access	2899566	1			T2	907		T3	1087		T4	13825
auto[0]	zero_access	1043058	1			T2	239		T3	306		T4	12210
auto[1]	word_access	65151433	1			T2	22258		T3	26737		T4	2937
auto[1]	triple_byte_access	1384576	1			T2	430		T3	529		T4	5922
auto[1]	halfword_access	2077523	1			T2	635		T3	855		T4	8965
auto[1]	byte_access	2774239	1			T2	845		T3	1046		T4	11816
auto[1]	zero_access	693051	1			T2	216		T3	265		T4	2978