Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	275276949	1			T2	196606		T3	331848		T4	65134
instr_valid_dis	250360030	1			T2	196606		T3	331848		T4	65134
instr_en	15457133	1			T11	314276		T29	342648		T48	32

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	8833801	1			T11	55196		T29	97578		T111	189780
sram_ifetch_valid_disable	252616790	1			T2	196606		T3	331848		T4	65134
sram_ifetch_enable	13826358	1			T11	112304		T13	90408		T29	88626

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	275276949	1			T2	196606		T3	331848		T4	65134
hw_debug_en_valid_off	251671431	1			T2	196606		T3	331848		T4	65134
hw_debug_en_on	12469661	1			T11	49032		T13	164604		T14	8769

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	252616790	1			T2	196606		T3	331848		T4	65134
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	244257535	1			T2	196606		T3	331848		T4	65134
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	5563967	1			T11	146776		T29	159658		T48	32
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	2690103	1			T11	55196		T29	23276		T111	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	683867	1			T9	2090		T110	38772		T30	9590
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1435384	1			T11	55196		T29	20062		T111	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2132774	1			T29	18430		T111	127020		T9	79262
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	878700	1			T111	6982		T9	40046		T110	31982
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	805856	1			T29	18430		T111	120038		T9	39216
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	5017123	1			T11	49032		T13	74196		T14	8769
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	1908819	1			T13	74196		T14	8769		T9	7920
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2152162	1			T11	49032		T29	51912		T111	37732

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7126976	1			T11	112304		T29	88626		T111	151364
lc_exec_en	5319764	1			T13	90408		T29	23376		T111	96358
valid_exec_dis	249195976	1			T2	196606		T3	331848		T4	65134
invalid_exec_dis	22660159	1			T11	167500		T13	90408		T29	186204