| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.427437038 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.483266317 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.723208810 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1835045897 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3718421176 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3934848683 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2051705445 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3291282430 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1762064860 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1282937260 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1548447709 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2430196783 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2429447001 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.600784134 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2893570015 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3913278675 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3224944129 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3282895058 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2682472515 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3911109859 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2611384084 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.736680091 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.191574591 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2863892446 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1314040601 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3039454221 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.44996151 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2931300886 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2971623123 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2540759552 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.534289162 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.404190477 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1136502780 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2798024955 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4109201921 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3612398253 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3299131616 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.178960452 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.443716123 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2668028402 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2820338650 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2503278933 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.247270286 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.28042918 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3986050101 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2002340588 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4083361625 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4245984842 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1545204065 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1459485307 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2808754832 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2483381366 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.581255398 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1323271611 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1532819301 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1733419807 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1099006106 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.869764765 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2827008975 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1672576670 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.531428043 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4047192537 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.417519024 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3384975262 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2848897817 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3407010595 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3897526254 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1877517147 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1877731625 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2126503667 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1463127230 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2344347059 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3101202836 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.465883545 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.332868579 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1992040005 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3980008635 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.254082874 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1942210177 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1334683156 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1054562731 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1548934415 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2821258124 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3614353970 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2356252263 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1883683610 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2829429955 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4274797773 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1462512314 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1719798199 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4040691244 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.498686010 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1080176650 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4123829280 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3623445097 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3839365158 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1496995083 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.641340830 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4038880569 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2795695637 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2802270510 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1017299869 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2521750225 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2905454051 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4118118040 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1368019592 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2740909508 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3102436594 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1911292487 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.628380330 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.2940833923 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1886692473 |
| /workspace/coverage/default/0.sram_ctrl_executable.3518053182 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.1121346064 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.3765963451 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2367950569 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.3352023543 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.1111388299 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2860014765 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.138663647 |
| /workspace/coverage/default/0.sram_ctrl_regwen.4226190436 |
| /workspace/coverage/default/0.sram_ctrl_smoke.664728694 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.329162080 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4125929680 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2085028454 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.4178445797 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.1506351173 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3139112883 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.2617298419 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.3363278447 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1114494997 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.1326978673 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2876665349 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.391905593 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3854621600 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.1748175860 |
| /workspace/coverage/default/1.sram_ctrl_regwen.1670845911 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.1605575274 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3849676024 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.807021503 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.4181123166 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1217747081 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1518706131 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.112533200 |
| /workspace/coverage/default/10.sram_ctrl_bijection.597412405 |
| /workspace/coverage/default/10.sram_ctrl_executable.3797429312 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.3789019651 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.2428652796 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2507063383 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3441318741 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1093412338 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2737856911 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1075256812 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3090424945 |
| /workspace/coverage/default/10.sram_ctrl_regwen.3997675475 |
| /workspace/coverage/default/10.sram_ctrl_smoke.4020580601 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1877508910 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1525466579 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2665600910 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2442081067 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2094926863 |
| /workspace/coverage/default/11.sram_ctrl_bijection.2423081763 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.2933704077 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2867283554 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2821829838 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.1394065162 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1187723559 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3696241638 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1736104007 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.1040396604 |
| /workspace/coverage/default/11.sram_ctrl_regwen.3804507974 |
| /workspace/coverage/default/11.sram_ctrl_smoke.634699770 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3769159961 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.4070156516 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4182915601 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.193379389 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.2058205494 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2248745043 |
| /workspace/coverage/default/12.sram_ctrl_executable.503771450 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.504136175 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.2821169008 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3080166816 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.3869050201 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.2700648115 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.2779386858 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3103585498 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.321557261 |
| /workspace/coverage/default/12.sram_ctrl_regwen.866455588 |
| /workspace/coverage/default/12.sram_ctrl_smoke.3319083494 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1126641717 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.23185786 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3292934281 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.416556895 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1757271705 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3258033371 |
| /workspace/coverage/default/13.sram_ctrl_bijection.4176945263 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.1064227965 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.94208227 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.859121990 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3017845977 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.2287712909 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.4215245060 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1773527033 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.2273169958 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2056945117 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1119801543 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.708252776 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.569488262 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2859225892 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1735102189 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1455165863 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2106281817 |
| /workspace/coverage/default/14.sram_ctrl_executable.3635057618 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.4021289818 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.686692701 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.512414411 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3024569879 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.4028834467 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.764130860 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.604658624 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.721019324 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1174186850 |
| /workspace/coverage/default/14.sram_ctrl_smoke.1589405847 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1995770090 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1439033583 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2201374459 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2706474671 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.2851761882 |
| /workspace/coverage/default/15.sram_ctrl_bijection.2131805633 |
| /workspace/coverage/default/15.sram_ctrl_executable.3094992380 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.1834621095 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.2208442884 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2126712602 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.99055028 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.1332455681 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.472421528 |
| /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3008924964 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.2979604956 |
| /workspace/coverage/default/15.sram_ctrl_regwen.546203270 |
| /workspace/coverage/default/15.sram_ctrl_smoke.1247744065 |
| /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1489682041 |
| /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1028270873 |
| /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.3268347248 |
| /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2025840415 |
| /workspace/coverage/default/16.sram_ctrl_alert_test.409331764 |
| /workspace/coverage/default/16.sram_ctrl_bijection.752433710 |
| /workspace/coverage/default/16.sram_ctrl_lc_escalation.4275462313 |
| /workspace/coverage/default/16.sram_ctrl_max_throughput.2754581653 |
| /workspace/coverage/default/16.sram_ctrl_mem_partial_access.438836086 |
| /workspace/coverage/default/16.sram_ctrl_mem_walk.1217231193 |
| /workspace/coverage/default/16.sram_ctrl_multiple_keys.2689850069 |
| /workspace/coverage/default/16.sram_ctrl_partial_access.1112472794 |
| /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1700176606 |
| /workspace/coverage/default/16.sram_ctrl_ram_cfg.380779613 |
| /workspace/coverage/default/16.sram_ctrl_regwen.1342064813 |
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| /workspace/coverage/default/46.sram_ctrl_multiple_keys.2132228292 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.3686169674 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3566209595 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.3326505400 |
| /workspace/coverage/default/46.sram_ctrl_regwen.1964907216 |
| /workspace/coverage/default/46.sram_ctrl_smoke.1213191698 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.409445362 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.417529713 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2002680499 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1997320309 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.1924948666 |
| /workspace/coverage/default/47.sram_ctrl_bijection.921599145 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.4181627893 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.1689395776 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2059254651 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2034483353 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.48021149 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2043923139 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1673598537 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.1400980441 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3848510644 |
| /workspace/coverage/default/47.sram_ctrl_smoke.2447719751 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3318352598 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3739886866 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2152429956 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3297693473 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.566922763 |
| /workspace/coverage/default/48.sram_ctrl_bijection.232470954 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1332930258 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2812235756 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.2058491441 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.1460157238 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.2879464464 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3973178012 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.230799902 |
| /workspace/coverage/default/48.sram_ctrl_regwen.3173559945 |
| /workspace/coverage/default/48.sram_ctrl_smoke.2626377467 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.581577037 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3454287519 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3117336227 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2118542023 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3348036470 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.3295744425 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1719797438 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.133016227 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2784010809 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1503163966 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.3999534560 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.2624597105 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.581286785 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.550235957 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.23506793 |
| /workspace/coverage/default/49.sram_ctrl_regwen.2356306727 |
| /workspace/coverage/default/49.sram_ctrl_smoke.4151635834 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3384874859 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3875832634 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3599540052 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2117943667 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.1007354512 |
| /workspace/coverage/default/5.sram_ctrl_bijection.4103905694 |
| /workspace/coverage/default/5.sram_ctrl_executable.4070886369 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.1049241239 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2671296235 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3781855451 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.3468557173 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2501398507 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.3078428594 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1725109260 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.3912966358 |
| /workspace/coverage/default/5.sram_ctrl_smoke.427696548 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.312467357 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2995700895 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2488673269 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1927210523 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.4098932519 |
| /workspace/coverage/default/6.sram_ctrl_bijection.3272772777 |
| /workspace/coverage/default/6.sram_ctrl_executable.2930094081 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2231385158 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.4205119537 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3525066992 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.528387273 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.2310684221 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.640898989 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2880186053 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.1035185668 |
| /workspace/coverage/default/6.sram_ctrl_regwen.2525987879 |
| /workspace/coverage/default/6.sram_ctrl_smoke.3319894906 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.1609340902 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1467636048 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2518723519 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.573945079 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1991737674 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.987966289 |
| /workspace/coverage/default/7.sram_ctrl_bijection.462789560 |
| /workspace/coverage/default/7.sram_ctrl_executable.853644535 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.4232939646 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3699990784 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2167780633 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3572561126 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.17973328 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.4135134651 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.166227131 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.1845375116 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3614084840 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1698058406 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2225506283 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3948083205 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1042592596 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1005759411 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.675177280 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.961474785 |
| /workspace/coverage/default/8.sram_ctrl_bijection.761367203 |
| /workspace/coverage/default/8.sram_ctrl_executable.2641558203 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.2943560932 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.3191524393 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3933097057 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.2332952830 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2806981395 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3783085056 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2818880205 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3440884057 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2411767446 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3745721393 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3293593292 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.422149641 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4131994308 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.33424035 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1015954707 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3271911333 |
| /workspace/coverage/default/9.sram_ctrl_executable.779794020 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.843785881 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.997161763 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2810054238 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.1079065408 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.1371708446 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.2092174960 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.918511736 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2627770422 |
| /workspace/coverage/default/9.sram_ctrl_regwen.3646477113 |
| /workspace/coverage/default/9.sram_ctrl_smoke.29441106 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.375366738 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.735433310 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.907140212 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1007354512 |
|
|
Feb 04 01:38:37 PM PST 24 |
Feb 04 01:38:38 PM PST 24 |
55037486 ps |
| T2 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2129982601 |
|
|
Feb 04 01:43:50 PM PST 24 |
Feb 04 01:46:24 PM PST 24 |
41255720328 ps |
| T3 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.759698803 |
|
|
Feb 04 01:48:50 PM PST 24 |
Feb 04 02:05:44 PM PST 24 |
36735604205 ps |
| T4 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2812235756 |
|
|
Feb 04 01:52:48 PM PST 24 |
Feb 04 01:54:11 PM PST 24 |
4712259534 ps |
| T6 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.1336778827 |
|
|
Feb 04 01:49:44 PM PST 24 |
Feb 04 01:50:53 PM PST 24 |
1493885405 ps |
| T10 |
/workspace/coverage/default/26.sram_ctrl_alert_test.4021198808 |
|
|
Feb 04 01:45:45 PM PST 24 |
Feb 04 01:45:47 PM PST 24 |
23888797 ps |
| T5 |
/workspace/coverage/default/38.sram_ctrl_smoke.1284496424 |
|
|
Feb 04 01:49:03 PM PST 24 |
Feb 04 01:49:22 PM PST 24 |
2034312263 ps |
| T11 |
/workspace/coverage/default/36.sram_ctrl_regwen.3385551744 |
|
|
Feb 04 01:48:43 PM PST 24 |
Feb 04 02:07:28 PM PST 24 |
72178701831 ps |
| T12 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.1327232805 |
|
|
Feb 04 01:50:24 PM PST 24 |
Feb 04 01:57:01 PM PST 24 |
19813929153 ps |
| T13 |
/workspace/coverage/default/39.sram_ctrl_regwen.3045554936 |
|
|
Feb 04 01:49:44 PM PST 24 |
Feb 04 02:02:01 PM PST 24 |
45092352234 ps |
| T22 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2376679433 |
|
|
Feb 04 01:48:10 PM PST 24 |
Feb 04 01:48:25 PM PST 24 |
355363057 ps |
| T18 |
/workspace/coverage/default/16.sram_ctrl_smoke.2149979624 |
|
|
Feb 04 01:42:20 PM PST 24 |
Feb 04 01:42:30 PM PST 24 |
433486545 ps |
| T19 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.539978756 |
|
|
Feb 04 01:51:15 PM PST 24 |
Feb 04 01:53:38 PM PST 24 |
7179957296 ps |
| T20 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1599564322 |
|
|
Feb 04 01:50:08 PM PST 24 |
Feb 04 01:53:29 PM PST 24 |
6571275555 ps |
| T14 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1043032795 |
|
|
Feb 04 01:44:47 PM PST 24 |
Feb 04 03:06:21 PM PST 24 |
11753861046 ps |
| T31 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2605705101 |
|
|
Feb 04 01:42:57 PM PST 24 |
Feb 04 01:42:59 PM PST 24 |
53413526 ps |
| T21 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.716648211 |
|
|
Feb 04 01:45:22 PM PST 24 |
Feb 04 01:52:19 PM PST 24 |
30214569142 ps |
| T17 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2859225892 |
|
|
Feb 04 01:41:35 PM PST 24 |
Feb 04 01:46:24 PM PST 24 |
7386727277 ps |
| T23 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1790349663 |
|
|
Feb 04 01:42:57 PM PST 24 |
Feb 04 01:50:35 PM PST 24 |
61935999609 ps |
| T15 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.787443080 |
|
|
Feb 04 01:48:15 PM PST 24 |
Feb 04 01:56:35 PM PST 24 |
212804435079 ps |
| T34 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2107596112 |
|
|
Feb 04 01:46:58 PM PST 24 |
Feb 04 02:28:43 PM PST 24 |
1077185705 ps |
| T59 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3143898493 |
|
|
Feb 04 01:44:57 PM PST 24 |
Feb 04 01:45:31 PM PST 24 |
2556113505 ps |
| T60 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2739803632 |
|
|
Feb 04 01:42:56 PM PST 24 |
Feb 04 01:44:23 PM PST 24 |
1508619276 ps |
| T16 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2982076342 |
|
|
Feb 04 01:49:44 PM PST 24 |
Feb 04 01:55:13 PM PST 24 |
178339549477 ps |
| T117 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2784010809 |
|
|
Feb 04 01:53:01 PM PST 24 |
Feb 04 01:53:38 PM PST 24 |
4892829441 ps |
| T7 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.527158619 |
|
|
Feb 04 01:44:36 PM PST 24 |
Feb 04 01:45:03 PM PST 24 |
9968422599 ps |
| T118 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3999534560 |
|
|
Feb 04 01:53:11 PM PST 24 |
Feb 04 01:57:20 PM PST 24 |
4333383041 ps |
| T119 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.1114043691 |
|
|
Feb 04 01:49:57 PM PST 24 |
Feb 04 01:55:29 PM PST 24 |
42175830090 ps |
| T36 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.23506793 |
|
|
Feb 04 01:53:00 PM PST 24 |
Feb 04 01:53:20 PM PST 24 |
703134711 ps |
| T120 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2867283554 |
|
|
Feb 04 01:41:08 PM PST 24 |
Feb 04 01:42:01 PM PST 24 |
750450777 ps |
| T37 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2528513322 |
|
|
Feb 04 01:47:40 PM PST 24 |
Feb 04 01:47:46 PM PST 24 |
1680154160 ps |
| T24 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.4244938574 |
|
|
Feb 04 01:43:25 PM PST 24 |
Feb 04 01:51:06 PM PST 24 |
4973431708 ps |
| T29 |
/workspace/coverage/default/31.sram_ctrl_regwen.2899010300 |
|
|
Feb 04 01:46:58 PM PST 24 |
Feb 04 02:03:41 PM PST 24 |
15396172895 ps |
| T67 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3658862822 |
|
|
Feb 04 01:47:56 PM PST 24 |
Feb 04 01:54:43 PM PST 24 |
32837256879 ps |
| T121 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.972438284 |
|
|
Feb 04 01:45:46 PM PST 24 |
Feb 04 01:46:20 PM PST 24 |
2845927721 ps |
| T89 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.4088973706 |
|
|
Feb 04 01:45:23 PM PST 24 |
Feb 04 01:48:49 PM PST 24 |
2972988836 ps |
| T122 |
/workspace/coverage/default/19.sram_ctrl_bijection.1415089661 |
|
|
Feb 04 01:42:57 PM PST 24 |
Feb 04 01:52:38 PM PST 24 |
49556443941 ps |
| T123 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2521951018 |
|
|
Feb 04 01:43:44 PM PST 24 |
Feb 04 01:43:46 PM PST 24 |
21989710 ps |
| T35 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.329162080 |
|
|
Feb 04 01:36:52 PM PST 24 |
Feb 04 02:41:11 PM PST 24 |
1361633723 ps |
| T124 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3504966315 |
|
|
Feb 04 01:37:32 PM PST 24 |
Feb 04 01:44:23 PM PST 24 |
24477935794 ps |
| T125 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1271874971 |
|
|
Feb 04 01:49:33 PM PST 24 |
Feb 04 01:54:02 PM PST 24 |
17396528787 ps |
| T126 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1861078144 |
|
|
Feb 04 01:46:42 PM PST 24 |
Feb 04 01:47:21 PM PST 24 |
732411042 ps |
| T127 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.230799902 |
|
|
Feb 04 01:52:39 PM PST 24 |
Feb 04 01:52:53 PM PST 24 |
362904981 ps |
| T128 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1559165385 |
|
|
Feb 04 01:48:46 PM PST 24 |
Feb 04 01:52:12 PM PST 24 |
16582861183 ps |
| T68 |
/workspace/coverage/default/15.sram_ctrl_smoke.1247744065 |
|
|
Feb 04 01:42:13 PM PST 24 |
Feb 04 01:43:52 PM PST 24 |
423723969 ps |
| T50 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3534508987 |
|
|
Feb 04 01:50:28 PM PST 24 |
Feb 04 02:33:40 PM PST 24 |
1818375679 ps |
| T129 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3026841780 |
|
|
Feb 04 01:44:48 PM PST 24 |
Feb 04 01:44:57 PM PST 24 |
1346953267 ps |
| T130 |
/workspace/coverage/default/37.sram_ctrl_bijection.253313230 |
|
|
Feb 04 01:48:57 PM PST 24 |
Feb 04 02:10:14 PM PST 24 |
79206981361 ps |
| T75 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.512414411 |
|
|
Feb 04 01:42:12 PM PST 24 |
Feb 04 01:43:35 PM PST 24 |
9704123916 ps |
| T131 |
/workspace/coverage/default/40.sram_ctrl_smoke.3986432030 |
|
|
Feb 04 01:49:48 PM PST 24 |
Feb 04 01:50:28 PM PST 24 |
703529696 ps |
| T132 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.997161763 |
|
|
Feb 04 01:40:30 PM PST 24 |
Feb 04 01:41:43 PM PST 24 |
1517112071 ps |
| T133 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1040396604 |
|
|
Feb 04 01:41:08 PM PST 24 |
Feb 04 01:41:23 PM PST 24 |
373484502 ps |
| T61 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4109201921 |
|
|
Feb 04 12:35:59 PM PST 24 |
Feb 04 12:36:07 PM PST 24 |
100054396 ps |
| T62 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.718036066 |
|
|
Feb 04 12:36:06 PM PST 24 |
Feb 04 12:36:13 PM PST 24 |
12851486 ps |
| T51 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4274797773 |
|
|
Feb 04 12:35:28 PM PST 24 |
Feb 04 12:35:39 PM PST 24 |
134451061 ps |
| T52 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2503278933 |
|
|
Feb 04 12:35:46 PM PST 24 |
Feb 04 12:36:00 PM PST 24 |
2454713531 ps |
| T53 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2356252263 |
|
|
Feb 04 12:35:27 PM PST 24 |
Feb 04 12:35:39 PM PST 24 |
832689922 ps |
| T54 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3101202836 |
|
|
Feb 04 12:35:29 PM PST 24 |
Feb 04 12:35:49 PM PST 24 |
705524806 ps |
| T88 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2682472515 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:03 PM PST 24 |
18831319 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2344347059 |
|
|
Feb 04 12:35:36 PM PST 24 |
Feb 04 12:35:45 PM PST 24 |
15200926 ps |
| T63 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.581255398 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:01 PM PST 24 |
14976735 ps |
| T64 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.44996151 |
|
|
Feb 04 12:35:59 PM PST 24 |
Feb 04 12:36:07 PM PST 24 |
39794412 ps |
| T55 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2051705445 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:45 PM PST 24 |
28008589 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1496995083 |
|
|
Feb 04 12:35:51 PM PST 24 |
Feb 04 12:35:59 PM PST 24 |
37801316 ps |
| T56 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1136502780 |
|
|
Feb 04 12:35:58 PM PST 24 |
Feb 04 12:36:08 PM PST 24 |
93185096 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3897526254 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
47497149 ps |
| T57 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3986050101 |
|
|
Feb 04 12:35:45 PM PST 24 |
Feb 04 12:35:53 PM PST 24 |
75190700 ps |
| T47 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3824952788 |
|
|
Feb 04 12:35:32 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
146002196 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1548934415 |
|
|
Feb 04 12:35:25 PM PST 24 |
Feb 04 12:35:34 PM PST 24 |
19278530 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1762064860 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
20995462 ps |
| T48 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3291282430 |
|
|
Feb 04 12:35:31 PM PST 24 |
Feb 04 12:35:40 PM PST 24 |
290480001 ps |
| T73 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3039454221 |
|
|
Feb 04 12:35:57 PM PST 24 |
Feb 04 12:36:10 PM PST 24 |
350195734 ps |
| T49 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1462512314 |
|
|
Feb 04 12:35:32 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
353084598 ps |
| T58 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.641340830 |
|
|
Feb 04 12:35:41 PM PST 24 |
Feb 04 12:35:49 PM PST 24 |
71825493 ps |
| T74 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2802270510 |
|
|
Feb 04 12:35:52 PM PST 24 |
Feb 04 12:35:59 PM PST 24 |
14200596 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3718421176 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
56655403 ps |
| T72 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3612398253 |
|
|
Feb 04 12:35:51 PM PST 24 |
Feb 04 12:35:59 PM PST 24 |
23822280 ps |
| T87 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3282895058 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:01 PM PST 24 |
15574899 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3299131616 |
|
|
Feb 04 12:35:51 PM PST 24 |
Feb 04 12:36:00 PM PST 24 |
61693692 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1314040601 |
|
|
Feb 04 12:35:50 PM PST 24 |
Feb 04 12:36:00 PM PST 24 |
745920417 ps |
| T134 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.443716123 |
|
|
Feb 04 12:35:45 PM PST 24 |
Feb 04 12:35:52 PM PST 24 |
14626198 ps |
| T90 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.28042918 |
|
|
Feb 04 12:35:44 PM PST 24 |
Feb 04 12:35:51 PM PST 24 |
58790623 ps |
| T96 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1955041107 |
|
|
Feb 04 12:36:06 PM PST 24 |
Feb 04 12:36:15 PM PST 24 |
316585283 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.417519024 |
|
|
Feb 04 12:35:36 PM PST 24 |
Feb 04 12:35:46 PM PST 24 |
68027272 ps |
| T136 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4245984842 |
|
|
Feb 04 12:35:48 PM PST 24 |
Feb 04 12:35:57 PM PST 24 |
27433401 ps |
| T104 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.777900393 |
|
|
Feb 04 12:35:59 PM PST 24 |
Feb 04 12:36:08 PM PST 24 |
910118770 ps |
| T137 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1282937260 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:45 PM PST 24 |
27733173 ps |
| T91 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3934848683 |
|
|
Feb 04 12:35:33 PM PST 24 |
Feb 04 12:35:42 PM PST 24 |
15826899 ps |
| T138 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3224944129 |
|
|
Feb 04 12:35:57 PM PST 24 |
Feb 04 12:36:10 PM PST 24 |
684222386 ps |
| T139 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2740909508 |
|
|
Feb 04 12:35:44 PM PST 24 |
Feb 04 12:35:50 PM PST 24 |
217163633 ps |
| T140 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1835045897 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:57 PM PST 24 |
365520656 ps |
| T141 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1054562731 |
|
|
Feb 04 12:35:32 PM PST 24 |
Feb 04 12:35:46 PM PST 24 |
3134538085 ps |
| T142 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1532819301 |
|
|
Feb 04 12:35:53 PM PST 24 |
Feb 04 12:36:01 PM PST 24 |
63614700 ps |
| T76 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1334683156 |
|
|
Feb 04 12:35:32 PM PST 24 |
Feb 04 12:35:42 PM PST 24 |
17896753 ps |
| T143 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2827008975 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:04 PM PST 24 |
66846231 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3980008635 |
|
|
Feb 04 12:35:32 PM PST 24 |
Feb 04 12:35:44 PM PST 24 |
660682019 ps |
| T144 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.723208810 |
|
|
Feb 04 12:35:27 PM PST 24 |
Feb 04 12:35:35 PM PST 24 |
69149267 ps |
| T105 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1877731625 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:46 PM PST 24 |
1009809253 ps |
| T145 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1942210177 |
|
|
Feb 04 12:35:29 PM PST 24 |
Feb 04 12:35:39 PM PST 24 |
29680229 ps |
| T146 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4047192537 |
|
|
Feb 04 12:35:31 PM PST 24 |
Feb 04 12:35:41 PM PST 24 |
17919166 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.427437038 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:45 PM PST 24 |
18188428 ps |
| T147 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2971623123 |
|
|
Feb 04 12:35:58 PM PST 24 |
Feb 04 12:36:07 PM PST 24 |
39655916 ps |
| T148 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2829429955 |
|
|
Feb 04 12:35:28 PM PST 24 |
Feb 04 12:35:35 PM PST 24 |
109144087 ps |
| T97 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4123829280 |
|
|
Feb 04 12:35:45 PM PST 24 |
Feb 04 12:35:55 PM PST 24 |
146522173 ps |
| T149 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.483266317 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:44 PM PST 24 |
779082631 ps |
| T150 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2795695637 |
|
|
Feb 04 12:35:53 PM PST 24 |
Feb 04 12:36:13 PM PST 24 |
541461609 ps |
| T151 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.534289162 |
|
|
Feb 04 12:35:51 PM PST 24 |
Feb 04 12:35:59 PM PST 24 |
14090286 ps |
| T101 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2111253216 |
|
|
Feb 04 12:35:46 PM PST 24 |
Feb 04 12:35:58 PM PST 24 |
166557025 ps |
| T152 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3407010595 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
36244871 ps |
| T153 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2893570015 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:47 PM PST 24 |
623984667 ps |
| T154 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1080176650 |
|
|
Feb 04 12:35:45 PM PST 24 |
Feb 04 12:35:57 PM PST 24 |
118647567 ps |
| T78 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4040691244 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:01 PM PST 24 |
49286307 ps |
| T155 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2483381366 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:08 PM PST 24 |
3731154325 ps |
| T156 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.498686010 |
|
|
Feb 04 12:35:48 PM PST 24 |
Feb 04 12:35:57 PM PST 24 |
21360138 ps |
| T157 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1883683610 |
|
|
Feb 04 12:35:29 PM PST 24 |
Feb 04 12:35:37 PM PST 24 |
102153342 ps |
| T158 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1017299869 |
|
|
Feb 04 12:35:43 PM PST 24 |
Feb 04 12:35:50 PM PST 24 |
32150578 ps |
| T159 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2611384084 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:05 PM PST 24 |
136779771 ps |
| T102 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1733419807 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:02 PM PST 24 |
248886057 ps |
| T103 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2002340588 |
|
|
Feb 04 12:35:44 PM PST 24 |
Feb 04 12:35:53 PM PST 24 |
495496819 ps |
| T160 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.465883545 |
|
|
Feb 04 12:35:36 PM PST 24 |
Feb 04 12:35:46 PM PST 24 |
22476392 ps |
| T161 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2430196783 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:48 PM PST 24 |
352351470 ps |
| T162 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3839365158 |
|
|
Feb 04 12:35:46 PM PST 24 |
Feb 04 12:35:56 PM PST 24 |
18966580 ps |
| T163 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2848897817 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:58 PM PST 24 |
4975863496 ps |
| T164 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1992040005 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:47 PM PST 24 |
158051406 ps |
| T165 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.178960452 |
|
|
Feb 04 12:35:46 PM PST 24 |
Feb 04 12:36:01 PM PST 24 |
356702602 ps |
| T166 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1548447709 |
|
|
Feb 04 12:35:31 PM PST 24 |
Feb 04 12:35:39 PM PST 24 |
16673182 ps |
| T167 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2798024955 |
|
|
Feb 04 12:35:51 PM PST 24 |
Feb 04 12:36:03 PM PST 24 |
733830759 ps |
| T168 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.600784134 |
|
|
Feb 04 12:35:35 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
67934249 ps |
| T169 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3614353970 |
|
|
Feb 04 12:35:25 PM PST 24 |
Feb 04 12:35:38 PM PST 24 |
150968953 ps |
| T170 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.254082874 |
|
|
Feb 04 12:35:33 PM PST 24 |
Feb 04 12:35:42 PM PST 24 |
97128982 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2905454051 |
|
|
Feb 04 12:35:49 PM PST 24 |
Feb 04 12:35:59 PM PST 24 |
264348020 ps |
| T171 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2821258124 |
|
|
Feb 04 12:35:27 PM PST 24 |
Feb 04 12:35:34 PM PST 24 |
16049490 ps |
| T172 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3911109859 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:07 PM PST 24 |
255586698 ps |
| T173 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3623445097 |
|
|
Feb 04 12:35:49 PM PST 24 |
Feb 04 12:36:10 PM PST 24 |
347735008 ps |
| T174 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2863892446 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:03 PM PST 24 |
30115062 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2126503667 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
29300637 ps |
| T175 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1323271611 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:05 PM PST 24 |
14523684 ps |
| T176 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.736680091 |
|
|
Feb 04 12:35:58 PM PST 24 |
Feb 04 12:36:11 PM PST 24 |
1373759358 ps |
| T177 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1099006106 |
|
|
Feb 04 12:36:06 PM PST 24 |
Feb 04 12:36:18 PM PST 24 |
1392238326 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3913278675 |
|
|
Feb 04 12:35:30 PM PST 24 |
Feb 04 12:35:40 PM PST 24 |
1591800572 ps |
| T86 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1368019592 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:00 PM PST 24 |
21546603 ps |
| T178 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1672576670 |
|
|
Feb 04 12:35:55 PM PST 24 |
Feb 04 12:36:05 PM PST 24 |
1206735859 ps |
| T179 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1459485307 |
|
|
Feb 04 12:35:53 PM PST 24 |
Feb 04 12:36:02 PM PST 24 |
449778476 ps |
| T180 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4038880569 |
|
|
Feb 04 12:35:43 PM PST 24 |
Feb 04 12:35:51 PM PST 24 |
943615442 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3384975262 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
46229660 ps |
| T181 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.869764765 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:04 PM PST 24 |
18003252 ps |
| T182 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2429447001 |
|
|
Feb 04 12:35:34 PM PST 24 |
Feb 04 12:35:43 PM PST 24 |
105701111 ps |
| T183 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2540759552 |
|
|
Feb 04 12:35:57 PM PST 24 |
Feb 04 12:36:17 PM PST 24 |
1222251754 ps |
| T184 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.332868579 |
|
|
Feb 04 12:35:32 PM PST 24 |
Feb 04 12:35:42 PM PST 24 |
34222772 ps |
| T185 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1719798199 |
|
|
Feb 04 12:35:45 PM PST 24 |
Feb 04 12:36:05 PM PST 24 |
421381978 ps |
| T186 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1545204065 |
|
|
Feb 04 12:35:45 PM PST 24 |
Feb 04 12:35:54 PM PST 24 |
26137360 ps |
| T187 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.404190477 |
|
|
Feb 04 12:35:59 PM PST 24 |
Feb 04 12:36:08 PM PST 24 |
88412631 ps |
| T188 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4118118040 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:13 PM PST 24 |
362981458 ps |
| T189 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2820338650 |
|
|
Feb 04 12:35:51 PM PST 24 |
Feb 04 12:36:01 PM PST 24 |
128302973 ps |
| T190 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.191574591 |
|
|
Feb 04 12:35:56 PM PST 24 |
Feb 04 12:36:03 PM PST 24 |
19010273 ps |
| T191 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2808754832 |
|
|
Feb 04 12:35:44 PM PST 24 |
Feb 04 12:35:52 PM PST 24 |
413750208 ps |
| T192 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2668028402 |
|
|
Feb 04 12:35:44 PM PST 24 |
Feb 04 12:35:50 PM PST 24 |
87536582 ps |
| T193 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1911292487 |
|
|
Feb 04 12:35:46 PM PST 24 |
Feb 04 12:35:56 PM PST 24 |
939433007 ps |
| T194 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.531428043 |
|
|
Feb 04 12:36:06 PM PST 24 |
Feb 04 12:36:15 PM PST 24 |
218497274 ps |
| T195 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1877517147 |
|
|
Feb 04 12:35:31 PM PST 24 |
Feb 04 12:35:42 PM PST 24 |
124230720 ps |
| T196 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.247270286 |
|
|
Feb 04 12:35:51 PM PST 24 |
Feb 04 12:35:59 PM PST 24 |
46758297 ps |
| T197 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2931300886 |
|
|
Feb 04 12:35:59 PM PST 24 |
Feb 04 12:36:07 PM PST 24 |
14429420 ps |
| T198 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1463127230 |
|
|
Feb 04 12:35:36 PM PST 24 |
Feb 04 12:35:46 PM PST 24 |
1254448024 ps |
| T199 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2521750225 |
|
|
Feb 04 12:35:43 PM PST 24 |
Feb 04 12:35:53 PM PST 24 |
112661291 ps |
| T200 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3102436594 |
|
|
Feb 04 12:35:46 PM PST 24 |
Feb 04 12:35:58 PM PST 24 |
621336080 ps |
| T201 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4083361625 |
|
|
Feb 04 12:35:54 PM PST 24 |
Feb 04 12:36:13 PM PST 24 |
678970567 ps |
| T99 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3953502862 |
|
|
Feb 04 12:35:55 PM PST 24 |
Feb 04 12:36:02 PM PST 24 |
130951280 ps |
| T111 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1609340902 |
|
|
Feb 04 01:38:52 PM PST 24 |
Feb 04 03:05:33 PM PST 24 |
178587724186 ps |
| T8 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3198723395 |
|
|
Feb 04 01:43:03 PM PST 24 |
Feb 04 01:44:01 PM PST 24 |
9473039717 ps |
| T202 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1217231193 |
|
|
Feb 04 01:42:23 PM PST 24 |
Feb 04 01:46:31 PM PST 24 |
7887215575 ps |
| T203 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2076059919 |
|
|
Feb 04 01:45:48 PM PST 24 |
Feb 04 01:46:17 PM PST 24 |
5571567596 ps |
| T204 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1028270873 |
|
|
Feb 04 01:42:14 PM PST 24 |
Feb 04 01:47:46 PM PST 24 |
4287693534 ps |
| T205 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3781712887 |
|
|
Feb 04 01:50:44 PM PST 24 |
Feb 04 01:57:52 PM PST 24 |
7067770624 ps |
| T206 |
/workspace/coverage/default/7.sram_ctrl_bijection.462789560 |
|
|
Feb 04 01:38:54 PM PST 24 |
Feb 04 02:11:36 PM PST 24 |
53122844907 ps |
| T25 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2936756360 |
|
|
Feb 04 01:43:45 PM PST 24 |
Feb 04 02:26:21 PM PST 24 |
47140921356 ps |
| T9 |
/workspace/coverage/default/21.sram_ctrl_stress_all.1900129938 |
|
|
Feb 04 01:43:50 PM PST 24 |
Feb 04 02:48:22 PM PST 24 |
185135490799 ps |
| T207 |
/workspace/coverage/default/37.sram_ctrl_smoke.967791132 |
|
|
Feb 04 01:48:55 PM PST 24 |
Feb 04 01:51:30 PM PST 24 |
466038354 ps |
| T208 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1002191637 |
|
|
Feb 04 01:49:58 PM PST 24 |
Feb 04 03:12:50 PM PST 24 |
1105942879 ps |
| T209 |
/workspace/coverage/default/26.sram_ctrl_smoke.1119122294 |
|
|
Feb 04 01:45:18 PM PST 24 |
Feb 04 01:45:35 PM PST 24 |
821782482 ps |
| T210 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3693921512 |
|
|
Feb 04 01:37:58 PM PST 24 |
Feb 04 01:40:21 PM PST 24 |
6901737249 ps |
| T211 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1719497694 |
|
|
Feb 04 01:44:38 PM PST 24 |
Feb 04 01:50:01 PM PST 24 |
15086753978 ps |
| T212 |
/workspace/coverage/default/36.sram_ctrl_bijection.1181584412 |
|
|
Feb 04 01:48:52 PM PST 24 |
Feb 04 01:59:19 PM PST 24 |
138930721426 ps |
| T213 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.433737455 |
|
|
Feb 04 01:46:06 PM PST 24 |
Feb 04 01:50:41 PM PST 24 |
17556587587 ps |
| T214 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2532238289 |
|
|
Feb 04 01:46:42 PM PST 24 |
Feb 04 01:51:47 PM PST 24 |
27803929634 ps |
| T215 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1015954707 |
|
|
Feb 04 01:40:41 PM PST 24 |
Feb 04 01:40:43 PM PST 24 |
20064084 ps |
| T107 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2941810603 |
|
|
Feb 04 01:42:55 PM PST 24 |
Feb 04 02:30:25 PM PST 24 |
198881453682 ps |
| T216 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.17496619 |
|
|
Feb 04 01:49:35 PM PST 24 |
Feb 04 01:52:04 PM PST 24 |
1662102522 ps |
| T217 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1953739879 |
|
|
Feb 04 01:49:10 PM PST 24 |
Feb 04 02:39:40 PM PST 24 |
832334744 ps |
| T110 |
/workspace/coverage/default/29.sram_ctrl_executable.2996192736 |
|
|
Feb 04 01:46:15 PM PST 24 |
Feb 04 02:16:40 PM PST 24 |
26931074510 ps |
| T218 |
/workspace/coverage/default/37.sram_ctrl_alert_test.2031912332 |
|
|
Feb 04 01:49:10 PM PST 24 |
Feb 04 01:49:12 PM PST 24 |
15553235 ps |
| T81 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1455165863 |
|
|
Feb 04 01:41:57 PM PST 24 |
Feb 04 01:56:18 PM PST 24 |
26459199369 ps |
| T219 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.4262014031 |
|
|
Feb 04 01:49:23 PM PST 24 |
Feb 04 01:51:53 PM PST 24 |
14078198079 ps |
| T220 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2779386858 |
|
|
Feb 04 01:41:16 PM PST 24 |
Feb 04 01:42:03 PM PST 24 |
1450780026 ps |
| T82 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.2490238759 |
|
|
Feb 04 01:45:35 PM PST 24 |
Feb 04 01:46:47 PM PST 24 |
3961516533 ps |
| T221 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.2611151455 |
|
|
Feb 04 01:47:59 PM PST 24 |
Feb 04 01:53:04 PM PST 24 |
20680691609 ps |
| T222 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.807021503 |
|
|
Feb 04 01:37:25 PM PST 24 |
Feb 04 02:31:40 PM PST 24 |
1135935925 ps |
| T223 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1187723559 |
|
|
Feb 04 01:41:07 PM PST 24 |
Feb 04 01:41:48 PM PST 24 |
2950639582 ps |
| T83 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3332206238 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 01:39:46 PM PST 24 |
1584758400 ps |
| T224 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.528387273 |
|
|
Feb 04 01:38:54 PM PST 24 |
Feb 04 01:41:00 PM PST 24 |
11613100061 ps |
| T84 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.438836086 |
|
|
Feb 04 01:42:22 PM PST 24 |
Feb 04 01:44:48 PM PST 24 |
22169024626 ps |
| T225 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.422149641 |
|
|
Feb 04 01:39:27 PM PST 24 |
Feb 04 01:42:23 PM PST 24 |
4754199286 ps |
| T226 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.686692701 |
|
|
Feb 04 01:41:53 PM PST 24 |
Feb 04 01:42:44 PM PST 24 |
2820162385 ps |
| T227 |
/workspace/coverage/default/8.sram_ctrl_alert_test.961474785 |
|
|
Feb 04 01:39:53 PM PST 24 |
Feb 04 01:39:58 PM PST 24 |
13290660 ps |
| T228 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3090424945 |
|
|
Feb 04 01:40:52 PM PST 24 |
Feb 04 01:41:07 PM PST 24 |
1606121369 ps |
| T229 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.2726477853 |
|
|
Feb 04 01:37:34 PM PST 24 |
Feb 04 01:40:33 PM PST 24 |
6349028693 ps |
| T230 |
/workspace/coverage/default/10.sram_ctrl_bijection.597412405 |
|
|
Feb 04 01:40:41 PM PST 24 |
Feb 04 02:01:39 PM PST 24 |
211644059724 ps |
| T231 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.796734182 |
|
|
Feb 04 01:51:07 PM PST 24 |
Feb 04 01:55:57 PM PST 24 |
28289852141 ps |
| T232 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.150068932 |
|
|
Feb 04 01:48:32 PM PST 24 |
Feb 04 02:16:58 PM PST 24 |
7247750083 ps |
| T233 |
/workspace/coverage/default/7.sram_ctrl_alert_test.987966289 |
|
|
Feb 04 01:39:28 PM PST 24 |
Feb 04 01:39:32 PM PST 24 |
22366391 ps |
| T234 |
/workspace/coverage/default/10.sram_ctrl_smoke.4020580601 |
|
|
Feb 04 01:40:39 PM PST 24 |
Feb 04 01:41:01 PM PST 24 |
1745398552 ps |
| T235 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1725109260 |
|
|
Feb 04 01:38:12 PM PST 24 |
Feb 04 01:46:17 PM PST 24 |
85982237018 ps |
| T94 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.167866839 |
|
|
Feb 04 01:51:17 PM PST 24 |
Feb 04 01:53:49 PM PST 24 |
47007030577 ps |
| T236 |
/workspace/coverage/default/41.sram_ctrl_smoke.19071467 |
|
|
Feb 04 01:50:07 PM PST 24 |
Feb 04 01:51:57 PM PST 24 |
4709890420 ps |
| T237 |
/workspace/coverage/default/9.sram_ctrl_smoke.29441106 |
|
|
Feb 04 01:40:31 PM PST 24 |
Feb 04 01:41:12 PM PST 24 |
734896751 ps |
| T30 |
/workspace/coverage/default/21.sram_ctrl_executable.2198652026 |
|
|
Feb 04 01:43:48 PM PST 24 |
Feb 04 01:52:39 PM PST 24 |
18813298679 ps |
| T238 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2688606924 |
|
|
Feb 04 01:37:26 PM PST 24 |
Feb 04 02:04:50 PM PST 24 |
36753606630 ps |
| T239 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1133740459 |
|
|
Feb 04 01:46:37 PM PST 24 |
Feb 04 02:42:48 PM PST 24 |
1217523076 ps |
| T108 |
/workspace/coverage/default/3.sram_ctrl_regwen.1266128643 |
|
|
Feb 04 01:37:40 PM PST 24 |
Feb 04 02:02:41 PM PST 24 |
16197013451 ps |
| T240 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.3604825201 |
|
|
Feb 04 01:37:43 PM PST 24 |
Feb 04 01:44:34 PM PST 24 |
13024391707 ps |
| T241 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1208172415 |
|
|
Feb 04 01:49:22 PM PST 24 |
Feb 04 03:29:03 PM PST 24 |
3316811819 ps |
| T242 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2201374459 |
|
|
Feb 04 01:41:52 PM PST 24 |
Feb 04 01:42:21 PM PST 24 |
2676797104 ps |
| T85 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2979925367 |
|
|
Feb 04 01:45:13 PM PST 24 |
Feb 04 01:46:33 PM PST 24 |
26196123903 ps |
| T243 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.481873969 |
|
|
Feb 04 01:36:52 PM PST 24 |
Feb 04 01:37:00 PM PST 24 |
552739545 ps |
| T244 |
/workspace/coverage/default/46.sram_ctrl_smoke.1213191698 |
|
|
Feb 04 01:52:03 PM PST 24 |
Feb 04 01:52:11 PM PST 24 |
732402538 ps |
| T245 |
/workspace/coverage/default/45.sram_ctrl_smoke.2539209474 |
|
|
Feb 04 01:51:25 PM PST 24 |
Feb 04 01:51:44 PM PST 24 |
891393411 ps |
| T246 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1397871035 |
|
|
Feb 04 01:37:30 PM PST 24 |
Feb 04 01:37:38 PM PST 24 |
1350085384 ps |
| T247 |
/workspace/coverage/default/21.sram_ctrl_alert_test.651732488 |
|
|
Feb 04 01:43:52 PM PST 24 |
Feb 04 01:43:53 PM PST 24 |
70495214 ps |
| T248 |
/workspace/coverage/default/14.sram_ctrl_alert_test.2389230023 |
|
|
Feb 04 01:42:15 PM PST 24 |
Feb 04 01:42:17 PM PST 24 |
33953694 ps |
| T249 |
/workspace/coverage/default/44.sram_ctrl_alert_test.2873718841 |
|
|
Feb 04 01:51:22 PM PST 24 |
Feb 04 01:51:26 PM PST 24 |
93785174 ps |
| T250 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1635648459 |
|
|
Feb 04 01:37:31 PM PST 24 |
Feb 04 01:39:38 PM PST 24 |
1629700638 ps |
| T32 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.3372026050 |
|
|
Feb 04 01:46:42 PM PST 24 |
Feb 04 01:48:06 PM PST 24 |
7721865912 ps |
| T251 |
/workspace/coverage/default/35.sram_ctrl_alert_test.878744543 |
|
|
Feb 04 01:48:32 PM PST 24 |
Feb 04 01:48:34 PM PST 24 |
13445473 ps |
| T252 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3525066992 |
|
|
Feb 04 01:38:52 PM PST 24 |
Feb 04 01:41:39 PM PST 24 |
20734587605 ps |
| T253 |
/workspace/coverage/default/8.sram_ctrl_smoke.3745721393 |
|
|
Feb 04 01:39:27 PM PST 24 |
Feb 04 01:42:11 PM PST 24 |
3907112991 ps |
| T254 |
/workspace/coverage/default/21.sram_ctrl_smoke.3069576486 |
|
|
Feb 04 01:43:41 PM PST 24 |
Feb 04 01:44:34 PM PST 24 |
1407383720 ps |
| T255 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.410990666 |
|
|
Feb 04 01:47:45 PM PST 24 |
Feb 04 01:52:14 PM PST 24 |
3831692312 ps |
| T256 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.307776753 |
|
|
Feb 04 01:48:52 PM PST 24 |
Feb 04 01:49:39 PM PST 24 |
1428510517 ps |
| T257 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2034483353 |
|
|
Feb 04 01:52:12 PM PST 24 |
Feb 04 01:57:20 PM PST 24 |
18628433247 ps |
| T258 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2002680499 |
|
|
Feb 04 01:52:02 PM PST 24 |
Feb 04 01:52:33 PM PST 24 |
706213252 ps |
| T259 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1995770090 |
|
|
Feb 04 01:42:06 PM PST 24 |
Feb 04 03:56:44 PM PST 24 |
499050559 ps |
| T260 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3005596783 |
|
|
Feb 04 01:49:46 PM PST 24 |
Feb 04 03:30:44 PM PST 24 |
2476119736 ps |
| T109 |
/workspace/coverage/default/12.sram_ctrl_executable.503771450 |
|
|
Feb 04 01:41:17 PM PST 24 |
Feb 04 01:48:01 PM PST 24 |
17521254806 ps |
| T261 |
/workspace/coverage/default/29.sram_ctrl_smoke.3696501069 |
|
|
Feb 04 01:46:14 PM PST 24 |
Feb 04 01:46:36 PM PST 24 |
3252299423 ps |
| T262 |
/workspace/coverage/default/19.sram_ctrl_partial_access.1381567233 |
|
|
Feb 04 01:43:06 PM PST 24 |
Feb 04 01:43:41 PM PST 24 |
5035553501 ps |
| T263 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2806981395 |
|
|
Feb 04 01:39:28 PM PST 24 |
Feb 04 01:45:18 PM PST 24 |
21322529378 ps |
| T33 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2527552319 |
|
|
Feb 04 01:47:22 PM PST 24 |
Feb 04 01:49:07 PM PST 24 |
26420188504 ps |
| T26 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2244975083 |
|
|
Feb 04 01:37:42 PM PST 24 |
Feb 04 01:37:46 PM PST 24 |
435944695 ps |
| T264 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3454287519 |
|
|
Feb 04 01:52:49 PM PST 24 |
Feb 04 02:20:49 PM PST 24 |
163348851 ps |
| T265 |
/workspace/coverage/default/26.sram_ctrl_bijection.2262210298 |
|
|
Feb 04 01:45:22 PM PST 24 |
Feb 04 01:54:54 PM PST 24 |
91203646073 ps |
| T113 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3459669601 |
|
|
Feb 04 01:49:11 PM PST 24 |
Feb 04 02:57:42 PM PST 24 |
109579810977 ps |