Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	114926965	1			T2	98303		T3	150888		T4	1643
triple_byte_access	2606473	1			T3	3002		T4	3673		T5	86
halfword_access	4006949	1			T3	4489		T4	6567		T5	108
byte_access	5636724	1			T3	6104		T4	13164		T5	160
zero_access	1745776	1			T3	1441		T4	7520		T5	34

---

Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63746498

1

T2

32768

T3

83110

T4

16207

auto[1]

65176389

1

T2

65535

T3

82814

T4

16360

---

Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	56648846	1			T2	32768		T3	75521		T4	137
auto[0]	triple_byte_access	1224287	1			T3	1499		T4	703		T5	40
auto[0]	halfword_access	1938780	1			T3	2237		T4	2293		T5	50
auto[0]	byte_access	2878828	1			T3	3105		T4	7025		T5	72
auto[0]	zero_access	1055757	1			T3	748		T4	6049		T5	10
auto[1]	word_access	58278119	1			T2	65535		T3	75367		T4	1506
auto[1]	triple_byte_access	1382186	1			T3	1503		T4	2970		T5	46
auto[1]	halfword_access	2068169	1			T3	2252		T4	4274		T5	58
auto[1]	byte_access	2757896	1			T3	2999		T4	6139		T5	88
auto[1]	zero_access	690019	1			T3	693		T4	1471		T5	24