0dd29ab736| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.884m | 5.443ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.770s | 69.149us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.670s | 19.279us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.170s | 779.083us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.710s | 18.188us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 14.600s | 4.976ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.670s | 19.279us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.710s | 18.188us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 5.563m | 43.119ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 2.904m | 57.044ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 205 | 205 | 100.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 38.912m | 77.233ms | 50 | 50 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.970m | 5.884ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 48.492m | 574.202ms | 49 | 50 | 98.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 42.568m | 47.141ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 6.249m | 73.180ms | 46 | 50 | 92.00 |
| V2 | executable | sram_ctrl_executable | 32.335m | 205.300ms | 25 | 50 | 50.00 |
| V2 | partial_access | sram_ctrl_partial_access | 3.277m | 3.539ms | 49 | 50 | 98.00 |
| sram_ctrl_partial_access_b2b | 11.732m | 28.259ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 3.252m | 1.568ms | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 3.047m | 3.112ms | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 28.828m | 7.768ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 14.570s | 1.606ms | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.189h | 1.470s | 28 | 50 | 56.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.700s | 26.738us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.470s | 134.451us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.470s | 134.451us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.770s | 69.149us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.670s | 19.279us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.710s | 18.188us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.800s | 217.164us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.770s | 69.149us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.670s | 19.279us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.710s | 18.188us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.800s | 217.164us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 687 | 740 | 92.84 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 1.928m | 8.417ms | 0 | 20 | 0.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.250s | 234.459us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.600s | 1.010ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.250s | 234.459us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.600s | 1.010ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 28.828m | 7.768ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.670s | 19.279us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 32.335m | 205.300ms | 25 | 50 | 50.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 32.335m | 205.300ms | 25 | 50 | 50.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 32.335m | 205.300ms | 25 | 50 | 50.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 6.249m | 73.180ms | 46 | 50 | 92.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 1.928m | 8.417ms | 0 | 20 | 0.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.884m | 5.443ms | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.884m | 5.443ms | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 32.335m | 205.300ms | 25 | 50 | 50.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.250s | 234.459us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 6.249m | 73.180ms | 46 | 50 | 92.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.250s | 234.459us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.250s | 234.459us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.884m | 5.443ms | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.250s | 234.459us | 5 | 5 | 100.00 |
| V2S | TOTAL | 25 | 45 | 55.56 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 2.504h | 1.460ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 967 | 1040 | 92.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 16 | 16 | 11 | 68.75 |
| V2S | 3 | 3 | 2 | 66.67 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.52 | 100.00 | 98.32 | 100.00 | 100.00 | 99.72 | 99.70 | 98.89 |
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed has 20 failures:
0.sram_ctrl_passthru_mem_tl_intg_err.26626070402962452665261838025330273078356583987162223747006169806771545770381
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_WARNING @ 1176590160 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
UVM_INFO @ 1176804444 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 2839146206 val
UVM_INFO @ 1176983014 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 1 val
UVM_ERROR @ 1177054442 ps: (sram_ctrl_scoreboard.sv:560) [uvm_test_top.env.scoreboard] Check failed mirrored_value == item.d_data (6 [0x6] vs 14 [0xe]) reg name: sram_ctrl_regs_reg_block.scr_key_rotated
UVM_INFO @ 1177054442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
1.sram_ctrl_passthru_mem_tl_intg_err.34703576783457645415656625317144481636893861245583228063127763185353955434842
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_WARNING @ 343528079 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'success' while register 'sram_ctrl_regs_reg_block.scr_key_rotated' is being accessed
UVM_INFO @ 343600998 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 3338434966 val
UVM_INFO @ 343663500 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 2216890114 val
UVM_INFO @ 344278103 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.ctrl_regwen] lock_lockable_flds 0 val
UVM_INFO @ 344382273 ps: (dv_base_reg.sv:316) [sram_ctrl_regs_reg_block.exec_regwen] lock_lockable_flds 0 val
... and 18 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:164) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) item_err: *, allow_ifetch : *, sram_ifetch: *, exec: *, debug_en: *, lc_esc * has 17 failures:
4.sram_ctrl_stress_all.44268418148914435515257594294699448034349550535782800635333315842383705916158
Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 10251493361 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 150, exec: 9, debug_en: 3, lc_esc 0
UVM_INFO @ 10251493361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.sram_ctrl_stress_all.74010461499440242184343830344247429363241078747102194595124000899108710082561
Line 523, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 742026970492 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 150, exec: 9, debug_en: 5, lc_esc 0
UVM_INFO @ 742026970492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
11.sram_ctrl_executable.13172003767002433217597865509489034148200113775801077666680354698062307580905
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 1027409632 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 105, exec: 6, debug_en: 10, lc_esc 0
UVM_INFO @ 1027409632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.sram_ctrl_executable.96863103214422717944172312878471999414967790822989879223485951827617318296777
Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 11969010282 ps: (sram_ctrl_scoreboard.sv:164) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) item_err: 1, allow_ifetch : 0, sram_ifetch: 81, exec: 14, debug_en: 13, lc_esc 0
UVM_INFO @ 11969010282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 10 failures:
1.sram_ctrl_stress_all.24172730400654561201824000960204413144842881345869581378411289446975342796446
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 16340404108 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 16340404108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.sram_ctrl_stress_all.51245118292129472365843898900221507189170340565286362071119797144672085062572
Line 272, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 4077598437 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 4077598437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
4.sram_ctrl_lc_escalation.6311351693752128724817721556996547250090945395667564470222421681982254323498
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 13495585771 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 13495585771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.sram_ctrl_lc_escalation.60221740356032533239393324410300931822887982229961926632618343314481500428223
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 3814362313 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 3814362313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@495189) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.sram_ctrl_executable.63393091406960489603910306515387751294475026674712008073020179479959797204025
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 1432410012 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@495189) { a_addr: 'h50448b54 a_data: 'h4a33bb56 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4f a_opcode: 'h4 a_user: 'h19500 d_param: 'h0 d_source: 'h4f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1432410012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@143259) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.sram_ctrl_executable.53248576562438354112650499578634313858229610544473037438747862068917501891413
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 657557721 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@143259) { a_addr: 'h48c47400 a_data: 'h1601f6a8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h91 a_opcode: 'h4 a_user: 'h1885f d_param: 'h0 d_source: 'h91 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 657557721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
3.sram_ctrl_partial_access.14052582024293423935760979618425755314480084796913021375318934699884936484642
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest/run.log
UVM_FATAL @ 23159838820 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa300ee45
UVM_INFO @ 23159838820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@981102) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.sram_ctrl_executable.3740272231063745166214274564160520658946693215597408820100430534895524719714
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 2826719861 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@981102) { a_addr: 'h93169674 a_data: 'hcffd901f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h186d1 d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2826719861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@44069183) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
5.sram_ctrl_stress_all.47376951710939776323300797063760505653116997604305564345397437988527319009066
Line 313, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 474117563225 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@44069183) { a_addr: 'hda25bff0 a_data: 'h9cf27086 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hce a_opcode: 'h4 a_user: 'h1ac03 d_param: 'h0 d_source: 'hce d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 474117563225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@39087487) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
9.sram_ctrl_stress_all.37098778790623413576680818143994020986528183032082789678983706487529464698903
Line 581, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 1469791780590 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@39087487) { a_addr: 'h2f7f0248 a_data: 'h30dafe70 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h67 a_opcode: 'h4 a_user: 'h1a536 d_param: 'h0 d_source: 'h67 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1469791780590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1682922) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.sram_ctrl_executable.30972527284026391848361722025107314720443478185271283957951759566694163148506
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 4970735702 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1682922) { a_addr: 'hfebed030 a_data: 'hb1da7c3b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hce a_opcode: 'h4 a_user: 'h181a4 d_param: 'h0 d_source: 'hce d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4970735702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@391530) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.sram_ctrl_executable.23649260372059764978584742288701471462093209173510367233117246257224581965529
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 5358825206 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@391530) { a_addr: 'h689006c0 a_data: 'h138f96cf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1b3a0 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 5358825206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1291590) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
20.sram_ctrl_executable.74421039016726809957854778170076403437957180515996084118490865570451128580137
Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 10282061159 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1291590) { a_addr: 'hb2ef9898 a_data: 'h433ed62f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h57 a_opcode: 'h4 a_user: 'h1b581 d_param: 'h0 d_source: 'h57 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 10282061159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4029139) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
20.sram_ctrl_stress_all.50681472803476546855803975052926267164850013238794136687600565159648848531707
Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 28553482039 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4029139) { a_addr: 'h6efcac34 a_data: 'hfe1b5c80 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h95 a_opcode: 'h4 a_user: 'h18f19 d_param: 'h0 d_source: 'h95 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 28553482039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
21.sram_ctrl_bijection.13857680151099776571449219591701124301221149478017918711131410716294464354658
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3203494) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
23.sram_ctrl_executable.22643205644499944769844855212524665421794158566478071932232873417347842258981
Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 9530782151 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3203494) { a_addr: 'hce38924c a_data: 'h1780b443 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h1b607 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 9530782151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1670784) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
24.sram_ctrl_executable.16637013278997580425395966688586143086165953225915589883511453297178834184919
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 4708239617 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1670784) { a_addr: 'h6a938a88 a_data: 'hdce2a0af a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb4 a_opcode: 'h4 a_user: 'h192d5 d_param: 'h0 d_source: 'hb4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4708239617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496669) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
25.sram_ctrl_executable.51037998534704756309482684730953258274447486585904014638071985215255305312057
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 333631324 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@496669) { a_addr: 'h5dadcc60 a_data: 'h9c8e9adb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h76 a_opcode: 'h4 a_user: 'h1b2af d_param: 'h0 d_source: 'h76 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 333631324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@11168561) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
25.sram_ctrl_stress_all.110160991413284206683554539031536442562158424320871158675359447796761403558237
Line 337, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 133546817743 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@11168561) { a_addr: 'h3c6467b4 a_data: 'h8549cc69 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9e a_opcode: 'h4 a_user: 'h1aa84 d_param: 'h0 d_source: 'h9e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 133546817743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3890228) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
26.sram_ctrl_executable.21544684163544076076124309620816629242278530358852353498832172210555580686442
Line 320, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 16944593717 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3890228) { a_addr: 'h537fe298 a_data: 'h65a21bea a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'h56 a_opcode: 'h4 a_user: 'h1929f d_param: 'h0 d_source: 'h56 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 16944593717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@13703487) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
26.sram_ctrl_stress_all.62545117271901644288331931191241452534153247063870260451095081783697275714521
Line 345, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 37954332301 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@13703487) { a_addr: 'hcf1a1418 a_data: 'hb4a633b7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf3 a_opcode: 'h4 a_user: 'h180d8 d_param: 'h0 d_source: 'hf3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 37954332301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@11399959) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
34.sram_ctrl_stress_all.58655493110021735044770982244288504208555578704495446627094773150611245438633
Line 471, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 18180907000 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@11399959) { a_addr: 'h6394e000 a_data: 'ha8a49b61 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h66 a_opcode: 'h4 a_user: 'h19caa d_param: 'h0 d_source: 'h66 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 18180907000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@399894) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
38.sram_ctrl_executable.20520403018547646350697564923631377922938519107396262624829908062868173854853
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 1483626096 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@399894) { a_addr: 'h384033dc a_data: 'h7a85581f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h19513 d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1483626096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@39339353) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
41.sram_ctrl_stress_all.20968995543478688826034398700254719454216249024022400874134258925872793561996
Line 335, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 160655493409 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@39339353) { a_addr: 'h60e369c0 a_data: 'habd742b3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hfb a_opcode: 'h4 a_user: 'h189e4 d_param: 'h0 d_source: 'hfb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 160655493409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1735804) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
42.sram_ctrl_executable.61436684292108908561794344604508559165926924257686158470709709783542761493722
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 4660061797 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1735804) { a_addr: 'h20bf5b20 a_data: 'h543cb2cb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hed a_opcode: 'h4 a_user: 'h1a9de d_param: 'h0 d_source: 'hed d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4660061797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3904544) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
46.sram_ctrl_executable.109153407715526059505121134754662255354340873114585055996470430995326822922249
Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 9101688778 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3904544) { a_addr: 'hf25dc354 a_data: 'heb836833 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h58 a_opcode: 'h4 a_user: 'h1aa29 d_param: 'h0 d_source: 'h58 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 9101688778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@28379557) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
46.sram_ctrl_stress_all.90770493454430373809561428624544745063511009984385431801774094474974104060190
Line 399, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 137648223524 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@28379557) { a_addr: 'h2bc04094 a_data: 'hc15aa553 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1959e d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 137648223524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1625554) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
47.sram_ctrl_executable.107897205959711157621667574023931703663528248845896243559343937242695941068758
Line 298, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 10098784823 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@1625554) { a_addr: 'h9fdb58f4 a_data: 'hd8b3241f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h27 a_opcode: 'h4 a_user: 'h19451 d_param: 'h0 d_source: 'h27 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 10098784823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5882816) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
48.sram_ctrl_executable.46095332248518733790085935652179017322501343913692500250584334661603832432519
Line 354, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 104270668219 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5882816) { a_addr: 'h89abd0e0 a_data: 'hdcd2a1be a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h187db d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 104270668219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4795300) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
49.sram_ctrl_executable.70538908036074334247269744479610305159468272570123947851308963018295946799537
Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 13068600845 ps: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4795300) { a_addr: 'hc3f5f004 a_data: 'hd1d87628 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hfe a_opcode: 'h4 a_user: 'h18872 d_param: 'h0 d_source: 'hfe d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 13068600845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---