Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14645154

1

T1

59532

T2

3152

T3

30663

full_word

110947077

1

T1

3129

T2

32639

T3

305824

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	125591911	1			T1	62661		T2	35791		T3	336487
auto[TlIntgErrCmd]	114	1			T36	7		T37	5		T52	3
auto[TlIntgErrData]	103	1			T36	5		T37	6		T52	5
auto[TlIntgErrBoth]	103	1			T36	8		T37	9		T52	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60512717

1

T1

31185

T2

18028

T3

168528

auto[1]

65079514

1

T1

31476

T2

17763

T3

167959

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7212727	1			T1	30911		T2	1649		T3	15315
auto[TlIntgErrNone]	partial	auto[1]	7432125	1			T1	28621		T2	1503		T3	15348
auto[TlIntgErrNone]	full_word	auto[0]	53299843	1			T1	274		T2	16379		T3	153213
auto[TlIntgErrNone]	full_word	auto[1]	57647216	1			T1	2855		T2	16260		T3	152611
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T36	2		T37	3		T52	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T36	5		T37	2		T52	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T118	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T117	1		T121	2		T122	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T36	3		T37	2		T52	5
auto[TlIntgErrData]	partial	auto[1]	42	1			T36	2		T37	4		T63	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T121	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T91	1		T118	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T36	4		T37	6		T63	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T36	2		T37	2		T52	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T36	1		T37	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T36	1		T120	1		T119	1