Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	679588	1			T5	21059		T6	2829		T14	385
auto[1]	9688761	1			T1	28383		T2	828		T3	140408
auto[2]	518582	1			T5	14868		T6	2630		T14	429
auto[3]	9530653	1			T1	28687		T2	373		T3	139835

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12433551	1			T1	292		T2	999		T3	233714
auto[1]	1930879	1			T1	2816		T2	98		T3	22125
auto[2]	1950387	1			T1	5303		T2	94		T3	22149
auto[3]	4102767	1			T1	48659		T2	10		T3	2255

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7258931

1

T1

57068

T2

1201

T3

19

auto[1]

13158653

1

T1

2

T3

280224

T5

65686

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	237381	1			T6	2343		T14	9		T7	4
auto[0]	auto[0]	auto[1]	25015	1			T6	247		T14	54		T24	178
auto[0]	auto[0]	auto[2]	25046	1			T6	219		T14	57		T7	2
auto[0]	auto[0]	auto[3]	64793	1			T6	20		T14	265		T24	26
auto[0]	auto[1]	auto[0]	2406693	1			T1	33		T2	685		T3	8
auto[0]	auto[1]	auto[1]	262891	1			T1	220		T2	63		T10	641
auto[0]	auto[1]	auto[2]	272953	1			T1	2930		T2	72		T3	1
auto[0]	auto[1]	auto[3]	419117	1			T1	25199		T2	8		T10	135
auto[0]	auto[2]	auto[0]	177682	1			T6	2163		T14	12		T7	3
auto[0]	auto[2]	auto[1]	22340	1			T6	243		T14	34		T24	104
auto[0]	auto[2]	auto[2]	18857	1			T6	211		T14	64		T24	75
auto[0]	auto[2]	auto[3]	48387	1			T6	13		T14	319		T24	8
auto[0]	auto[3]	auto[0]	2348192	1			T1	259		T2	314		T3	8
auto[0]	auto[3]	auto[1]	263028	1			T1	2596		T2	35		T3	1
auto[0]	auto[3]	auto[2]	286090	1			T1	2373		T2	22		T3	1
auto[0]	auto[3]	auto[3]	380466	1			T1	23458		T2	2		T10	139
auto[1]	auto[0]	auto[0]	10766	1			T5	692		T101	427		T133	848
auto[1]	auto[0]	auto[1]	48591	1			T5	3188		T101	2039		T133	3918
auto[1]	auto[0]	auto[2]	48884	1			T5	3184		T101	2002		T133	3817
auto[1]	auto[0]	auto[3]	219112	1			T5	13995		T101	9008		T84	1
auto[1]	auto[1]	auto[0]	3622204	1			T3	117156		T5	118		T33	1
auto[1]	auto[1]	auto[1]	650847	1			T3	10478		T5	3123		T59	6410
auto[1]	auto[1]	auto[2]	622181	1			T3	11637		T5	491		T59	7095
auto[1]	auto[1]	auto[3]	1431875	1			T1	1		T3	1128		T5	14007
auto[1]	auto[2]	auto[0]	9542	1			T5	639		T101	258		T134	1
auto[1]	auto[2]	auto[1]	42774	1			T5	2817		T101	1260		T133	3621
auto[1]	auto[2]	auto[2]	36092	1			T5	2164		T101	1980		T133	2550
auto[1]	auto[2]	auto[3]	162908	1			T5	9248		T101	8509		T133	12022
auto[1]	auto[3]	auto[0]	3621091	1			T3	116542		T5	73		T59	73043
auto[1]	auto[3]	auto[1]	615393	1			T3	11646		T5	274		T59	7108
auto[1]	auto[3]	auto[2]	640284	1			T3	10510		T5	2172		T59	6360
auto[1]	auto[3]	auto[3]	1376109	1			T1	1		T3	1127		T5	9501