Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	846552989	146678	0	0
ctrl_regwen_rd_A	846552989	6969	0	0
exec_rd_A	846552989	6429	0	0
exec_regwen_rd_A	846552989	7145	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846552989	146678	0	0
T12	57478	1677	0	0
T13	937212	0	0	0
T14	72643	0	0	0
T15	71611	0	0	0
T16	45953	0	0	0
T23	89253	0	0	0
T25	0	5984	0	0
T33	150110	4691	0	0
T34	0	5248	0	0
T36	0	5	0	0
T37	0	3	0	0
T38	34549	0	0	0
T52	0	1	0	0
T53	0	13	0	0
T54	0	16	0	0
T55	0	389	0	0
T59	377865	0	0	0
T60	389488	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846552989	6969	0	0
T25	358155	1375	0	0
T52	8610	22	0	0
T57	34978	41	0	0
T58	1853	0	0	0
T62	13633	57	0	0
T67	2635	19	0	0
T68	1130	0	0	0
T69	0	9	0	0
T71	0	81	0	0
T72	0	86	0	0
T79	0	36	0	0
T108	9107	233	0	0
T112	13120	0	0	0
T113	34960	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846552989	6429	0	0
T25	358155	1167	0	0
T52	8610	52	0	0
T57	34978	11	0	0
T58	1853	0	0	0
T62	13633	99	0	0
T67	2635	0	0	0
T71	0	73	0	0
T72	0	133	0	0
T79	0	13	0	0
T80	0	9	0	0
T108	9107	217	0	0
T109	891	5	0	0
T112	13120	0	0	0
T113	34960	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846552989	7145	0	0
T25	358155	1319	0	0
T52	8610	11	0	0
T57	34978	33	0	0
T58	1853	0	0	0
T62	13633	60	0	0
T67	2635	19	0	0
T68	1130	0	0	0
T69	0	7	0	0
T71	0	80	0	0
T72	0	95	0	0
T73	0	3	0	0
T108	9107	212	0	0
T112	13120	0	0	0
T113	34960	0	0	0