Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.52 100.00 98.32 100.00 100.00 99.72 99.70 98.89


Total test records in report: 961
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T751 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3806444889 Feb 07 02:02:45 PM PST 24 Feb 07 02:08:57 PM PST 24 15970491658 ps
T752 /workspace/coverage/default/19.sram_ctrl_ram_cfg.1682468749 Feb 07 02:01:58 PM PST 24 Feb 07 02:02:13 PM PST 24 1354382384 ps
T753 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1140986247 Feb 07 02:01:47 PM PST 24 Feb 07 02:04:18 PM PST 24 8898154737 ps
T754 /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2507968395 Feb 07 02:08:11 PM PST 24 Feb 07 02:13:03 PM PST 24 22959779653 ps
T755 /workspace/coverage/default/38.sram_ctrl_ram_cfg.449382951 Feb 07 02:08:12 PM PST 24 Feb 07 02:08:19 PM PST 24 363261151 ps
T756 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3652095252 Feb 07 02:00:53 PM PST 24 Feb 07 02:06:33 PM PST 24 4126227600 ps
T757 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.466601184 Feb 07 02:00:59 PM PST 24 Feb 07 02:01:27 PM PST 24 2814983663 ps
T758 /workspace/coverage/default/21.sram_ctrl_mem_walk.1391227093 Feb 07 02:02:21 PM PST 24 Feb 07 02:07:41 PM PST 24 21967861228 ps
T759 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.449349049 Feb 07 02:08:13 PM PST 24 Feb 07 02:09:34 PM PST 24 26082835834 ps
T760 /workspace/coverage/default/42.sram_ctrl_lc_escalation.1722846853 Feb 07 02:08:19 PM PST 24 Feb 07 02:11:55 PM PST 24 40740596132 ps
T761 /workspace/coverage/default/39.sram_ctrl_mem_walk.444322242 Feb 07 02:08:16 PM PST 24 Feb 07 02:12:30 PM PST 24 19691030484 ps
T762 /workspace/coverage/default/41.sram_ctrl_bijection.3679859191 Feb 07 02:08:34 PM PST 24 Feb 07 02:31:15 PM PST 24 176374466405 ps
T763 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2518030422 Feb 07 02:00:47 PM PST 24 Feb 07 02:03:25 PM PST 24 4545322852 ps
T764 /workspace/coverage/default/6.sram_ctrl_mem_walk.2635435725 Feb 07 02:00:58 PM PST 24 Feb 07 02:03:30 PM PST 24 14049981524 ps
T765 /workspace/coverage/default/47.sram_ctrl_alert_test.3953593192 Feb 07 02:09:31 PM PST 24 Feb 07 02:09:36 PM PST 24 11744024 ps
T766 /workspace/coverage/default/9.sram_ctrl_ram_cfg.1445139522 Feb 07 02:01:19 PM PST 24 Feb 07 02:01:26 PM PST 24 1399754337 ps
T767 /workspace/coverage/default/45.sram_ctrl_stress_all.428645844 Feb 07 02:09:02 PM PST 24 Feb 07 02:47:13 PM PST 24 89561923669 ps
T768 /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3272975295 Feb 07 02:02:45 PM PST 24 Feb 07 03:49:54 PM PST 24 4814042969 ps
T769 /workspace/coverage/default/4.sram_ctrl_partial_access.4238136246 Feb 07 02:00:53 PM PST 24 Feb 07 02:01:35 PM PST 24 1573619339 ps
T770 /workspace/coverage/default/5.sram_ctrl_ram_cfg.200159035 Feb 07 02:00:59 PM PST 24 Feb 07 02:01:14 PM PST 24 351566136 ps
T771 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1976624446 Feb 07 02:08:23 PM PST 24 Feb 07 02:12:20 PM PST 24 70611768352 ps
T772 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.789077232 Feb 07 02:03:20 PM PST 24 Feb 07 02:17:56 PM PST 24 14752886446 ps
T773 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2980356802 Feb 07 02:08:14 PM PST 24 Feb 07 02:15:53 PM PST 24 25996609346 ps
T774 /workspace/coverage/default/35.sram_ctrl_lc_escalation.2409832317 Feb 07 02:08:01 PM PST 24 Feb 07 02:11:28 PM PST 24 23779910159 ps
T775 /workspace/coverage/default/2.sram_ctrl_multiple_keys.1717955028 Feb 07 02:00:42 PM PST 24 Feb 07 02:01:11 PM PST 24 1326964975 ps
T776 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1109541936 Feb 07 02:02:24 PM PST 24 Feb 07 02:03:14 PM PST 24 715202445 ps
T777 /workspace/coverage/default/29.sram_ctrl_multiple_keys.3947007631 Feb 07 02:03:55 PM PST 24 Feb 07 02:43:31 PM PST 24 31267540156 ps
T778 /workspace/coverage/default/22.sram_ctrl_alert_test.3057830811 Feb 07 02:02:44 PM PST 24 Feb 07 02:02:48 PM PST 24 31017322 ps
T779 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4114051573 Feb 07 02:03:56 PM PST 24 Feb 07 02:11:51 PM PST 24 39148256791 ps
T780 /workspace/coverage/default/48.sram_ctrl_mem_walk.704549184 Feb 07 02:09:29 PM PST 24 Feb 07 02:13:38 PM PST 24 8047869455 ps
T781 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1232702628 Feb 07 02:02:44 PM PST 24 Feb 07 02:03:37 PM PST 24 739117725 ps
T782 /workspace/coverage/default/12.sram_ctrl_ram_cfg.3522647697 Feb 07 02:01:25 PM PST 24 Feb 07 02:01:32 PM PST 24 359740104 ps
T783 /workspace/coverage/default/10.sram_ctrl_executable.1354653592 Feb 07 02:01:22 PM PST 24 Feb 07 02:19:33 PM PST 24 36239228046 ps
T784 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2239659982 Feb 07 02:08:14 PM PST 24 Feb 07 02:12:28 PM PST 24 8110906656 ps
T785 /workspace/coverage/default/40.sram_ctrl_lc_escalation.871661546 Feb 07 02:08:16 PM PST 24 Feb 07 02:09:12 PM PST 24 5220162598 ps
T786 /workspace/coverage/default/44.sram_ctrl_multiple_keys.1530967305 Feb 07 02:08:34 PM PST 24 Feb 07 02:16:32 PM PST 24 8243694650 ps
T787 /workspace/coverage/default/24.sram_ctrl_max_throughput.3301536472 Feb 07 02:02:44 PM PST 24 Feb 07 02:03:37 PM PST 24 2719322372 ps
T788 /workspace/coverage/default/32.sram_ctrl_smoke.1488782288 Feb 07 02:07:59 PM PST 24 Feb 07 02:08:23 PM PST 24 4863315011 ps
T789 /workspace/coverage/default/32.sram_ctrl_executable.3748065564 Feb 07 02:07:57 PM PST 24 Feb 07 02:12:20 PM PST 24 19065150066 ps
T790 /workspace/coverage/default/41.sram_ctrl_smoke.2302270766 Feb 07 02:08:29 PM PST 24 Feb 07 02:08:51 PM PST 24 454053619 ps
T791 /workspace/coverage/default/38.sram_ctrl_bijection.2843155350 Feb 07 02:08:12 PM PST 24 Feb 07 02:35:56 PM PST 24 24422382318 ps
T792 /workspace/coverage/default/13.sram_ctrl_ram_cfg.1601420968 Feb 07 02:01:32 PM PST 24 Feb 07 02:01:38 PM PST 24 348733730 ps
T793 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1342055617 Feb 07 02:01:05 PM PST 24 Feb 07 02:01:51 PM PST 24 2989137001 ps
T794 /workspace/coverage/default/39.sram_ctrl_smoke.4193265664 Feb 07 02:08:12 PM PST 24 Feb 07 02:08:32 PM PST 24 419966958 ps
T795 /workspace/coverage/default/45.sram_ctrl_multiple_keys.289917345 Feb 07 02:08:48 PM PST 24 Feb 07 02:28:31 PM PST 24 346210488058 ps
T796 /workspace/coverage/default/24.sram_ctrl_regwen.175049414 Feb 07 02:02:44 PM PST 24 Feb 07 02:10:00 PM PST 24 4990200378 ps
T797 /workspace/coverage/default/33.sram_ctrl_max_throughput.598792926 Feb 07 02:08:01 PM PST 24 Feb 07 02:10:02 PM PST 24 798499239 ps
T798 /workspace/coverage/default/40.sram_ctrl_ram_cfg.512381561 Feb 07 02:08:28 PM PST 24 Feb 07 02:08:34 PM PST 24 715244047 ps
T799 /workspace/coverage/default/40.sram_ctrl_mem_walk.751841733 Feb 07 02:08:21 PM PST 24 Feb 07 02:10:45 PM PST 24 6903031607 ps
T800 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3858065358 Feb 07 02:02:45 PM PST 24 Feb 07 02:04:05 PM PST 24 1685908049 ps
T801 /workspace/coverage/default/7.sram_ctrl_access_during_key_req.953738977 Feb 07 02:01:16 PM PST 24 Feb 07 02:30:12 PM PST 24 37421928176 ps
T802 /workspace/coverage/default/5.sram_ctrl_stress_all.2051506518 Feb 07 02:00:55 PM PST 24 Feb 07 02:32:56 PM PST 24 209742047099 ps
T803 /workspace/coverage/default/44.sram_ctrl_bijection.3615090340 Feb 07 02:08:33 PM PST 24 Feb 07 02:44:37 PM PST 24 144668117272 ps
T804 /workspace/coverage/default/47.sram_ctrl_lc_escalation.2124511569 Feb 07 02:09:28 PM PST 24 Feb 07 02:12:56 PM PST 24 20275077942 ps
T805 /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1557620454 Feb 07 02:03:22 PM PST 24 Feb 07 02:11:00 PM PST 24 36255544265 ps
T806 /workspace/coverage/default/35.sram_ctrl_bijection.2934142404 Feb 07 02:08:01 PM PST 24 Feb 07 02:20:35 PM PST 24 10845001671 ps
T807 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2068867540 Feb 07 02:01:05 PM PST 24 Feb 07 02:05:12 PM PST 24 12001988054 ps
T808 /workspace/coverage/default/45.sram_ctrl_max_throughput.3147983710 Feb 07 02:08:51 PM PST 24 Feb 07 02:10:07 PM PST 24 752935005 ps
T809 /workspace/coverage/default/13.sram_ctrl_stress_all.2500777161 Feb 07 02:01:38 PM PST 24 Feb 07 03:12:48 PM PST 24 146033125937 ps
T810 /workspace/coverage/default/48.sram_ctrl_partial_access.805377812 Feb 07 02:09:18 PM PST 24 Feb 07 02:09:45 PM PST 24 5161708595 ps
T811 /workspace/coverage/default/17.sram_ctrl_regwen.2735862167 Feb 07 02:01:44 PM PST 24 Feb 07 02:16:10 PM PST 24 106993034040 ps
T812 /workspace/coverage/default/38.sram_ctrl_regwen.443318599 Feb 07 02:08:11 PM PST 24 Feb 07 02:20:54 PM PST 24 25591373024 ps
T813 /workspace/coverage/default/33.sram_ctrl_executable.3094137404 Feb 07 02:08:03 PM PST 24 Feb 07 02:13:32 PM PST 24 12622171236 ps
T814 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3041734599 Feb 07 02:01:33 PM PST 24 Feb 07 02:06:01 PM PST 24 57763466659 ps
T815 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2815534375 Feb 07 02:09:40 PM PST 24 Feb 07 02:10:58 PM PST 24 771421994 ps
T816 /workspace/coverage/default/26.sram_ctrl_partial_access.3009762260 Feb 07 02:03:21 PM PST 24 Feb 07 02:04:16 PM PST 24 1065836146 ps
T817 /workspace/coverage/default/36.sram_ctrl_lc_escalation.3899563353 Feb 07 02:07:59 PM PST 24 Feb 07 02:10:23 PM PST 24 53584116633 ps
T818 /workspace/coverage/default/2.sram_ctrl_max_throughput.1352899418 Feb 07 02:00:42 PM PST 24 Feb 07 02:01:33 PM PST 24 2846478098 ps
T819 /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2131544702 Feb 07 02:01:41 PM PST 24 Feb 07 02:07:13 PM PST 24 61088633656 ps
T820 /workspace/coverage/default/42.sram_ctrl_executable.1928411165 Feb 07 02:08:19 PM PST 24 Feb 07 02:27:35 PM PST 24 19847332381 ps
T821 /workspace/coverage/default/13.sram_ctrl_partial_access.2611602977 Feb 07 02:01:34 PM PST 24 Feb 07 02:02:53 PM PST 24 3073303438 ps
T822 /workspace/coverage/default/22.sram_ctrl_bijection.2176831314 Feb 07 02:02:19 PM PST 24 Feb 07 02:19:16 PM PST 24 105961281580 ps
T823 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.4120966477 Feb 07 02:02:23 PM PST 24 Feb 07 02:07:27 PM PST 24 4931889038 ps
T824 /workspace/coverage/default/39.sram_ctrl_ram_cfg.543157583 Feb 07 02:08:11 PM PST 24 Feb 07 02:08:26 PM PST 24 3745925013 ps
T825 /workspace/coverage/default/16.sram_ctrl_multiple_keys.3363309151 Feb 07 02:01:33 PM PST 24 Feb 07 02:11:10 PM PST 24 31467429270 ps
T826 /workspace/coverage/default/29.sram_ctrl_partial_access.103730764 Feb 07 02:03:49 PM PST 24 Feb 07 02:04:25 PM PST 24 2988014372 ps
T827 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3542443816 Feb 07 02:01:45 PM PST 24 Feb 07 02:01:52 PM PST 24 1413978022 ps
T828 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3393389264 Feb 07 02:08:31 PM PST 24 Feb 07 02:13:42 PM PST 24 14145327666 ps
T829 /workspace/coverage/default/22.sram_ctrl_max_throughput.1123900933 Feb 07 02:02:18 PM PST 24 Feb 07 02:05:29 PM PST 24 829373067 ps
T830 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2887637539 Feb 07 02:02:42 PM PST 24 Feb 07 02:03:29 PM PST 24 715759820 ps
T831 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1256534117 Feb 07 02:08:23 PM PST 24 Feb 07 03:25:46 PM PST 24 6140393133 ps
T832 /workspace/coverage/default/21.sram_ctrl_ram_cfg.2118117388 Feb 07 02:02:43 PM PST 24 Feb 07 02:03:00 PM PST 24 1401332615 ps
T833 /workspace/coverage/default/6.sram_ctrl_partial_access.3231239168 Feb 07 02:01:07 PM PST 24 Feb 07 02:01:21 PM PST 24 1513545159 ps
T834 /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1041207880 Feb 07 02:00:54 PM PST 24 Feb 07 02:19:04 PM PST 24 7256120679 ps
T835 /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2845605406 Feb 07 02:08:12 PM PST 24 Feb 07 02:08:39 PM PST 24 1429166221 ps
T836 /workspace/coverage/default/39.sram_ctrl_lc_escalation.1027072649 Feb 07 02:08:17 PM PST 24 Feb 07 02:10:46 PM PST 24 22796011038 ps
T837 /workspace/coverage/default/2.sram_ctrl_lc_escalation.1008209479 Feb 07 02:00:45 PM PST 24 Feb 07 02:02:57 PM PST 24 6202196556 ps
T838 /workspace/coverage/default/19.sram_ctrl_mem_walk.183106782 Feb 07 02:01:56 PM PST 24 Feb 07 02:06:40 PM PST 24 14177403365 ps
T839 /workspace/coverage/default/46.sram_ctrl_max_throughput.3466639188 Feb 07 02:09:01 PM PST 24 Feb 07 02:11:10 PM PST 24 797704711 ps
T840 /workspace/coverage/default/10.sram_ctrl_regwen.1654325955 Feb 07 02:01:18 PM PST 24 Feb 07 02:08:25 PM PST 24 34370965740 ps
T841 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3769305498 Feb 07 02:03:21 PM PST 24 Feb 07 02:07:14 PM PST 24 6009627050 ps
T842 /workspace/coverage/default/3.sram_ctrl_stress_all.1496863494 Feb 07 02:01:10 PM PST 24 Feb 07 02:33:15 PM PST 24 172416623332 ps
T843 /workspace/coverage/default/28.sram_ctrl_executable.705827549 Feb 07 02:03:55 PM PST 24 Feb 07 02:24:00 PM PST 24 105292769694 ps
T844 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2283707812 Feb 07 02:08:02 PM PST 24 Feb 07 02:09:08 PM PST 24 765822743 ps
T845 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.92039458 Feb 07 02:01:21 PM PST 24 Feb 07 02:16:25 PM PST 24 23337059377 ps
T846 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2533323009 Feb 07 02:00:41 PM PST 24 Feb 07 03:09:58 PM PST 24 3104841615 ps
T847 /workspace/coverage/default/44.sram_ctrl_regwen.3652143009 Feb 07 02:08:39 PM PST 24 Feb 07 02:45:57 PM PST 24 40181321894 ps
T848 /workspace/coverage/default/2.sram_ctrl_ram_cfg.2488144606 Feb 07 02:00:40 PM PST 24 Feb 07 02:00:55 PM PST 24 1407026642 ps
T849 /workspace/coverage/default/0.sram_ctrl_regwen.3217182580 Feb 07 02:00:51 PM PST 24 Feb 07 02:01:16 PM PST 24 3182764752 ps
T850 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2491802955 Feb 07 02:00:55 PM PST 24 Feb 07 02:02:17 PM PST 24 10665704492 ps
T851 /workspace/coverage/default/31.sram_ctrl_ram_cfg.1898521533 Feb 07 02:07:59 PM PST 24 Feb 07 02:08:06 PM PST 24 1532508738 ps
T852 /workspace/coverage/default/31.sram_ctrl_max_throughput.4212801782 Feb 07 02:08:04 PM PST 24 Feb 07 02:08:32 PM PST 24 3360907300 ps
T853 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1756783659 Feb 07 02:02:11 PM PST 24 Feb 07 02:07:12 PM PST 24 12482808781 ps
T854 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.622007710 Feb 07 02:01:45 PM PST 24 Feb 07 02:07:50 PM PST 24 6635458470 ps
T855 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3489553071 Feb 07 02:00:33 PM PST 24 Feb 07 02:04:35 PM PST 24 6215865300 ps
T856 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3561091828 Feb 07 02:08:14 PM PST 24 Feb 07 02:15:27 PM PST 24 51689108728 ps
T857 /workspace/coverage/default/35.sram_ctrl_smoke.1540018921 Feb 07 02:08:02 PM PST 24 Feb 07 02:08:34 PM PST 24 7567294506 ps
T858 /workspace/coverage/default/26.sram_ctrl_mem_walk.1900612002 Feb 07 02:03:21 PM PST 24 Feb 07 02:05:58 PM PST 24 44879330074 ps
T859 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1866081260 Feb 07 02:04:06 PM PST 24 Feb 07 02:04:35 PM PST 24 691800197 ps
T860 /workspace/coverage/default/26.sram_ctrl_max_throughput.3322786226 Feb 07 02:03:20 PM PST 24 Feb 07 02:04:25 PM PST 24 727834215 ps
T861 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.669602009 Feb 07 02:08:00 PM PST 24 Feb 07 02:14:31 PM PST 24 8326189975 ps
T862 /workspace/coverage/default/40.sram_ctrl_max_throughput.119947091 Feb 07 02:08:18 PM PST 24 Feb 07 02:09:37 PM PST 24 1520487585 ps
T863 /workspace/coverage/default/40.sram_ctrl_alert_test.2698482017 Feb 07 02:08:29 PM PST 24 Feb 07 02:08:30 PM PST 24 12231047 ps
T864 /workspace/coverage/default/28.sram_ctrl_regwen.1840787847 Feb 07 02:03:51 PM PST 24 Feb 07 02:05:26 PM PST 24 2271124201 ps
T865 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3365456147 Feb 07 02:01:17 PM PST 24 Feb 07 02:03:52 PM PST 24 834970455 ps
T866 /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3339399371 Feb 07 02:03:49 PM PST 24 Feb 07 03:40:47 PM PST 24 4214111755 ps
T867 /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3585710344 Feb 07 02:02:24 PM PST 24 Feb 07 02:03:44 PM PST 24 4004945765 ps
T868 /workspace/coverage/default/33.sram_ctrl_regwen.1313833574 Feb 07 02:08:01 PM PST 24 Feb 07 02:16:36 PM PST 24 12810851554 ps
T869 /workspace/coverage/default/46.sram_ctrl_ram_cfg.1083122428 Feb 07 02:09:15 PM PST 24 Feb 07 02:09:22 PM PST 24 434238989 ps
T870 /workspace/coverage/default/46.sram_ctrl_lc_escalation.464797125 Feb 07 02:09:12 PM PST 24 Feb 07 02:13:10 PM PST 24 20641684515 ps
T871 /workspace/coverage/default/28.sram_ctrl_partial_access.73851362 Feb 07 02:03:38 PM PST 24 Feb 07 02:04:16 PM PST 24 985166865 ps
T872 /workspace/coverage/default/6.sram_ctrl_alert_test.3979496730 Feb 07 02:01:04 PM PST 24 Feb 07 02:01:05 PM PST 24 39774738 ps
T873 /workspace/coverage/default/32.sram_ctrl_bijection.552221455 Feb 07 02:07:59 PM PST 24 Feb 07 02:40:38 PM PST 24 488961243928 ps
T874 /workspace/coverage/default/44.sram_ctrl_ram_cfg.373676546 Feb 07 02:08:38 PM PST 24 Feb 07 02:08:53 PM PST 24 826705968 ps
T875 /workspace/coverage/default/17.sram_ctrl_multiple_keys.4035155525 Feb 07 02:01:37 PM PST 24 Feb 07 02:14:24 PM PST 24 36827427619 ps
T876 /workspace/coverage/default/28.sram_ctrl_multiple_keys.3229785613 Feb 07 02:03:39 PM PST 24 Feb 07 02:16:01 PM PST 24 78690025173 ps
T877 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2662681397 Feb 07 02:01:30 PM PST 24 Feb 07 02:05:19 PM PST 24 39388269139 ps
T878 /workspace/coverage/default/11.sram_ctrl_alert_test.3681741118 Feb 07 02:01:23 PM PST 24 Feb 07 02:01:25 PM PST 24 22294601 ps
T879 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1360882352 Feb 07 02:01:38 PM PST 24 Feb 07 02:22:34 PM PST 24 29646435393 ps
T880 /workspace/coverage/default/29.sram_ctrl_max_throughput.3759017298 Feb 07 02:04:03 PM PST 24 Feb 07 02:04:47 PM PST 24 6346766006 ps
T881 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.4105191755 Feb 07 02:01:01 PM PST 24 Feb 07 02:05:40 PM PST 24 14301101714 ps
T882 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3354119266 Feb 07 02:01:32 PM PST 24 Feb 07 02:48:31 PM PST 24 1355770577 ps
T883 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3379888966 Feb 07 02:07:59 PM PST 24 Feb 07 02:15:03 PM PST 24 23637519949 ps
T884 /workspace/coverage/default/37.sram_ctrl_max_throughput.4229854122 Feb 07 02:08:11 PM PST 24 Feb 07 02:10:59 PM PST 24 1593503879 ps
T885 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3435477443 Feb 07 02:01:59 PM PST 24 Feb 07 02:06:48 PM PST 24 11066030932 ps
T886 /workspace/coverage/default/41.sram_ctrl_alert_test.1746472228 Feb 07 02:08:16 PM PST 24 Feb 07 02:08:17 PM PST 24 19437765 ps
T887 /workspace/coverage/default/22.sram_ctrl_ram_cfg.1469467606 Feb 07 02:02:39 PM PST 24 Feb 07 02:02:48 PM PST 24 1398246442 ps
T888 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2233300256 Feb 07 02:08:18 PM PST 24 Feb 07 02:11:06 PM PST 24 2602676480 ps
T889 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1330002451 Feb 07 02:08:04 PM PST 24 Feb 07 02:09:18 PM PST 24 3773962507 ps
T890 /workspace/coverage/default/8.sram_ctrl_lc_escalation.1474155230 Feb 07 02:01:00 PM PST 24 Feb 07 02:02:10 PM PST 24 4312938053 ps
T891 /workspace/coverage/default/13.sram_ctrl_multiple_keys.3960348505 Feb 07 02:01:32 PM PST 24 Feb 07 02:23:47 PM PST 24 38420653190 ps
T892 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2755075632 Feb 07 02:01:19 PM PST 24 Feb 07 02:03:45 PM PST 24 4419099872 ps
T893 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2966720473 Feb 07 02:09:51 PM PST 24 Feb 07 02:12:22 PM PST 24 8706495519 ps
T894 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.985395195 Feb 07 02:08:13 PM PST 24 Feb 07 02:15:11 PM PST 24 5044890371 ps
T895 /workspace/coverage/default/42.sram_ctrl_smoke.3611589179 Feb 07 02:08:16 PM PST 24 Feb 07 02:08:27 PM PST 24 453825700 ps
T896 /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2757702503 Feb 07 02:01:09 PM PST 24 Feb 07 02:06:48 PM PST 24 17568237285 ps
T897 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1265197573 Feb 07 02:01:31 PM PST 24 Feb 07 02:03:48 PM PST 24 3188969145 ps
T898 /workspace/coverage/default/0.sram_ctrl_mem_walk.3385390938 Feb 07 02:00:39 PM PST 24 Feb 07 02:04:54 PM PST 24 8387177965 ps
T899 /workspace/coverage/default/38.sram_ctrl_multiple_keys.807816255 Feb 07 02:08:14 PM PST 24 Feb 07 02:33:44 PM PST 24 18452759895 ps
T900 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2212833167 Feb 07 02:07:57 PM PST 24 Feb 07 02:12:35 PM PST 24 3745771836 ps
T901 /workspace/coverage/default/5.sram_ctrl_alert_test.2803601766 Feb 07 02:01:01 PM PST 24 Feb 07 02:01:04 PM PST 24 24018159 ps
T902 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1638955763 Feb 07 02:02:18 PM PST 24 Feb 07 02:05:08 PM PST 24 8747575595 ps
T903 /workspace/coverage/default/44.sram_ctrl_lc_escalation.3918230698 Feb 07 02:08:29 PM PST 24 Feb 07 02:11:00 PM PST 24 31950338679 ps
T904 /workspace/coverage/default/30.sram_ctrl_ram_cfg.2885728207 Feb 07 02:07:57 PM PST 24 Feb 07 02:08:03 PM PST 24 347018362 ps
T905 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1611276121 Feb 07 02:01:21 PM PST 24 Feb 07 02:02:42 PM PST 24 2665369086 ps
T906 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3760416681 Feb 07 02:01:35 PM PST 24 Feb 07 02:01:42 PM PST 24 742818774 ps
T907 /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1169788823 Feb 07 02:03:24 PM PST 24 Feb 07 02:04:46 PM PST 24 2701228820 ps
T908 /workspace/coverage/default/21.sram_ctrl_multiple_keys.2516746637 Feb 07 02:02:22 PM PST 24 Feb 07 02:03:44 PM PST 24 819673577 ps
T909 /workspace/coverage/default/23.sram_ctrl_ram_cfg.3222213028 Feb 07 02:02:38 PM PST 24 Feb 07 02:02:56 PM PST 24 1091813247 ps
T910 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.648710 Feb 07 02:01:20 PM PST 24 Feb 07 02:02:14 PM PST 24 7223094367 ps
T911 /workspace/coverage/default/35.sram_ctrl_max_throughput.1901884032 Feb 07 02:08:04 PM PST 24 Feb 07 02:09:03 PM PST 24 1997981787 ps
T912 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3902777583 Feb 07 02:01:22 PM PST 24 Feb 07 02:07:42 PM PST 24 12632760013 ps
T913 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3305653893 Feb 07 02:01:16 PM PST 24 Feb 07 02:03:37 PM PST 24 6007066706 ps
T914 /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3156739393 Feb 07 02:07:59 PM PST 24 Feb 07 02:10:45 PM PST 24 3718454901 ps
T915 /workspace/coverage/default/9.sram_ctrl_regwen.3650108693 Feb 07 02:01:15 PM PST 24 Feb 07 02:18:00 PM PST 24 10634114680 ps
T916 /workspace/coverage/default/21.sram_ctrl_partial_access.2340104663 Feb 07 02:02:27 PM PST 24 Feb 07 02:02:47 PM PST 24 382050064 ps
T917 /workspace/coverage/default/19.sram_ctrl_alert_test.3069853886 Feb 07 02:02:12 PM PST 24 Feb 07 02:02:33 PM PST 24 23392825 ps
T918 /workspace/coverage/default/44.sram_ctrl_alert_test.2857058386 Feb 07 02:08:48 PM PST 24 Feb 07 02:08:50 PM PST 24 45049445 ps
T919 /workspace/coverage/default/27.sram_ctrl_max_throughput.1228811790 Feb 07 02:03:27 PM PST 24 Feb 07 02:06:17 PM PST 24 1912378060 ps
T920 /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1245876639 Feb 07 02:01:51 PM PST 24 Feb 07 02:07:30 PM PST 24 4848476849 ps
T921 /workspace/coverage/default/21.sram_ctrl_alert_test.578234337 Feb 07 02:02:23 PM PST 24 Feb 07 02:02:32 PM PST 24 12894842 ps
T922 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4243346293 Feb 07 02:04:04 PM PST 24 Feb 07 02:09:29 PM PST 24 12641127605 ps
T923 /workspace/coverage/default/28.sram_ctrl_smoke.3098955849 Feb 07 02:03:39 PM PST 24 Feb 07 02:04:04 PM PST 24 20957238670 ps
T924 /workspace/coverage/default/18.sram_ctrl_multiple_keys.2658013356 Feb 07 02:01:46 PM PST 24 Feb 07 02:24:19 PM PST 24 18426537130 ps
T925 /workspace/coverage/default/6.sram_ctrl_stress_pipeline.4061643873 Feb 07 02:01:09 PM PST 24 Feb 07 02:05:30 PM PST 24 3262175384 ps
T926 /workspace/coverage/default/46.sram_ctrl_multiple_keys.2855319357 Feb 07 02:09:01 PM PST 24 Feb 07 02:22:12 PM PST 24 15351958662 ps
T927 /workspace/coverage/default/12.sram_ctrl_stress_all.2456011580 Feb 07 02:01:25 PM PST 24 Feb 07 02:45:28 PM PST 24 105430234757 ps
T928 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.335343999 Feb 07 02:09:20 PM PST 24 Feb 07 02:11:09 PM PST 24 1592155377 ps
T929 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3417495987 Feb 07 02:00:53 PM PST 24 Feb 07 02:03:04 PM PST 24 836410447 ps
T930 /workspace/coverage/default/6.sram_ctrl_bijection.3735790273 Feb 07 02:01:12 PM PST 24 Feb 07 02:17:43 PM PST 24 15059850784 ps
T931 /workspace/coverage/default/42.sram_ctrl_max_throughput.3649988933 Feb 07 02:08:17 PM PST 24 Feb 07 02:08:53 PM PST 24 5346024500 ps
T932 /workspace/coverage/default/6.sram_ctrl_multiple_keys.2807572194 Feb 07 02:01:06 PM PST 24 Feb 07 02:08:40 PM PST 24 27707026533 ps
T933 /workspace/coverage/default/4.sram_ctrl_multiple_keys.3740542776 Feb 07 02:00:54 PM PST 24 Feb 07 02:20:06 PM PST 24 19324435237 ps
T934 /workspace/coverage/default/1.sram_ctrl_multiple_keys.2185735620 Feb 07 02:00:50 PM PST 24 Feb 07 02:10:49 PM PST 24 20809822152 ps
T935 /workspace/coverage/default/15.sram_ctrl_mem_walk.394359357 Feb 07 02:01:34 PM PST 24 Feb 07 02:04:09 PM PST 24 79483241698 ps
T936 /workspace/coverage/default/25.sram_ctrl_mem_walk.555447193 Feb 07 02:03:22 PM PST 24 Feb 07 02:05:33 PM PST 24 8233403892 ps
T937 /workspace/coverage/default/18.sram_ctrl_mem_walk.3847215579 Feb 07 02:01:48 PM PST 24 Feb 07 02:07:24 PM PST 24 114574276515 ps
T938 /workspace/coverage/default/46.sram_ctrl_alert_test.1522873872 Feb 07 02:09:11 PM PST 24 Feb 07 02:09:12 PM PST 24 15147379 ps
T939 /workspace/coverage/default/22.sram_ctrl_stress_all.1466548439 Feb 07 02:02:40 PM PST 24 Feb 07 02:55:42 PM PST 24 359013558381 ps
T940 /workspace/coverage/default/42.sram_ctrl_partial_access.938993331 Feb 07 02:08:19 PM PST 24 Feb 07 02:10:23 PM PST 24 532069674 ps
T941 /workspace/coverage/default/7.sram_ctrl_alert_test.3854018224 Feb 07 02:01:02 PM PST 24 Feb 07 02:01:04 PM PST 24 37922147 ps
T942 /workspace/coverage/default/9.sram_ctrl_partial_access.787192027 Feb 07 02:01:21 PM PST 24 Feb 07 02:01:52 PM PST 24 3854982845 ps
T943 /workspace/coverage/default/24.sram_ctrl_alert_test.820142748 Feb 07 02:02:55 PM PST 24 Feb 07 02:02:57 PM PST 24 12944403 ps
T944 /workspace/coverage/default/21.sram_ctrl_max_throughput.783841253 Feb 07 02:02:19 PM PST 24 Feb 07 02:03:36 PM PST 24 2988220032 ps
T945 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2628584320 Feb 07 02:09:37 PM PST 24 Feb 07 02:15:22 PM PST 24 5052093153 ps
T946 /workspace/coverage/default/31.sram_ctrl_lc_escalation.2978236431 Feb 07 02:07:57 PM PST 24 Feb 07 02:10:57 PM PST 24 32697836307 ps
T947 /workspace/coverage/default/49.sram_ctrl_regwen.1904410263 Feb 07 02:09:47 PM PST 24 Feb 07 02:20:58 PM PST 24 29315650751 ps
T948 /workspace/coverage/default/43.sram_ctrl_ram_cfg.275669259 Feb 07 02:08:20 PM PST 24 Feb 07 02:08:28 PM PST 24 1294268688 ps
T949 /workspace/coverage/default/11.sram_ctrl_lc_escalation.392785011 Feb 07 02:01:14 PM PST 24 Feb 07 02:01:30 PM PST 24 2317495515 ps
T950 /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.495703108 Feb 07 02:08:33 PM PST 24 Feb 07 03:25:48 PM PST 24 560789464 ps
T951 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.754205326 Feb 07 02:07:57 PM PST 24 Feb 07 02:10:42 PM PST 24 27261193188 ps
T952 /workspace/coverage/default/23.sram_ctrl_smoke.283983113 Feb 07 02:02:37 PM PST 24 Feb 07 02:02:54 PM PST 24 6991500874 ps
T953 /workspace/coverage/default/41.sram_ctrl_mem_walk.3345644288 Feb 07 02:08:16 PM PST 24 Feb 07 02:10:49 PM PST 24 43025791464 ps
T954 /workspace/coverage/default/38.sram_ctrl_smoke.3758102121 Feb 07 02:08:11 PM PST 24 Feb 07 02:08:23 PM PST 24 1246138189 ps
T955 /workspace/coverage/default/3.sram_ctrl_max_throughput.3181000383 Feb 07 02:00:56 PM PST 24 Feb 07 02:01:58 PM PST 24 732019033 ps
T956 /workspace/coverage/default/41.sram_ctrl_partial_access.2530112948 Feb 07 02:08:28 PM PST 24 Feb 07 02:08:42 PM PST 24 488794595 ps
T957 /workspace/coverage/default/47.sram_ctrl_regwen.532491471 Feb 07 02:09:21 PM PST 24 Feb 07 02:16:01 PM PST 24 6151567317 ps
T958 /workspace/coverage/default/32.sram_ctrl_ram_cfg.4122934431 Feb 07 02:07:59 PM PST 24 Feb 07 02:08:13 PM PST 24 357051063 ps
T959 /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4174944535 Feb 07 02:00:46 PM PST 24 Feb 07 02:31:26 PM PST 24 1805980375 ps
T960 /workspace/coverage/default/49.sram_ctrl_partial_access.3752784476 Feb 07 02:09:37 PM PST 24 Feb 07 02:10:24 PM PST 24 972413860 ps
T961 /workspace/coverage/default/34.sram_ctrl_smoke.2724799479 Feb 07 02:08:00 PM PST 24 Feb 07 02:09:29 PM PST 24 859068753 ps

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1815915232
Short name T5
Test name
Test status
Simulation time 32604298971 ps
CPU time 354.85 seconds
Started Feb 07 02:08:05 PM PST 24
Finished Feb 07 02:14:02 PM PST 24
Peak memory 201868 kb
Host smart-0817b503-3ab7-4e97-bc62-2515f39a5ae7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815915232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.1815915232
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.1979444356
Short name T125
Test name
Test status
Simulation time 431822514996 ps
CPU time 5738.97 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 03:43:54 PM PST 24
Peak memory 387244 kb
Host smart-c339069e-1351-4418-a92e-08635385e120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979444356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.1979444356
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.853269534
Short name T33
Test name
Test status
Simulation time 1547503005 ps
CPU time 9180.75 seconds
Started Feb 07 02:08:49 PM PST 24
Finished Feb 07 04:41:51 PM PST 24
Peak memory 456008 kb
Host smart-8c967f26-932c-4f87-bf76-4adc2e74f4ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=853269534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.853269534
Directory /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3031637968
Short name T36
Test name
Test status
Simulation time 819060240 ps
CPU time 2.25 seconds
Started Feb 07 01:57:01 PM PST 24
Finished Feb 07 01:57:06 PM PST 24
Peak memory 202772 kb
Host smart-a0864628-d465-46ad-becf-7ba3f5be908b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031637968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.3031637968
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.265424876
Short name T21
Test name
Test status
Simulation time 187518008 ps
CPU time 2.7 seconds
Started Feb 07 02:00:55 PM PST 24
Finished Feb 07 02:00:59 PM PST 24
Peak memory 221908 kb
Host smart-9eba6a11-e1a9-4299-b360-cc76fe76064a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265424876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_sec_cm.265424876
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2974564589
Short name T25
Test name
Test status
Simulation time 44769542266 ps
CPU time 4948.47 seconds
Started Feb 07 02:08:17 PM PST 24
Finished Feb 07 03:30:47 PM PST 24
Peak memory 570636 kb
Host smart-538f5f84-bf20-478d-b2ff-9a462bb01d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2974564589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.2974564589
Directory /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.456857315
Short name T1
Test name
Test status
Simulation time 1565301488 ps
CPU time 133.98 seconds
Started Feb 07 02:01:23 PM PST 24
Finished Feb 07 02:03:38 PM PST 24
Peak memory 214064 kb
Host smart-67e8dcc9-f816-4eb4-a8e5-d33e0f0ef84c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456857315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.sram_ctrl_mem_partial_access.456857315
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1675017177
Short name T65
Test name
Test status
Simulation time 34391928 ps
CPU time 0.66 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:18 PM PST 24
Peak memory 202576 kb
Host smart-795194a5-b0aa-4b12-8031-3133c1f938fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675017177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.1675017177
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.3036908170
Short name T143
Test name
Test status
Simulation time 349206944 ps
CPU time 5.42 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:03:27 PM PST 24
Peak memory 202328 kb
Host smart-421a8a13-393e-4564-b080-cc9e9f9c2a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036908170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3036908170
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2774710718
Short name T121
Test name
Test status
Simulation time 521430272 ps
CPU time 2.07 seconds
Started Feb 07 01:56:51 PM PST 24
Finished Feb 07 01:56:59 PM PST 24
Peak memory 202768 kb
Host smart-4c1e4c33-adfd-43bc-be6a-247853517d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774710718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.2774710718
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.320972141
Short name T127
Test name
Test status
Simulation time 258942184900 ps
CPU time 6968.45 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 04:04:33 PM PST 24
Peak memory 388184 kb
Host smart-14d33f53-7530-4313-854d-cebee3a410d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320972141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_stress_all.320972141
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3135719721
Short name T17
Test name
Test status
Simulation time 3814412586 ps
CPU time 652.84 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:19:06 PM PST 24
Peak memory 372980 kb
Host smart-ac3e8511-24ee-47d5-984f-cd36a6906fe1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135719721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.3135719721
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.1018770960
Short name T26
Test name
Test status
Simulation time 14603558789 ps
CPU time 300.46 seconds
Started Feb 07 02:01:29 PM PST 24
Finished Feb 07 02:06:30 PM PST 24
Peak memory 367692 kb
Host smart-b5cfd256-2e85-4fa8-bb38-2b05d4e9bfe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018770960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1018770960
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1381621300
Short name T119
Test name
Test status
Simulation time 68033984 ps
CPU time 1.43 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 202816 kb
Host smart-5fa5930b-426e-4c9e-9116-b702006b53a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381621300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1381621300
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.3499730548
Short name T253
Test name
Test status
Simulation time 19946896 ps
CPU time 0.65 seconds
Started Feb 07 02:01:34 PM PST 24
Finished Feb 07 02:01:35 PM PST 24
Peak memory 201812 kb
Host smart-5a678bf4-48ee-4222-814b-6fc9d5693a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499730548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.3499730548
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1145957817
Short name T115
Test name
Test status
Simulation time 442591559 ps
CPU time 2.09 seconds
Started Feb 07 01:56:44 PM PST 24
Finished Feb 07 01:56:50 PM PST 24
Peak memory 202812 kb
Host smart-8c6281b5-77b1-4985-9880-359c9b3cf68d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145957817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1145957817
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3140202190
Short name T118
Test name
Test status
Simulation time 369776494 ps
CPU time 2.43 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 202864 kb
Host smart-a91394d1-fdf5-4ab2-ab0e-964efc99041e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140202190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.3140202190
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.1509042683
Short name T454
Test name
Test status
Simulation time 17045498098 ps
CPU time 163.48 seconds
Started Feb 07 02:00:39 PM PST 24
Finished Feb 07 02:03:24 PM PST 24
Peak memory 210320 kb
Host smart-2a1c6c86-e237-41e1-976f-c4ea40916a18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509042683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.1509042683
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3201074304
Short name T83
Test name
Test status
Simulation time 53668291 ps
CPU time 0.66 seconds
Started Feb 07 01:56:51 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 201868 kb
Host smart-717b371b-832f-44c7-bdf3-ef82a5beb178
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201074304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.3201074304
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1815372032
Short name T183
Test name
Test status
Simulation time 41736003 ps
CPU time 0.72 seconds
Started Feb 07 01:56:44 PM PST 24
Finished Feb 07 01:56:48 PM PST 24
Peak memory 202640 kb
Host smart-c54b21e7-072a-459c-8a36-d79ccb23dfea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815372032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.1815372032
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1319359797
Short name T154
Test name
Test status
Simulation time 191843609 ps
CPU time 1.47 seconds
Started Feb 07 01:56:44 PM PST 24
Finished Feb 07 01:56:49 PM PST 24
Peak memory 202792 kb
Host smart-b683706d-7113-43f7-813f-50efb717c640
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319359797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.1319359797
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4072525501
Short name T68
Test name
Test status
Simulation time 13330776 ps
CPU time 0.65 seconds
Started Feb 07 01:56:46 PM PST 24
Finished Feb 07 01:56:49 PM PST 24
Peak memory 201952 kb
Host smart-bf830733-8359-4a10-a7fd-0a7d8bfaad29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072525501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.4072525501
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.736885611
Short name T57
Test name
Test status
Simulation time 1345423877 ps
CPU time 5.18 seconds
Started Feb 07 01:56:43 PM PST 24
Finished Feb 07 01:56:53 PM PST 24
Peak memory 202908 kb
Host smart-572e54bc-a08d-42c1-bffe-31c18ad3a7e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736885611 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.736885611
Directory /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.734174206
Short name T82
Test name
Test status
Simulation time 22692148 ps
CPU time 0.66 seconds
Started Feb 07 01:56:46 PM PST 24
Finished Feb 07 01:56:49 PM PST 24
Peak memory 202632 kb
Host smart-5e4a9727-8837-4a12-90f3-d68ec0e7cbb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734174206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.sram_ctrl_csr_rw.734174206
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3991412925
Short name T104
Test name
Test status
Simulation time 67708803 ps
CPU time 0.76 seconds
Started Feb 07 01:56:44 PM PST 24
Finished Feb 07 01:56:48 PM PST 24
Peak memory 202424 kb
Host smart-fe53b2be-bfe8-43fb-a4b5-795b611ea043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991412925 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3991412925
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2199770152
Short name T70
Test name
Test status
Simulation time 35168795 ps
CPU time 1.66 seconds
Started Feb 07 01:56:44 PM PST 24
Finished Feb 07 01:56:49 PM PST 24
Peak memory 202812 kb
Host smart-17231288-a9d4-4378-b0f5-8de556a9c078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199770152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.2199770152
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.891347683
Short name T184
Test name
Test status
Simulation time 112406388 ps
CPU time 0.74 seconds
Started Feb 07 01:56:49 PM PST 24
Finished Feb 07 01:56:53 PM PST 24
Peak memory 202596 kb
Host smart-25ef627f-7681-4922-8423-c88970a4a299
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891347683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_aliasing.891347683
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.575328401
Short name T108
Test name
Test status
Simulation time 93901457 ps
CPU time 1.46 seconds
Started Feb 07 01:56:51 PM PST 24
Finished Feb 07 01:56:58 PM PST 24
Peak memory 202776 kb
Host smart-d1e88146-02e3-4925-8f7c-721b351ea7ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575328401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_bit_bash.575328401
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1662206242
Short name T192
Test name
Test status
Simulation time 43991547 ps
CPU time 0.67 seconds
Started Feb 07 01:56:43 PM PST 24
Finished Feb 07 01:56:48 PM PST 24
Peak memory 202644 kb
Host smart-cc6a5776-04ee-47ae-ac2e-62b382146ee4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662206242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1662206242
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2527447794
Short name T158
Test name
Test status
Simulation time 729891433 ps
CPU time 14.36 seconds
Started Feb 07 01:56:52 PM PST 24
Finished Feb 07 01:57:11 PM PST 24
Peak memory 210988 kb
Host smart-32c72fa8-b481-40dc-a31d-88129f99d770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527447794 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2527447794
Directory /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3474782344
Short name T198
Test name
Test status
Simulation time 22116908 ps
CPU time 0.64 seconds
Started Feb 07 01:56:49 PM PST 24
Finished Feb 07 01:56:56 PM PST 24
Peak memory 202464 kb
Host smart-435045eb-8474-406b-a412-016219f8e637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474782344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.3474782344
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.30366576
Short name T160
Test name
Test status
Simulation time 20657977 ps
CPU time 0.68 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 202136 kb
Host smart-a5c51e1c-c9b5-444a-811a-cd02515e809d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30366576 -assert nopostproc +UVM_TESTNAME=sram_ctr
l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.30366576
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.130803134
Short name T194
Test name
Test status
Simulation time 206325930 ps
CPU time 2.17 seconds
Started Feb 07 01:56:52 PM PST 24
Finished Feb 07 01:57:00 PM PST 24
Peak memory 202980 kb
Host smart-b5a9ad32-ff24-4eaa-a068-3231e5019979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130803134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_tl_errors.130803134
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1935949240
Short name T148
Test name
Test status
Simulation time 288773553 ps
CPU time 2.69 seconds
Started Feb 07 01:57:01 PM PST 24
Finished Feb 07 01:57:06 PM PST 24
Peak memory 202888 kb
Host smart-8121e853-1079-4714-87db-614e22f5fa5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935949240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.1935949240
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3727871497
Short name T182
Test name
Test status
Simulation time 1301217728 ps
CPU time 5.84 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:23 PM PST 24
Peak memory 211080 kb
Host smart-43ef1878-7e18-43d0-83d9-3c02992627b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727871497 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3727871497
Directory /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1969749622
Short name T166
Test name
Test status
Simulation time 16517594 ps
CPU time 0.68 seconds
Started Feb 07 01:57:01 PM PST 24
Finished Feb 07 01:57:04 PM PST 24
Peak memory 201956 kb
Host smart-4b7ac94c-880c-4313-b9ae-83cc4a56521c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969749622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.1969749622
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3533438936
Short name T202
Test name
Test status
Simulation time 65246012 ps
CPU time 0.75 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:16 PM PST 24
Peak memory 202624 kb
Host smart-9707a094-2359-4f16-893f-2f288f85b987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533438936 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3533438936
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.916896454
Short name T151
Test name
Test status
Simulation time 37937745 ps
CPU time 3.37 seconds
Started Feb 07 01:56:58 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 202836 kb
Host smart-720da63d-97e5-4d0f-b92b-8d811eb23a90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916896454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_tl_errors.916896454
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2112534699
Short name T122
Test name
Test status
Simulation time 715706163 ps
CPU time 2.13 seconds
Started Feb 07 01:57:05 PM PST 24
Finished Feb 07 01:57:08 PM PST 24
Peak memory 202800 kb
Host smart-ca5716b0-52c5-4de6-bc45-1bf2af9f2eba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112534699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.2112534699
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2827846902
Short name T205
Test name
Test status
Simulation time 1387654759 ps
CPU time 5.42 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:21 PM PST 24
Peak memory 211080 kb
Host smart-e2af11f3-f773-449f-81c9-26e27055f719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827846902 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2827846902
Directory /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2597578914
Short name T181
Test name
Test status
Simulation time 68937685 ps
CPU time 0.76 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:15 PM PST 24
Peak memory 202628 kb
Host smart-8cb55ad5-29d5-4f17-a913-96c5ffab81d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597578914 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.2597578914
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1355966131
Short name T58
Test name
Test status
Simulation time 38621898 ps
CPU time 1.7 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202860 kb
Host smart-0b36e0ee-1a58-41f3-8e2f-8819184815e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355966131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.1355966131
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3261605560
Short name T61
Test name
Test status
Simulation time 611332873 ps
CPU time 1.7 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 202760 kb
Host smart-eaf8aea7-0ab2-4592-b676-cf543a18900b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261605560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.3261605560
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.270024946
Short name T172
Test name
Test status
Simulation time 2250460697 ps
CPU time 4.39 seconds
Started Feb 07 01:57:13 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202924 kb
Host smart-df9964be-cace-44ed-a56b-949616d4af7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270024946 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.270024946
Directory /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3929425871
Short name T75
Test name
Test status
Simulation time 24966604 ps
CPU time 0.65 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:16 PM PST 24
Peak memory 202652 kb
Host smart-9d9657da-1d43-443f-a525-d152258d0b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929425871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.3929425871
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2911579267
Short name T92
Test name
Test status
Simulation time 89714697 ps
CPU time 0.71 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202672 kb
Host smart-ecf83ad8-2eeb-4956-8418-5c5ae503d83b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911579267 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2911579267
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3390942403
Short name T79
Test name
Test status
Simulation time 77685923 ps
CPU time 2.4 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 202760 kb
Host smart-38cf7ccc-f167-4bf2-9519-5685aa87399c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390942403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.3390942403
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2484238330
Short name T199
Test name
Test status
Simulation time 322821666 ps
CPU time 1.49 seconds
Started Feb 07 01:57:13 PM PST 24
Finished Feb 07 01:57:16 PM PST 24
Peak memory 202824 kb
Host smart-1c4d81fe-b75a-4bb0-9521-01b97cb43ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484238330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.2484238330
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.776165677
Short name T113
Test name
Test status
Simulation time 353153634 ps
CPU time 14.08 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:33 PM PST 24
Peak memory 211008 kb
Host smart-7d5a2c31-f05c-4311-aa71-359bd8587d6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776165677 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.776165677
Directory /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1701098540
Short name T190
Test name
Test status
Simulation time 45231925 ps
CPU time 0.64 seconds
Started Feb 07 01:57:13 PM PST 24
Finished Feb 07 01:57:15 PM PST 24
Peak memory 201864 kb
Host smart-4938a15a-5537-4b8b-87f4-24b9b57ca0ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701098540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1701098540
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.293563665
Short name T203
Test name
Test status
Simulation time 44900115 ps
CPU time 0.79 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:15 PM PST 24
Peak memory 202624 kb
Host smart-3aad86f1-16d8-4134-8ae8-e96fd83ea45a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293563665 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.293563665
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1833735362
Short name T72
Test name
Test status
Simulation time 134690617 ps
CPU time 4.63 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:22 PM PST 24
Peak memory 202852 kb
Host smart-d7cdd883-6cd0-4dff-af6a-679226e249c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833735362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.1833735362
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1536524276
Short name T63
Test name
Test status
Simulation time 187624244 ps
CPU time 1.54 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:18 PM PST 24
Peak memory 211084 kb
Host smart-cc7c9694-7849-44c6-bfcf-f6d248d97ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536524276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.1536524276
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1975362846
Short name T54
Test name
Test status
Simulation time 725647214 ps
CPU time 5.75 seconds
Started Feb 07 01:57:13 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 211216 kb
Host smart-8a66d47d-da10-40f2-9963-a13c12d1259d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975362846 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1975362846
Directory /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.520776706
Short name T109
Test name
Test status
Simulation time 37202532 ps
CPU time 0.67 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 201888 kb
Host smart-58d7100d-a225-4b3f-adf2-63bd18332825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520776706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.sram_ctrl_csr_rw.520776706
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2291073093
Short name T35
Test name
Test status
Simulation time 14503721 ps
CPU time 0.71 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:18 PM PST 24
Peak memory 202644 kb
Host smart-cb879da2-e158-44a0-9c0e-1002738619cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291073093 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2291073093
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3079543896
Short name T197
Test name
Test status
Simulation time 168976537 ps
CPU time 2.42 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 202836 kb
Host smart-8d4b999e-a5c5-4046-94f5-33abb5b40cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079543896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.3079543896
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4242730376
Short name T120
Test name
Test status
Simulation time 165324840 ps
CPU time 2.02 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202832 kb
Host smart-92e41ec9-a862-48dc-a0ba-8f96244135b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242730376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.4242730376
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4243945690
Short name T170
Test name
Test status
Simulation time 2873043444 ps
CPU time 6.7 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:21 PM PST 24
Peak memory 211192 kb
Host smart-aa2fa21a-a856-4b58-9ac9-b0805c8f81e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243945690 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.4243945690
Directory /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3271651471
Short name T161
Test name
Test status
Simulation time 17617975 ps
CPU time 0.66 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 201896 kb
Host smart-7aafe4fe-6043-49b1-82de-374facc92289
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271651471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.3271651471
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4144134613
Short name T66
Test name
Test status
Simulation time 165196395 ps
CPU time 0.83 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:18 PM PST 24
Peak memory 202664 kb
Host smart-3f88ca09-8abb-4199-9a40-2fc75fddc440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144134613 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.4144134613
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3128137776
Short name T99
Test name
Test status
Simulation time 90096089 ps
CPU time 2.99 seconds
Started Feb 07 01:57:12 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 202784 kb
Host smart-91b8d224-99d8-40ae-89ad-5b9d61a1573f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128137776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.3128137776
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3815728519
Short name T37
Test name
Test status
Simulation time 186233940 ps
CPU time 2.31 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 202776 kb
Host smart-87ad59b3-821b-473f-9fd4-be93e8c959d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815728519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.3815728519
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1198164150
Short name T153
Test name
Test status
Simulation time 4913801861 ps
CPU time 5.14 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 211164 kb
Host smart-b62d97c3-5254-4f7c-bcdf-fdbd1234051c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198164150 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.1198164150
Directory /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.338490801
Short name T193
Test name
Test status
Simulation time 45846847 ps
CPU time 0.66 seconds
Started Feb 07 01:57:12 PM PST 24
Finished Feb 07 01:57:13 PM PST 24
Peak memory 202280 kb
Host smart-ae11038d-d6b4-4789-a594-579d5b8f6d29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338490801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_csr_rw.338490801
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2469597783
Short name T200
Test name
Test status
Simulation time 80576061 ps
CPU time 0.88 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202632 kb
Host smart-0d951df5-662e-48ad-97de-84264d955d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469597783 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.2469597783
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1040656189
Short name T62
Test name
Test status
Simulation time 140567882 ps
CPU time 4.64 seconds
Started Feb 07 01:57:12 PM PST 24
Finished Feb 07 01:57:18 PM PST 24
Peak memory 202804 kb
Host smart-841e9d13-1279-4852-92b9-a377343a4c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040656189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.1040656189
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1011353769
Short name T163
Test name
Test status
Simulation time 429443005 ps
CPU time 6.09 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:25 PM PST 24
Peak memory 211100 kb
Host smart-41d00909-c5a0-4ff6-b562-255d6c9f6328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011353769 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1011353769
Directory /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1895022655
Short name T73
Test name
Test status
Simulation time 36299859 ps
CPU time 0.63 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 201776 kb
Host smart-aa57372e-a845-410d-a3fb-8b136444f7ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895022655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.1895022655
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2771348263
Short name T177
Test name
Test status
Simulation time 40571950 ps
CPU time 0.69 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202624 kb
Host smart-bdd9092d-871b-4223-ba1e-274e669ac9f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771348263 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.2771348263
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2214038289
Short name T171
Test name
Test status
Simulation time 49600754 ps
CPU time 2.06 seconds
Started Feb 07 01:57:13 PM PST 24
Finished Feb 07 01:57:16 PM PST 24
Peak memory 202892 kb
Host smart-62104457-6e8a-4106-a404-a94e861284a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214038289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.2214038289
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3506841849
Short name T117
Test name
Test status
Simulation time 991729844 ps
CPU time 2.34 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202884 kb
Host smart-deea9d43-22cf-4529-bce6-9a80d8e3f22d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506841849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.3506841849
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2544121979
Short name T165
Test name
Test status
Simulation time 715084668 ps
CPU time 13.79 seconds
Started Feb 07 01:57:16 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 211016 kb
Host smart-488213b6-5004-4182-b100-0ba09ede43bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544121979 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2544121979
Directory /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2204202615
Short name T169
Test name
Test status
Simulation time 22401822 ps
CPU time 0.65 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:17 PM PST 24
Peak memory 201776 kb
Host smart-b7046cec-fb59-4e6d-bcae-1bfc219fc9c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204202615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.2204202615
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1252434918
Short name T67
Test name
Test status
Simulation time 27483108 ps
CPU time 0.73 seconds
Started Feb 07 01:57:14 PM PST 24
Finished Feb 07 01:57:16 PM PST 24
Peak memory 202660 kb
Host smart-0eab1404-0ea8-4a08-901d-7e59f623a32c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252434918 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.1252434918
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.856140662
Short name T55
Test name
Test status
Simulation time 25977019 ps
CPU time 2.53 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 211000 kb
Host smart-69fc5a8e-905d-48d0-a37d-992d20ab13dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856140662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_tl_errors.856140662
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4204350515
Short name T173
Test name
Test status
Simulation time 5902376896 ps
CPU time 6.61 seconds
Started Feb 07 01:57:31 PM PST 24
Finished Feb 07 01:57:39 PM PST 24
Peak memory 211172 kb
Host smart-a544c00a-8313-49da-b8e2-7cee3ed45992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204350515 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.4204350515
Directory /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1985860148
Short name T76
Test name
Test status
Simulation time 32445304 ps
CPU time 0.71 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202120 kb
Host smart-1882db52-8a64-4c74-a110-c5b0e27ab18e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985860148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_csr_rw.1985860148
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.4183249596
Short name T96
Test name
Test status
Simulation time 53337328 ps
CPU time 0.74 seconds
Started Feb 07 01:57:27 PM PST 24
Finished Feb 07 01:57:29 PM PST 24
Peak memory 202468 kb
Host smart-644ea7ed-2397-489d-a50b-31ac88640446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183249596 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.4183249596
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.945161490
Short name T204
Test name
Test status
Simulation time 157584504 ps
CPU time 2.09 seconds
Started Feb 07 01:57:15 PM PST 24
Finished Feb 07 01:57:19 PM PST 24
Peak memory 202840 kb
Host smart-3f9c275a-b7a6-4e1c-bd30-88fb02eeef87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945161490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_tl_errors.945161490
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1152050919
Short name T191
Test name
Test status
Simulation time 537337852 ps
CPU time 1.57 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 202816 kb
Host smart-787c1ae0-35d9-4e77-9be0-fa32beef3cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152050919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.1152050919
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3329648959
Short name T149
Test name
Test status
Simulation time 59873362 ps
CPU time 0.74 seconds
Started Feb 07 01:57:04 PM PST 24
Finished Feb 07 01:57:06 PM PST 24
Peak memory 202192 kb
Host smart-3de175a0-b66a-4c38-9f4a-366c8e773308
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329648959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.3329648959
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3816398962
Short name T156
Test name
Test status
Simulation time 374604374 ps
CPU time 1.31 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 202368 kb
Host smart-ffa32660-7472-4e84-8c21-5d1fbb0216db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816398962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.3816398962
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2146585816
Short name T80
Test name
Test status
Simulation time 45965044 ps
CPU time 0.65 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 202036 kb
Host smart-b880c545-8398-4597-a650-e8c420bcc399
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146585816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.2146585816
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1759092131
Short name T174
Test name
Test status
Simulation time 357556224 ps
CPU time 4.52 seconds
Started Feb 07 01:57:06 PM PST 24
Finished Feb 07 01:57:11 PM PST 24
Peak memory 202944 kb
Host smart-466e479f-688f-4491-9e3a-dfd3c6baea6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759092131 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.1759092131
Directory /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.701000700
Short name T159
Test name
Test status
Simulation time 33018066 ps
CPU time 0.67 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 202672 kb
Host smart-d00e7e5c-5ec7-4c64-b398-7e2abbc6ffe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701000700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_csr_rw.701000700
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3003652239
Short name T103
Test name
Test status
Simulation time 88624240 ps
CPU time 0.8 seconds
Started Feb 07 01:56:52 PM PST 24
Finished Feb 07 01:56:59 PM PST 24
Peak memory 202640 kb
Host smart-ee88f9dd-30d3-481b-9692-229f7c66f6e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003652239 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3003652239
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3504421496
Short name T71
Test name
Test status
Simulation time 1375139944 ps
CPU time 4.56 seconds
Started Feb 07 01:56:56 PM PST 24
Finished Feb 07 01:57:03 PM PST 24
Peak memory 211024 kb
Host smart-b68c1be5-8e4d-4dcf-90c9-ea15be1b644e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504421496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.3504421496
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3840605029
Short name T123
Test name
Test status
Simulation time 573235244 ps
CPU time 2.57 seconds
Started Feb 07 01:56:57 PM PST 24
Finished Feb 07 01:57:02 PM PST 24
Peak memory 202836 kb
Host smart-75e8d1bb-dc0c-456c-8695-36fcbc16a45f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840605029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.3840605029
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1394059070
Short name T94
Test name
Test status
Simulation time 246256673 ps
CPU time 2.07 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:58 PM PST 24
Peak memory 202796 kb
Host smart-0f8ba1d0-6c88-4df2-9dd0-c6f64d612164
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394059070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1394059070
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3767520957
Short name T188
Test name
Test status
Simulation time 32060562 ps
CPU time 0.73 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 202556 kb
Host smart-81854380-66fa-4776-9c15-c31750d08f78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767520957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.3767520957
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.482657251
Short name T195
Test name
Test status
Simulation time 1430743193 ps
CPU time 4.65 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:57:01 PM PST 24
Peak memory 202852 kb
Host smart-db1018c7-0e62-4b54-a521-d18b75407426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482657251 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.482657251
Directory /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3210238329
Short name T196
Test name
Test status
Simulation time 41283146 ps
CPU time 0.63 seconds
Started Feb 07 01:56:53 PM PST 24
Finished Feb 07 01:56:59 PM PST 24
Peak memory 201872 kb
Host smart-6bfa9de1-fc53-4dd1-a86e-45819e16524b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210238329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.3210238329
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3916994936
Short name T168
Test name
Test status
Simulation time 50438118 ps
CPU time 0.68 seconds
Started Feb 07 01:56:56 PM PST 24
Finished Feb 07 01:56:59 PM PST 24
Peak memory 202636 kb
Host smart-81691bed-18eb-4101-9e9c-b63529c693d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916994936 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.3916994936
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1706165984
Short name T98
Test name
Test status
Simulation time 191258929 ps
CPU time 1.99 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:58 PM PST 24
Peak memory 202840 kb
Host smart-042ff1a2-c72c-4fab-92cc-1f7871a3c87d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706165984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.1706165984
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1929907635
Short name T52
Test name
Test status
Simulation time 175735802 ps
CPU time 1.7 seconds
Started Feb 07 01:56:51 PM PST 24
Finished Feb 07 01:56:58 PM PST 24
Peak memory 202772 kb
Host smart-d4adb2e1-3675-4a0f-9121-39a5c2d01263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929907635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.1929907635
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3485632937
Short name T78
Test name
Test status
Simulation time 21084662 ps
CPU time 0.76 seconds
Started Feb 07 01:56:52 PM PST 24
Finished Feb 07 01:56:58 PM PST 24
Peak memory 202128 kb
Host smart-8f641055-4d10-44d2-9744-424994371e3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485632937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.3485632937
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2052586781
Short name T147
Test name
Test status
Simulation time 63914367 ps
CPU time 1.36 seconds
Started Feb 07 01:57:03 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 202356 kb
Host smart-98795b47-d748-4dde-bd40-3f7c16029ec6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052586781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.2052586781
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4224139057
Short name T69
Test name
Test status
Simulation time 16101463 ps
CPU time 0.73 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 202580 kb
Host smart-54e83bd7-2b23-4f6a-920c-a6c921319231
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224139057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.4224139057
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3256018995
Short name T175
Test name
Test status
Simulation time 6816221665 ps
CPU time 8.29 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 211124 kb
Host smart-ddc88f9f-a83e-4223-9353-dd482ae09501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256018995 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3256018995
Directory /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2423545795
Short name T93
Test name
Test status
Simulation time 108545156 ps
CPU time 0.65 seconds
Started Feb 07 01:56:53 PM PST 24
Finished Feb 07 01:56:59 PM PST 24
Peak memory 202164 kb
Host smart-cc877563-d0e6-4bd0-911f-eedc927718d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423545795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.2423545795
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3577783068
Short name T64
Test name
Test status
Simulation time 18975680 ps
CPU time 0.73 seconds
Started Feb 07 01:56:49 PM PST 24
Finished Feb 07 01:56:53 PM PST 24
Peak memory 202620 kb
Host smart-94df447e-12a0-4a7f-bc30-a95432a09297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577783068 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3577783068
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3530499544
Short name T167
Test name
Test status
Simulation time 404438706 ps
CPU time 3.07 seconds
Started Feb 07 01:57:04 PM PST 24
Finished Feb 07 01:57:08 PM PST 24
Peak memory 202908 kb
Host smart-3be67f42-22fc-4600-a274-191b118dc93b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530499544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.3530499544
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2292155819
Short name T189
Test name
Test status
Simulation time 349400624 ps
CPU time 5.89 seconds
Started Feb 07 01:57:02 PM PST 24
Finished Feb 07 01:57:10 PM PST 24
Peak memory 202900 kb
Host smart-aeef3027-bd0b-43b7-adbc-8deaaf526ffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292155819 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2292155819
Directory /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2543852641
Short name T102
Test name
Test status
Simulation time 24619959 ps
CPU time 0.67 seconds
Started Feb 07 01:56:51 PM PST 24
Finished Feb 07 01:56:57 PM PST 24
Peak memory 201720 kb
Host smart-87636bc3-7713-4597-ae9d-6c50c45c3e86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543852641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.2543852641
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3327011268
Short name T185
Test name
Test status
Simulation time 17938963 ps
CPU time 0.71 seconds
Started Feb 07 01:57:00 PM PST 24
Finished Feb 07 01:57:03 PM PST 24
Peak memory 202580 kb
Host smart-feba8cf0-79a6-4d92-b11f-3afd705579b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327011268 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.3327011268
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1872656069
Short name T95
Test name
Test status
Simulation time 355872252 ps
CPU time 2.64 seconds
Started Feb 07 01:56:52 PM PST 24
Finished Feb 07 01:56:59 PM PST 24
Peak memory 202732 kb
Host smart-db55cd5c-ca39-49f6-bdc4-2e60fae98d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872656069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.1872656069
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.903747379
Short name T112
Test name
Test status
Simulation time 136697094 ps
CPU time 2.04 seconds
Started Feb 07 01:56:50 PM PST 24
Finished Feb 07 01:56:58 PM PST 24
Peak memory 202844 kb
Host smart-78443cbc-b0eb-4362-9a59-e895fc671cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903747379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.sram_ctrl_tl_intg_err.903747379
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.155024316
Short name T53
Test name
Test status
Simulation time 349062061 ps
CPU time 5.75 seconds
Started Feb 07 01:57:01 PM PST 24
Finished Feb 07 01:57:09 PM PST 24
Peak memory 211164 kb
Host smart-4595e3ea-34b7-407e-9b04-1ca3085a2349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155024316 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.155024316
Directory /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3506262069
Short name T77
Test name
Test status
Simulation time 12663277 ps
CPU time 0.65 seconds
Started Feb 07 01:56:59 PM PST 24
Finished Feb 07 01:57:02 PM PST 24
Peak memory 202132 kb
Host smart-66b5469f-115e-4ab1-8bc2-07eae12caa2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506262069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3506262069
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.536260281
Short name T176
Test name
Test status
Simulation time 22877841 ps
CPU time 0.81 seconds
Started Feb 07 01:57:12 PM PST 24
Finished Feb 07 01:57:13 PM PST 24
Peak memory 202108 kb
Host smart-de69d864-19c5-4c3d-99be-5973b8711d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536260281 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.536260281
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.616996605
Short name T157
Test name
Test status
Simulation time 36332583 ps
CPU time 3.47 seconds
Started Feb 07 01:57:00 PM PST 24
Finished Feb 07 01:57:06 PM PST 24
Peak memory 211044 kb
Host smart-f826f7bd-0785-4909-b150-8d4689a4f16c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616996605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_tl_errors.616996605
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1380827970
Short name T91
Test name
Test status
Simulation time 580741499 ps
CPU time 2.55 seconds
Started Feb 07 01:57:00 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 201960 kb
Host smart-3ac5f2ad-6428-4f0b-9b5e-938b7ad61c31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380827970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.1380827970
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3618009579
Short name T178
Test name
Test status
Simulation time 1199379364 ps
CPU time 5.11 seconds
Started Feb 07 01:57:03 PM PST 24
Finished Feb 07 01:57:09 PM PST 24
Peak memory 202836 kb
Host smart-d2a12b9f-20c0-4fd3-8a58-c0fa2f7e3ddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618009579 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3618009579
Directory /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1571583048
Short name T155
Test name
Test status
Simulation time 12052704 ps
CPU time 0.64 seconds
Started Feb 07 01:56:57 PM PST 24
Finished Feb 07 01:57:00 PM PST 24
Peak memory 202372 kb
Host smart-51a88ef2-5a2b-402d-b1f4-80d024a3b0fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571583048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1571583048
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3958442105
Short name T201
Test name
Test status
Simulation time 17435360 ps
CPU time 0.72 seconds
Started Feb 07 01:57:12 PM PST 24
Finished Feb 07 01:57:13 PM PST 24
Peak memory 202040 kb
Host smart-e432691f-1f99-439c-a4d9-1c2bcb2b2f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958442105 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3958442105
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3109017819
Short name T179
Test name
Test status
Simulation time 31637148 ps
CPU time 2.38 seconds
Started Feb 07 01:57:00 PM PST 24
Finished Feb 07 01:57:04 PM PST 24
Peak memory 201924 kb
Host smart-bf6cfac8-633d-4810-a9e6-80b0d672dadd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109017819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.3109017819
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.830582611
Short name T187
Test name
Test status
Simulation time 360266011 ps
CPU time 13.34 seconds
Started Feb 07 01:57:12 PM PST 24
Finished Feb 07 01:57:26 PM PST 24
Peak memory 211032 kb
Host smart-a69a38f1-fc37-4680-b479-69bdf0e1b69c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830582611 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.830582611
Directory /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4246355919
Short name T180
Test name
Test status
Simulation time 15444946 ps
CPU time 0.67 seconds
Started Feb 07 01:56:58 PM PST 24
Finished Feb 07 01:57:01 PM PST 24
Peak memory 201836 kb
Host smart-09b7d576-44c3-482a-89a6-db4268f118ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246355919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.4246355919
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2334826012
Short name T97
Test name
Test status
Simulation time 47015198 ps
CPU time 0.71 seconds
Started Feb 07 01:56:58 PM PST 24
Finished Feb 07 01:57:02 PM PST 24
Peak memory 202676 kb
Host smart-63c0c906-f98a-4e56-a474-e6bed6214e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334826012 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.2334826012
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.301718146
Short name T150
Test name
Test status
Simulation time 109120318 ps
CPU time 3.24 seconds
Started Feb 07 01:56:59 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 202828 kb
Host smart-b85d0a57-bff1-47d3-9c85-73ceb45d3a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301718146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_tl_errors.301718146
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.538078480
Short name T116
Test name
Test status
Simulation time 74893045 ps
CPU time 1.34 seconds
Started Feb 07 01:57:01 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 202840 kb
Host smart-a728966a-1275-47d8-ae52-aec11e1a6f59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538078480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.sram_ctrl_tl_intg_err.538078480
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3063797838
Short name T164
Test name
Test status
Simulation time 713407766 ps
CPU time 6.84 seconds
Started Feb 07 01:57:00 PM PST 24
Finished Feb 07 01:57:09 PM PST 24
Peak memory 211104 kb
Host smart-5b95de70-1d2d-40b0-b865-25ab30601148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063797838 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3063797838
Directory /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1132168657
Short name T162
Test name
Test status
Simulation time 13542985 ps
CPU time 0.68 seconds
Started Feb 07 01:57:00 PM PST 24
Finished Feb 07 01:57:03 PM PST 24
Peak memory 201876 kb
Host smart-f5e4034c-960d-449c-98b3-247ca1017fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132168657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.1132168657
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2856476016
Short name T186
Test name
Test status
Simulation time 16074990 ps
CPU time 0.71 seconds
Started Feb 07 01:57:03 PM PST 24
Finished Feb 07 01:57:05 PM PST 24
Peak memory 202632 kb
Host smart-befda46e-0e79-4cd2-9f3a-9eb1d1ec4775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856476016 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2856476016
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.664036958
Short name T56
Test name
Test status
Simulation time 602525156 ps
CPU time 3.92 seconds
Started Feb 07 01:57:01 PM PST 24
Finished Feb 07 01:57:06 PM PST 24
Peak memory 202816 kb
Host smart-c188390e-06c7-43cc-b757-a6822c46124f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664036958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_tl_errors.664036958
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3705675217
Short name T152
Test name
Test status
Simulation time 309680126 ps
CPU time 1.58 seconds
Started Feb 07 01:57:01 PM PST 24
Finished Feb 07 01:57:04 PM PST 24
Peak memory 202820 kb
Host smart-a3a602c7-d3ba-46cd-8b88-1a94a67624fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705675217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.3705675217
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3519037946
Short name T568
Test name
Test status
Simulation time 54543367491 ps
CPU time 692.95 seconds
Started Feb 07 02:00:38 PM PST 24
Finished Feb 07 02:12:11 PM PST 24
Peak memory 377084 kb
Host smart-d620b6c7-3b85-4ff2-988a-9db9d7c91475
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519037946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.3519037946
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.2666340099
Short name T395
Test name
Test status
Simulation time 22414763 ps
CPU time 0.66 seconds
Started Feb 07 02:00:39 PM PST 24
Finished Feb 07 02:00:41 PM PST 24
Peak memory 201848 kb
Host smart-51394b52-d372-4d37-891c-beb35142729c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666340099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.2666340099
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.1110699467
Short name T214
Test name
Test status
Simulation time 26565770018 ps
CPU time 1797.99 seconds
Started Feb 07 02:00:35 PM PST 24
Finished Feb 07 02:30:34 PM PST 24
Peak memory 202188 kb
Host smart-c590eb56-5ba0-4928-bb63-f86eece8cadd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110699467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
1110699467
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.987335068
Short name T255
Test name
Test status
Simulation time 757156858 ps
CPU time 61.24 seconds
Started Feb 07 02:00:33 PM PST 24
Finished Feb 07 02:01:35 PM PST 24
Peak memory 311540 kb
Host smart-64844ed7-5914-4f71-8583-116f75443479
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987335068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.sram_ctrl_max_throughput.987335068
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3715199585
Short name T742
Test name
Test status
Simulation time 29409917262 ps
CPU time 84.45 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:02:06 PM PST 24
Peak memory 212268 kb
Host smart-2a19e18c-ae11-452a-8d0d-e618cb713032
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715199585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.3715199585
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.3385390938
Short name T898
Test name
Test status
Simulation time 8387177965 ps
CPU time 253.69 seconds
Started Feb 07 02:00:39 PM PST 24
Finished Feb 07 02:04:54 PM PST 24
Peak memory 202216 kb
Host smart-e9a79db3-79c0-4f32-b4ef-adf5f273f943
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385390938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.3385390938
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.6630777
Short name T370
Test name
Test status
Simulation time 9398802966 ps
CPU time 589.1 seconds
Started Feb 07 02:00:39 PM PST 24
Finished Feb 07 02:10:29 PM PST 24
Peak memory 373944 kb
Host smart-bdf633ce-a80b-4b68-a694-a1da51057755
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6630777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multipl
e_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_
keys.6630777
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.2535386003
Short name T597
Test name
Test status
Simulation time 547816966 ps
CPU time 24.19 seconds
Started Feb 07 02:00:51 PM PST 24
Finished Feb 07 02:01:17 PM PST 24
Peak memory 202148 kb
Host smart-ea6784d9-fdaa-4bb4-929e-3f9e077c14ee
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535386003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.2535386003
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.464824561
Short name T545
Test name
Test status
Simulation time 40068408187 ps
CPU time 323.92 seconds
Started Feb 07 02:00:33 PM PST 24
Finished Feb 07 02:05:58 PM PST 24
Peak memory 202232 kb
Host smart-69524ce3-3b43-4fe1-bd87-932d2cfe33a0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464824561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.sram_ctrl_partial_access_b2b.464824561
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.2555721752
Short name T686
Test name
Test status
Simulation time 1409717538 ps
CPU time 13.7 seconds
Started Feb 07 02:00:47 PM PST 24
Finished Feb 07 02:01:08 PM PST 24
Peak memory 202392 kb
Host smart-68fcebc4-3749-4c5c-8493-9ec3d1343ca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555721752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2555721752
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.3217182580
Short name T849
Test name
Test status
Simulation time 3182764752 ps
CPU time 22.87 seconds
Started Feb 07 02:00:51 PM PST 24
Finished Feb 07 02:01:16 PM PST 24
Peak memory 207288 kb
Host smart-21e88625-c929-4cd1-9fd2-fe1ef108774d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217182580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3217182580
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.2885270189
Short name T42
Test name
Test status
Simulation time 1056435753 ps
CPU time 3.02 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:00:44 PM PST 24
Peak memory 221004 kb
Host smart-c34ec158-ac43-45f1-9a2f-d8539e9d24c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885270189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.2885270189
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.2472286490
Short name T641
Test name
Test status
Simulation time 1016620046 ps
CPU time 21.53 seconds
Started Feb 07 02:00:45 PM PST 24
Finished Feb 07 02:01:08 PM PST 24
Peak memory 201840 kb
Host smart-5cf6925e-19d8-4021-9fa6-539c43e396cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472286490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2472286490
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4174944535
Short name T959
Test name
Test status
Simulation time 1805980375 ps
CPU time 1838.64 seconds
Started Feb 07 02:00:46 PM PST 24
Finished Feb 07 02:31:26 PM PST 24
Peak memory 757628 kb
Host smart-82ca5aff-faaf-4ec4-843f-a27ecae0ab71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4174944535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.4174944535
Directory /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3489553071
Short name T855
Test name
Test status
Simulation time 6215865300 ps
CPU time 240.67 seconds
Started Feb 07 02:00:33 PM PST 24
Finished Feb 07 02:04:35 PM PST 24
Peak memory 210456 kb
Host smart-fb4e5299-d1ce-42bb-87d7-7a4499efdf8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489553071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.3489553071
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4149713126
Short name T414
Test name
Test status
Simulation time 1120072693 ps
CPU time 47.01 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:01:28 PM PST 24
Peak memory 272584 kb
Host smart-361afa12-fb2b-4499-82b7-dc25b658d14a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149713126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.4149713126
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2317006914
Short name T636
Test name
Test status
Simulation time 12346351724 ps
CPU time 2048.49 seconds
Started Feb 07 02:00:41 PM PST 24
Finished Feb 07 02:34:52 PM PST 24
Peak memory 376036 kb
Host smart-fae1ced0-fad0-48f6-a299-67ad85c0c2aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317006914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2317006914
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.773877011
Short name T437
Test name
Test status
Simulation time 34163780 ps
CPU time 0.62 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:00:53 PM PST 24
Peak memory 201900 kb
Host smart-1be9283f-5999-44a3-a4fa-9456e8ca272e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773877011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.773877011
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.2101995778
Short name T224
Test name
Test status
Simulation time 195320997739 ps
CPU time 1829 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:31:22 PM PST 24
Peak memory 202216 kb
Host smart-3bf3cfb8-3ddc-46a4-9fad-d698931c79db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101995778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2101995778
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.435277362
Short name T499
Test name
Test status
Simulation time 76307154363 ps
CPU time 264.39 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:05:17 PM PST 24
Peak memory 214456 kb
Host smart-e6c88206-6488-40d7-ba3f-c7d8c1b430d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435277362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esca
lation.435277362
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.3660536558
Short name T704
Test name
Test status
Simulation time 1499329688 ps
CPU time 43.02 seconds
Started Feb 07 02:00:41 PM PST 24
Finished Feb 07 02:01:26 PM PST 24
Peak memory 256684 kb
Host smart-b1466eb2-6cc7-4f97-b5a9-63de231d0fc9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660536558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.3660536558
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2518030422
Short name T763
Test name
Test status
Simulation time 4545322852 ps
CPU time 153.76 seconds
Started Feb 07 02:00:47 PM PST 24
Finished Feb 07 02:03:25 PM PST 24
Peak memory 218520 kb
Host smart-0b8671eb-4a3a-4c96-b8fc-e7ad8752bc71
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518030422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.2518030422
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.78854118
Short name T247
Test name
Test status
Simulation time 9548640159 ps
CPU time 148.48 seconds
Started Feb 07 02:00:46 PM PST 24
Finished Feb 07 02:03:16 PM PST 24
Peak memory 202236 kb
Host smart-66440723-4684-4f6b-91eb-6b7ed432df3a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78854118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_m
em_walk.78854118
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2185735620
Short name T934
Test name
Test status
Simulation time 20809822152 ps
CPU time 596.57 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:10:49 PM PST 24
Peak memory 379088 kb
Host smart-016fe9be-abed-4b93-889c-eb69e1f64bf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185735620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2185735620
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.3692563544
Short name T311
Test name
Test status
Simulation time 707360942 ps
CPU time 12.42 seconds
Started Feb 07 02:00:43 PM PST 24
Finished Feb 07 02:00:56 PM PST 24
Peak memory 202148 kb
Host smart-e45d7c02-c4eb-49aa-9303-4c46df740750
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692563544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.3692563544
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.331744286
Short name T586
Test name
Test status
Simulation time 79040975512 ps
CPU time 481.1 seconds
Started Feb 07 02:00:33 PM PST 24
Finished Feb 07 02:08:35 PM PST 24
Peak memory 202144 kb
Host smart-4529dca1-a8c9-4d1a-ae86-a9caa009875a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331744286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.sram_ctrl_partial_access_b2b.331744286
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1854823574
Short name T343
Test name
Test status
Simulation time 349657294 ps
CPU time 6.81 seconds
Started Feb 07 02:00:45 PM PST 24
Finished Feb 07 02:00:54 PM PST 24
Peak memory 202356 kb
Host smart-49436614-d7dd-4335-96b3-d3c7fd918770
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854823574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1854823574
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3043533149
Short name T355
Test name
Test status
Simulation time 2980991646 ps
CPU time 89.82 seconds
Started Feb 07 02:00:44 PM PST 24
Finished Feb 07 02:02:15 PM PST 24
Peak memory 310328 kb
Host smart-c8cb82b8-97f5-47d8-9a32-9b2f5cf6a75b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043533149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3043533149
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.1209546101
Short name T41
Test name
Test status
Simulation time 210972594 ps
CPU time 2.15 seconds
Started Feb 07 02:00:45 PM PST 24
Finished Feb 07 02:00:49 PM PST 24
Peak memory 223856 kb
Host smart-441b56b5-1367-45b0-a912-bb4d33cf528e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209546101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_sec_cm.1209546101
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.1538517432
Short name T216
Test name
Test status
Simulation time 3221228926 ps
CPU time 133.94 seconds
Started Feb 07 02:00:47 PM PST 24
Finished Feb 07 02:03:05 PM PST 24
Peak memory 370772 kb
Host smart-12f97ba2-5963-4235-8f95-6b75c088cf95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538517432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1538517432
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2533323009
Short name T846
Test name
Test status
Simulation time 3104841615 ps
CPU time 4155.47 seconds
Started Feb 07 02:00:41 PM PST 24
Finished Feb 07 03:09:58 PM PST 24
Peak memory 521524 kb
Host smart-424ab432-e4ca-4ec5-9b86-ae50a8c5f8ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2533323009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.2533323009
Directory /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2064519299
Short name T719
Test name
Test status
Simulation time 18803654151 ps
CPU time 327.06 seconds
Started Feb 07 02:00:37 PM PST 24
Finished Feb 07 02:06:04 PM PST 24
Peak memory 202244 kb
Host smart-41add239-999c-4e81-9148-118233e9e331
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064519299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.2064519299
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1887069167
Short name T210
Test name
Test status
Simulation time 3793653352 ps
CPU time 55.91 seconds
Started Feb 07 02:00:49 PM PST 24
Finished Feb 07 02:01:49 PM PST 24
Peak memory 275016 kb
Host smart-f1cc7843-04ea-4d81-8325-d3f442311255
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887069167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1887069167
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.92039458
Short name T845
Test name
Test status
Simulation time 23337059377 ps
CPU time 903.68 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:16:25 PM PST 24
Peak memory 375984 kb
Host smart-73f5f710-fe9b-4c90-b7b5-1d5730b9bae2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92039458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.sram_ctrl_access_during_key_req.92039458
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.3036856844
Short name T422
Test name
Test status
Simulation time 15367816 ps
CPU time 0.63 seconds
Started Feb 07 02:01:18 PM PST 24
Finished Feb 07 02:01:20 PM PST 24
Peak memory 201884 kb
Host smart-00caea9b-00a3-405b-9569-ff325c1e9814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036856844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.3036856844
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.561229712
Short name T319
Test name
Test status
Simulation time 73132387386 ps
CPU time 1098.05 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:19:33 PM PST 24
Peak memory 202212 kb
Host smart-25095937-32b0-4fc6-90ee-b0c90b3d4379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561229712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.
561229712
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.1354653592
Short name T783
Test name
Test status
Simulation time 36239228046 ps
CPU time 1090.07 seconds
Started Feb 07 02:01:22 PM PST 24
Finished Feb 07 02:19:33 PM PST 24
Peak memory 376064 kb
Host smart-4dc0e7ac-43bc-44e2-b715-fa26eea0c1a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354653592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.1354653592
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.1342471182
Short name T114
Test name
Test status
Simulation time 28538567651 ps
CPU time 87.81 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:02:45 PM PST 24
Peak memory 210380 kb
Host smart-eb2d8974-be97-4c87-bdf2-e0fb3e760f5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342471182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.1342471182
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.1751672599
Short name T300
Test name
Test status
Simulation time 771864740 ps
CPU time 135.12 seconds
Started Feb 07 02:01:23 PM PST 24
Finished Feb 07 02:03:39 PM PST 24
Peak memory 353416 kb
Host smart-a082d8aa-bc94-4ace-938b-9806e3dd4571
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751672599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.1751672599
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1611276121
Short name T905
Test name
Test status
Simulation time 2665369086 ps
CPU time 79.55 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:02:42 PM PST 24
Peak memory 211120 kb
Host smart-ef4a238e-a2f2-49ce-8e59-95d4cfa391d2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611276121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.1611276121
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.3386390620
Short name T245
Test name
Test status
Simulation time 3943919277 ps
CPU time 249.05 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:05:24 PM PST 24
Peak memory 202192 kb
Host smart-d7aa6f23-04ef-427b-90ce-c8f816e0223c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386390620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.3386390620
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.2901583980
Short name T354
Test name
Test status
Simulation time 19250130665 ps
CPU time 1261.83 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:22:22 PM PST 24
Peak memory 378116 kb
Host smart-777d6c52-f022-4c3d-a894-e78813b1986d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901583980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.2901583980
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.2440341538
Short name T287
Test name
Test status
Simulation time 3061198303 ps
CPU time 83.04 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:02:40 PM PST 24
Peak memory 345312 kb
Host smart-c417946c-f0a2-4d2b-a745-c4842b1a4b4d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440341538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.2440341538
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2045408493
Short name T691
Test name
Test status
Simulation time 39991976534 ps
CPU time 239.05 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:05:19 PM PST 24
Peak memory 202136 kb
Host smart-c88109b3-cac1-4f24-9162-919794d4acbc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045408493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2045408493
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.1146854068
Short name T682
Test name
Test status
Simulation time 774979313 ps
CPU time 13.34 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:01:33 PM PST 24
Peak memory 202376 kb
Host smart-2325f2c8-c7c3-49e3-a3fd-3a0fe737780c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146854068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1146854068
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1654325955
Short name T840
Test name
Test status
Simulation time 34370965740 ps
CPU time 426.02 seconds
Started Feb 07 02:01:18 PM PST 24
Finished Feb 07 02:08:25 PM PST 24
Peak memory 377892 kb
Host smart-94593672-8da7-4660-bb86-c8266b2fe88e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654325955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1654325955
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.3476475730
Short name T714
Test name
Test status
Simulation time 3594187275 ps
CPU time 16.32 seconds
Started Feb 07 02:01:22 PM PST 24
Finished Feb 07 02:01:39 PM PST 24
Peak memory 202112 kb
Host smart-e83118c6-7e0f-41ad-9706-f8d71cd40e81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476475730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3476475730
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2337647156
Short name T611
Test name
Test status
Simulation time 4552061253 ps
CPU time 3974.8 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 03:07:35 PM PST 24
Peak memory 555784 kb
Host smart-ccab89cb-181f-4deb-8d5b-f28a97d54b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2337647156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2337647156
Directory /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1922796503
Short name T3
Test name
Test status
Simulation time 34781871140 ps
CPU time 460.91 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:09:01 PM PST 24
Peak memory 202216 kb
Host smart-5e12d498-2128-414f-af39-6ac7f42048e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922796503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.1922796503
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3559606007
Short name T267
Test name
Test status
Simulation time 3133670758 ps
CPU time 184.26 seconds
Started Feb 07 02:01:20 PM PST 24
Finished Feb 07 02:04:25 PM PST 24
Peak memory 366780 kb
Host smart-032cf2aa-c296-4cca-97e8-4bb869c80fb8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559606007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3559606007
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3328551767
Short name T434
Test name
Test status
Simulation time 7469039478 ps
CPU time 701.79 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:12:58 PM PST 24
Peak memory 360160 kb
Host smart-1cd1a869-6ff3-4fb4-acf1-e9de1f49ad44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328551767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.3328551767
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.3681741118
Short name T878
Test name
Test status
Simulation time 22294601 ps
CPU time 0.65 seconds
Started Feb 07 02:01:23 PM PST 24
Finished Feb 07 02:01:25 PM PST 24
Peak memory 201872 kb
Host smart-6e4ca157-82d1-4d61-a0bb-b58026a0678b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681741118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.3681741118
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.569639969
Short name T666
Test name
Test status
Simulation time 56285674052 ps
CPU time 1014.91 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:18:17 PM PST 24
Peak memory 202272 kb
Host smart-601e28ab-b193-413f-a0ef-a674779e90ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569639969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.
569639969
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.2592323043
Short name T639
Test name
Test status
Simulation time 37757448643 ps
CPU time 1055.63 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:18:58 PM PST 24
Peak memory 368664 kb
Host smart-fd81a9d5-2360-4b5d-9d23-e40148d09593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592323043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.2592323043
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.392785011
Short name T949
Test name
Test status
Simulation time 2317495515 ps
CPU time 15.45 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:01:30 PM PST 24
Peak memory 210360 kb
Host smart-d370eed4-57d1-4d25-8803-52b7056f9519
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392785011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_esc
alation.392785011
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.1621819343
Short name T420
Test name
Test status
Simulation time 10079528517 ps
CPU time 49.08 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:02:04 PM PST 24
Peak memory 270688 kb
Host smart-8fde309d-9741-402e-9f95-b31b8e80abb6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621819343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.1621819343
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3305653893
Short name T913
Test name
Test status
Simulation time 6007066706 ps
CPU time 140.62 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:03:37 PM PST 24
Peak memory 211004 kb
Host smart-9d4fc2d2-0c28-4d94-b858-7a2d0289043f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305653893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.3305653893
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.2458641436
Short name T301
Test name
Test status
Simulation time 4032344743 ps
CPU time 124.62 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:03:27 PM PST 24
Peak memory 202232 kb
Host smart-212f46f6-96aa-4d8e-bbed-e502d85451a7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458641436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.2458641436
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.3699248135
Short name T469
Test name
Test status
Simulation time 16426404946 ps
CPU time 144.57 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:03:46 PM PST 24
Peak memory 322520 kb
Host smart-ef5f5089-5a94-4508-953a-5ce3d13d28e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699248135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.3699248135
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.1607612823
Short name T346
Test name
Test status
Simulation time 844314272 ps
CPU time 17.01 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:01:34 PM PST 24
Peak memory 217532 kb
Host smart-15ce6b3f-c40b-41eb-9250-c4f4f856bb15
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607612823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.1607612823
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2653697168
Short name T633
Test name
Test status
Simulation time 38058213539 ps
CPU time 261.26 seconds
Started Feb 07 02:01:26 PM PST 24
Finished Feb 07 02:05:48 PM PST 24
Peak memory 202148 kb
Host smart-8a2d999c-eea7-455d-8ce6-c5aeb7adb3b5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653697168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 11.sram_ctrl_partial_access_b2b.2653697168
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.879238139
Short name T259
Test name
Test status
Simulation time 358829080 ps
CPU time 6.57 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:01:28 PM PST 24
Peak memory 202376 kb
Host smart-3671dcae-c6da-465d-95f8-d12d74d80fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879238139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.879238139
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.3357624690
Short name T622
Test name
Test status
Simulation time 100833657339 ps
CPU time 1182.06 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:20:57 PM PST 24
Peak memory 375024 kb
Host smart-55fe6741-238c-489d-9ebc-85f842a1961a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357624690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3357624690
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.4221065299
Short name T534
Test name
Test status
Simulation time 1205429941 ps
CPU time 12.71 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:01:34 PM PST 24
Peak memory 202044 kb
Host smart-02e3becc-676b-4b6b-8194-273b79676e5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221065299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.4221065299
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.2952031163
Short name T710
Test name
Test status
Simulation time 90126934301 ps
CPU time 2489.77 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:42:50 PM PST 24
Peak memory 376880 kb
Host smart-bf86893e-c6a9-4777-978a-89eaf3a0f020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952031163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.2952031163
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1989182735
Short name T528
Test name
Test status
Simulation time 7612778063 ps
CPU time 6220.65 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 03:45:01 PM PST 24
Peak memory 576020 kb
Host smart-e708c7ae-2f35-4c11-8a96-ccc9c8a076fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1989182735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1989182735
Directory /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3730092987
Short name T326
Test name
Test status
Simulation time 2717751083 ps
CPU time 209.25 seconds
Started Feb 07 02:01:22 PM PST 24
Finished Feb 07 02:04:52 PM PST 24
Peak memory 210448 kb
Host smart-a71990e0-1550-4a45-83eb-e94e126f1769
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730092987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.3730092987
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3365456147
Short name T865
Test name
Test status
Simulation time 834970455 ps
CPU time 154.32 seconds
Started Feb 07 02:01:17 PM PST 24
Finished Feb 07 02:03:52 PM PST 24
Peak memory 365688 kb
Host smart-06a7289f-e20f-4d70-90a9-4addaf010e8e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365456147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.3365456147
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1842711741
Short name T406
Test name
Test status
Simulation time 7919981455 ps
CPU time 367.09 seconds
Started Feb 07 02:01:23 PM PST 24
Finished Feb 07 02:07:31 PM PST 24
Peak memory 373996 kb
Host smart-b1ae3c7f-0a03-4fa2-b19e-55a5ad5633c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842711741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.1842711741
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3051945657
Short name T493
Test name
Test status
Simulation time 21074334 ps
CPU time 0.64 seconds
Started Feb 07 02:01:32 PM PST 24
Finished Feb 07 02:01:33 PM PST 24
Peak memory 201492 kb
Host smart-7cadb8d1-99b2-4109-a408-9b2dcadeb4c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051945657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3051945657
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.717536911
Short name T566
Test name
Test status
Simulation time 110492546251 ps
CPU time 2411.69 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:41:32 PM PST 24
Peak memory 202216 kb
Host smart-9adbb89c-b87f-43ae-8555-e7fa0571ad96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717536911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.
717536911
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.209125885
Short name T630
Test name
Test status
Simulation time 3336362628 ps
CPU time 40.1 seconds
Started Feb 07 02:01:25 PM PST 24
Finished Feb 07 02:02:06 PM PST 24
Peak memory 210388 kb
Host smart-767353b2-703e-4fe4-8886-f0f9b69e0b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209125885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc
alation.209125885
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.3228356886
Short name T721
Test name
Test status
Simulation time 1517975869 ps
CPU time 105.93 seconds
Started Feb 07 02:01:22 PM PST 24
Finished Feb 07 02:03:09 PM PST 24
Peak memory 331944 kb
Host smart-cd53dfe2-7c8d-4db0-a69d-4fef2740c0d3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228356886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.3228356886
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.3722984868
Short name T234
Test name
Test status
Simulation time 21079273438 ps
CPU time 294.2 seconds
Started Feb 07 02:01:20 PM PST 24
Finished Feb 07 02:06:15 PM PST 24
Peak memory 202252 kb
Host smart-05c1ed4e-0dc4-4130-8194-732ce5aa95c7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722984868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.3722984868
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.316657512
Short name T362
Test name
Test status
Simulation time 72989346682 ps
CPU time 1468.09 seconds
Started Feb 07 02:01:18 PM PST 24
Finished Feb 07 02:25:47 PM PST 24
Peak memory 374992 kb
Host smart-2c64a60c-42d3-438d-91d6-0b917eea2da2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316657512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multip
le_keys.316657512
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.1098184986
Short name T693
Test name
Test status
Simulation time 8089230409 ps
CPU time 55.16 seconds
Started Feb 07 02:01:22 PM PST 24
Finished Feb 07 02:02:18 PM PST 24
Peak memory 287204 kb
Host smart-61848080-1e07-4224-9b64-0628f4a79a2a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098184986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.1098184986
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3902777583
Short name T912
Test name
Test status
Simulation time 12632760013 ps
CPU time 378.94 seconds
Started Feb 07 02:01:22 PM PST 24
Finished Feb 07 02:07:42 PM PST 24
Peak memory 202224 kb
Host smart-2c9de137-23e3-4352-8ae1-72d2a1256fdb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902777583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.3902777583
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3522647697
Short name T782
Test name
Test status
Simulation time 359740104 ps
CPU time 6.32 seconds
Started Feb 07 02:01:25 PM PST 24
Finished Feb 07 02:01:32 PM PST 24
Peak memory 202312 kb
Host smart-498e6f0a-41cf-4427-851d-aefd1ac7dc96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522647697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3522647697
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.513002377
Short name T367
Test name
Test status
Simulation time 9659577200 ps
CPU time 874.95 seconds
Started Feb 07 02:01:23 PM PST 24
Finished Feb 07 02:15:59 PM PST 24
Peak memory 364780 kb
Host smart-2434d20b-3297-4eab-884e-cbd58f80475f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513002377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.513002377
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.2085050342
Short name T453
Test name
Test status
Simulation time 7131190163 ps
CPU time 49.26 seconds
Started Feb 07 02:01:18 PM PST 24
Finished Feb 07 02:02:08 PM PST 24
Peak memory 302296 kb
Host smart-7becf98c-99a4-4f1f-b655-68aecfeff3f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085050342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2085050342
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.2456011580
Short name T927
Test name
Test status
Simulation time 105430234757 ps
CPU time 2641.98 seconds
Started Feb 07 02:01:25 PM PST 24
Finished Feb 07 02:45:28 PM PST 24
Peak memory 372656 kb
Host smart-81b5ea3c-750e-4989-b63c-1e25b85e852c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456011580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.2456011580
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2580245403
Short name T421
Test name
Test status
Simulation time 7154807292 ps
CPU time 3195.69 seconds
Started Feb 07 02:01:20 PM PST 24
Finished Feb 07 02:54:37 PM PST 24
Peak memory 490020 kb
Host smart-0fa3e077-62dc-436c-b695-6e4685d8c820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2580245403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2580245403
Directory /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3836305445
Short name T705
Test name
Test status
Simulation time 16212840023 ps
CPU time 424.65 seconds
Started Feb 07 02:01:15 PM PST 24
Finished Feb 07 02:08:20 PM PST 24
Peak memory 202180 kb
Host smart-3251dfec-40cc-4acd-b161-171a7af09e62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836305445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.3836305445
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.648710
Short name T910
Test name
Test status
Simulation time 7223094367 ps
CPU time 53.44 seconds
Started Feb 07 02:01:20 PM PST 24
Finished Feb 07 02:02:14 PM PST 24
Peak memory 283976 kb
Host smart-81704315-9d89-4776-8248-35f3eb06f550
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base
_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.sram_ctrl_throughput_w_partial_write.648710
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.993946078
Short name T418
Test name
Test status
Simulation time 13277443406 ps
CPU time 1559.12 seconds
Started Feb 07 02:01:34 PM PST 24
Finished Feb 07 02:27:34 PM PST 24
Peak memory 377104 kb
Host smart-73e7cd65-cc73-43f6-847f-e23232d3c3d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993946078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_access_during_key_req.993946078
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.1713109042
Short name T668
Test name
Test status
Simulation time 158050846953 ps
CPU time 2395.88 seconds
Started Feb 07 02:01:35 PM PST 24
Finished Feb 07 02:41:32 PM PST 24
Peak memory 202120 kb
Host smart-ef0eef1c-4f86-44da-ac45-389d8e038e04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713109042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection
.1713109042
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.3844332471
Short name T379
Test name
Test status
Simulation time 13287869237 ps
CPU time 365.09 seconds
Started Feb 07 02:01:36 PM PST 24
Finished Feb 07 02:07:42 PM PST 24
Peak memory 210484 kb
Host smart-68ba7aea-bd61-432b-a007-9c94ccd67321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844332471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.3844332471
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.2230467764
Short name T571
Test name
Test status
Simulation time 718444858 ps
CPU time 30.13 seconds
Started Feb 07 02:01:38 PM PST 24
Finished Feb 07 02:02:09 PM PST 24
Peak memory 226284 kb
Host smart-59177c53-1160-4f51-a349-cc7c018d13d8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230467764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.2230467764
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1265197573
Short name T897
Test name
Test status
Simulation time 3188969145 ps
CPU time 136.4 seconds
Started Feb 07 02:01:31 PM PST 24
Finished Feb 07 02:03:48 PM PST 24
Peak memory 211696 kb
Host smart-d221c309-ee55-44aa-bcae-630ff30c7493
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265197573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.1265197573
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1510395335
Short name T275
Test name
Test status
Simulation time 2070387306 ps
CPU time 124.54 seconds
Started Feb 07 02:01:29 PM PST 24
Finished Feb 07 02:03:34 PM PST 24
Peak memory 202152 kb
Host smart-cffebce5-f3c3-44ea-ac25-722afe6ec487
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510395335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1510395335
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.3960348505
Short name T891
Test name
Test status
Simulation time 38420653190 ps
CPU time 1334.56 seconds
Started Feb 07 02:01:32 PM PST 24
Finished Feb 07 02:23:47 PM PST 24
Peak memory 375972 kb
Host smart-eee26de5-4101-4d9f-bcd1-889aaae6506b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960348505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.3960348505
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.2611602977
Short name T821
Test name
Test status
Simulation time 3073303438 ps
CPU time 77.5 seconds
Started Feb 07 02:01:34 PM PST 24
Finished Feb 07 02:02:53 PM PST 24
Peak memory 327712 kb
Host smart-7e8e29b5-b2dd-4917-9801-39920eb7f15f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611602977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.2611602977
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3041734599
Short name T814
Test name
Test status
Simulation time 57763466659 ps
CPU time 267.19 seconds
Started Feb 07 02:01:33 PM PST 24
Finished Feb 07 02:06:01 PM PST 24
Peak memory 202228 kb
Host smart-374dc2d7-4fce-4c1d-8fa8-6c2aacf1be79
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041734599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.3041734599
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.1601420968
Short name T792
Test name
Test status
Simulation time 348733730 ps
CPU time 5.17 seconds
Started Feb 07 02:01:32 PM PST 24
Finished Feb 07 02:01:38 PM PST 24
Peak memory 202344 kb
Host smart-7773d35b-d263-4e3a-81c3-34a0b35808d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601420968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1601420968
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.1870842658
Short name T436
Test name
Test status
Simulation time 260989355700 ps
CPU time 1351.18 seconds
Started Feb 07 02:01:36 PM PST 24
Finished Feb 07 02:24:08 PM PST 24
Peak memory 369688 kb
Host smart-ac317ce2-3757-42f5-bed9-9356ad9700b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870842658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1870842658
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.3312355091
Short name T741
Test name
Test status
Simulation time 3293691120 ps
CPU time 16.43 seconds
Started Feb 07 02:01:38 PM PST 24
Finished Feb 07 02:01:55 PM PST 24
Peak memory 202052 kb
Host smart-40ce5afc-2982-45fe-a89e-1f68d0d65b9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312355091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3312355091
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.2500777161
Short name T809
Test name
Test status
Simulation time 146033125937 ps
CPU time 4268.95 seconds
Started Feb 07 02:01:38 PM PST 24
Finished Feb 07 03:12:48 PM PST 24
Peak memory 385192 kb
Host smart-6e202243-84a8-4d5e-80bc-63e468413c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500777161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.sram_ctrl_stress_all.2500777161
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2218539076
Short name T369
Test name
Test status
Simulation time 1511426734 ps
CPU time 4849.63 seconds
Started Feb 07 02:01:31 PM PST 24
Finished Feb 07 03:22:22 PM PST 24
Peak memory 421296 kb
Host smart-245628b8-a6ae-483b-b289-fdd8403394a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2218539076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2218539076
Directory /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2662681397
Short name T877
Test name
Test status
Simulation time 39388269139 ps
CPU time 227.97 seconds
Started Feb 07 02:01:30 PM PST 24
Finished Feb 07 02:05:19 PM PST 24
Peak memory 202208 kb
Host smart-a58d056f-4deb-46af-9692-eadd332f1763
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662681397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.2662681397
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3254584717
Short name T655
Test name
Test status
Simulation time 689449920 ps
CPU time 28.85 seconds
Started Feb 07 02:01:30 PM PST 24
Finished Feb 07 02:02:00 PM PST 24
Peak memory 214872 kb
Host smart-f16e53a2-aa23-45f6-b0a1-c32459706339
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254584717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3254584717
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3439823033
Short name T738
Test name
Test status
Simulation time 36995978705 ps
CPU time 1958.07 seconds
Started Feb 07 02:01:35 PM PST 24
Finished Feb 07 02:34:14 PM PST 24
Peak memory 377868 kb
Host smart-4c4a2a3e-1ad9-4a9d-9a47-9abbcbb01930
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439823033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.3439823033
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.581154999
Short name T400
Test name
Test status
Simulation time 54437763 ps
CPU time 0.67 seconds
Started Feb 07 02:01:32 PM PST 24
Finished Feb 07 02:01:34 PM PST 24
Peak memory 201460 kb
Host smart-c3e56f13-e09a-48ec-8fe8-e04992c46a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581154999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.581154999
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.2338716413
Short name T288
Test name
Test status
Simulation time 164293120333 ps
CPU time 732.99 seconds
Started Feb 07 02:01:39 PM PST 24
Finished Feb 07 02:13:52 PM PST 24
Peak memory 202188 kb
Host smart-223f6df1-30f8-45be-a264-c62647ed712d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338716413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.2338716413
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.1717055511
Short name T23
Test name
Test status
Simulation time 8113903674 ps
CPU time 167.73 seconds
Started Feb 07 02:01:34 PM PST 24
Finished Feb 07 02:04:23 PM PST 24
Peak memory 362424 kb
Host smart-7f724c09-72fa-42fe-aa9a-ebbd956c55a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717055511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.1717055511
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.702866135
Short name T601
Test name
Test status
Simulation time 14990131352 ps
CPU time 130.62 seconds
Started Feb 07 02:01:31 PM PST 24
Finished Feb 07 02:03:43 PM PST 24
Peak memory 346264 kb
Host smart-a728affb-7618-4b90-ad72-1677d347dd62
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702866135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.sram_ctrl_max_throughput.702866135
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2141647843
Short name T407
Test name
Test status
Simulation time 15338623822 ps
CPU time 83.02 seconds
Started Feb 07 02:01:35 PM PST 24
Finished Feb 07 02:02:59 PM PST 24
Peak memory 210668 kb
Host smart-aeb92663-5335-4ffe-b058-71ed897fae1e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141647843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.2141647843
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.2996093919
Short name T515
Test name
Test status
Simulation time 7889228161 ps
CPU time 121.71 seconds
Started Feb 07 02:01:35 PM PST 24
Finished Feb 07 02:03:38 PM PST 24
Peak memory 202188 kb
Host smart-d54e05e2-5b69-44b4-9167-a5334c8f33a3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996093919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.2996093919
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.2662420210
Short name T660
Test name
Test status
Simulation time 4269166471 ps
CPU time 220.97 seconds
Started Feb 07 02:01:30 PM PST 24
Finished Feb 07 02:05:12 PM PST 24
Peak memory 374048 kb
Host smart-9b728869-c782-4907-a374-4d7e59995a8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662420210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.2662420210
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.3745978353
Short name T257
Test name
Test status
Simulation time 1405345362 ps
CPU time 28.48 seconds
Started Feb 07 02:01:32 PM PST 24
Finished Feb 07 02:02:02 PM PST 24
Peak memory 202124 kb
Host smart-68cb4048-7452-4c51-a8c2-c36c13907813
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745978353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
sram_ctrl_partial_access.3745978353
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.4033452160
Short name T376
Test name
Test status
Simulation time 6227315177 ps
CPU time 387.71 seconds
Started Feb 07 02:01:35 PM PST 24
Finished Feb 07 02:08:03 PM PST 24
Peak memory 202120 kb
Host smart-bdb5af91-e995-47fc-8773-23f7471806a0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033452160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.4033452160
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.40347114
Short name T729
Test name
Test status
Simulation time 365201099 ps
CPU time 5.58 seconds
Started Feb 07 02:01:31 PM PST 24
Finished Feb 07 02:01:37 PM PST 24
Peak memory 202320 kb
Host smart-b654a097-6123-40b5-aedc-b8c506a6fc13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40347114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.40347114
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.26321946
Short name T477
Test name
Test status
Simulation time 2814658996 ps
CPU time 470.3 seconds
Started Feb 07 02:01:29 PM PST 24
Finished Feb 07 02:09:19 PM PST 24
Peak memory 379080 kb
Host smart-f5faf59e-bc91-4522-954d-676c8b11f6f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26321946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.26321946
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.1020367260
Short name T313
Test name
Test status
Simulation time 1692361622 ps
CPU time 29.19 seconds
Started Feb 07 02:01:28 PM PST 24
Finished Feb 07 02:01:58 PM PST 24
Peak memory 202088 kb
Host smart-4682de06-5793-45f9-8535-ebdd89ffbf89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020367260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1020367260
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1898260778
Short name T500
Test name
Test status
Simulation time 765444972 ps
CPU time 1854.75 seconds
Started Feb 07 02:01:36 PM PST 24
Finished Feb 07 02:32:31 PM PST 24
Peak memory 521480 kb
Host smart-7f7db0bf-9bc0-4c71-9a93-06bf458dac15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1898260778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1898260778
Directory /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2116577323
Short name T458
Test name
Test status
Simulation time 16189276433 ps
CPU time 321.99 seconds
Started Feb 07 02:01:38 PM PST 24
Finished Feb 07 02:07:01 PM PST 24
Peak memory 202260 kb
Host smart-1d019ea3-4dec-4a2f-963a-bee21f9c8f1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116577323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2116577323
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1773490770
Short name T556
Test name
Test status
Simulation time 824880236 ps
CPU time 117.9 seconds
Started Feb 07 02:01:30 PM PST 24
Finished Feb 07 02:03:29 PM PST 24
Peak memory 358888 kb
Host smart-03414626-9895-4814-8065-09ca95c5299b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773490770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.1773490770
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2964727144
Short name T337
Test name
Test status
Simulation time 4983762587 ps
CPU time 594.18 seconds
Started Feb 07 02:01:30 PM PST 24
Finished Feb 07 02:11:25 PM PST 24
Peak memory 359016 kb
Host smart-44b0fa30-e204-4873-b8db-d972cfb4ca8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964727144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.2964727144
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.3219345108
Short name T28
Test name
Test status
Simulation time 15368279 ps
CPU time 0.63 seconds
Started Feb 07 02:01:36 PM PST 24
Finished Feb 07 02:01:38 PM PST 24
Peak memory 201920 kb
Host smart-ec413184-6bf7-42b1-bb4e-5a84a3d5d28b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219345108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.3219345108
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.4267475866
Short name T750
Test name
Test status
Simulation time 14032680524 ps
CPU time 954.17 seconds
Started Feb 07 02:01:30 PM PST 24
Finished Feb 07 02:17:25 PM PST 24
Peak memory 202276 kb
Host smart-9818095f-4a61-4c95-9611-66a7f0d52b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267475866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.4267475866
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.2310222773
Short name T673
Test name
Test status
Simulation time 18919766758 ps
CPU time 106.26 seconds
Started Feb 07 02:01:31 PM PST 24
Finished Feb 07 02:03:18 PM PST 24
Peak memory 210864 kb
Host smart-96155808-30b9-48bd-bc67-3e2d71b91e71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310222773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.2310222773
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.2328932174
Short name T446
Test name
Test status
Simulation time 705853357 ps
CPU time 43.86 seconds
Started Feb 07 02:01:29 PM PST 24
Finished Feb 07 02:02:14 PM PST 24
Peak memory 267588 kb
Host smart-40751181-0952-4acc-bfa2-4d0bb79f90e0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328932174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.sram_ctrl_max_throughput.2328932174
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2248500249
Short name T424
Test name
Test status
Simulation time 982865357 ps
CPU time 76.44 seconds
Started Feb 07 02:01:37 PM PST 24
Finished Feb 07 02:02:54 PM PST 24
Peak memory 211364 kb
Host smart-3a076d0c-aadc-4230-8a8c-378ab35b98f1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248500249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.2248500249
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.394359357
Short name T935
Test name
Test status
Simulation time 79483241698 ps
CPU time 154.29 seconds
Started Feb 07 02:01:34 PM PST 24
Finished Feb 07 02:04:09 PM PST 24
Peak memory 202564 kb
Host smart-5c53b2a9-c280-4694-83b1-aea0721d7f1f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394359357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_mem_walk.394359357
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.2454654612
Short name T651
Test name
Test status
Simulation time 10463754379 ps
CPU time 768.74 seconds
Started Feb 07 02:01:38 PM PST 24
Finished Feb 07 02:14:27 PM PST 24
Peak memory 373104 kb
Host smart-d21f5662-240e-4fb6-b377-7a4f38967b41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454654612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.2454654612
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.1857600230
Short name T656
Test name
Test status
Simulation time 2004774181 ps
CPU time 13.95 seconds
Started Feb 07 02:01:39 PM PST 24
Finished Feb 07 02:01:53 PM PST 24
Peak memory 232852 kb
Host smart-7b2d399e-0b3d-4ff2-8452-891898e1b1c9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857600230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.1857600230
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.809100085
Short name T351
Test name
Test status
Simulation time 85789278563 ps
CPU time 431.24 seconds
Started Feb 07 02:01:29 PM PST 24
Finished Feb 07 02:08:41 PM PST 24
Peak memory 202176 kb
Host smart-895a6159-63be-4c24-82f6-468ff323eb05
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809100085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.sram_ctrl_partial_access_b2b.809100085
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.3760416681
Short name T906
Test name
Test status
Simulation time 742818774 ps
CPU time 6.31 seconds
Started Feb 07 02:01:35 PM PST 24
Finished Feb 07 02:01:42 PM PST 24
Peak memory 202340 kb
Host smart-608dd846-bb3d-4407-ade6-5bd3178f6ba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760416681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.3760416681
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.3826316753
Short name T212
Test name
Test status
Simulation time 669032695 ps
CPU time 42.34 seconds
Started Feb 07 02:01:33 PM PST 24
Finished Feb 07 02:02:17 PM PST 24
Peak memory 282952 kb
Host smart-5c0b7769-0dae-4704-960a-7c91abefec4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826316753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3826316753
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3354119266
Short name T882
Test name
Test status
Simulation time 1355770577 ps
CPU time 2818.06 seconds
Started Feb 07 02:01:32 PM PST 24
Finished Feb 07 02:48:31 PM PST 24
Peak memory 611992 kb
Host smart-7b6401c2-7494-45fd-b644-256efc70b1dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3354119266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3354119266
Directory /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.411764679
Short name T539
Test name
Test status
Simulation time 15456957542 ps
CPU time 270.03 seconds
Started Feb 07 02:01:32 PM PST 24
Finished Feb 07 02:06:03 PM PST 24
Peak memory 210408 kb
Host smart-48c9eb5c-6f63-4a10-96e9-486b1dde8ed6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411764679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_stress_pipeline.411764679
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4066587784
Short name T349
Test name
Test status
Simulation time 1597844760 ps
CPU time 182.16 seconds
Started Feb 07 02:01:31 PM PST 24
Finished Feb 07 02:04:34 PM PST 24
Peak memory 365684 kb
Host smart-4127a969-6c23-4165-87cc-82d9e240edcc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066587784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.4066587784
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1360882352
Short name T879
Test name
Test status
Simulation time 29646435393 ps
CPU time 1255.32 seconds
Started Feb 07 02:01:38 PM PST 24
Finished Feb 07 02:22:34 PM PST 24
Peak memory 376064 kb
Host smart-92a020aa-6488-422d-ac07-30d4ca1dd04f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360882352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.1360882352
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.3208981633
Short name T527
Test name
Test status
Simulation time 98638419 ps
CPU time 0.6 seconds
Started Feb 07 02:01:43 PM PST 24
Finished Feb 07 02:01:44 PM PST 24
Peak memory 201824 kb
Host smart-bcf24a48-7ba8-4185-b499-92dacc2c2a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208981633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.3208981633
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1729791184
Short name T211
Test name
Test status
Simulation time 86425441671 ps
CPU time 1829.05 seconds
Started Feb 07 02:01:33 PM PST 24
Finished Feb 07 02:32:03 PM PST 24
Peak memory 202188 kb
Host smart-6ba890dc-6d41-4d55-b2e5-ab87b293cfd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729791184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1729791184
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.1950040513
Short name T698
Test name
Test status
Simulation time 3069988551 ps
CPU time 65.02 seconds
Started Feb 07 02:01:40 PM PST 24
Finished Feb 07 02:02:46 PM PST 24
Peak memory 202168 kb
Host smart-9d369230-993b-4b33-bc51-5bd0149eba3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950040513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.1950040513
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.2245844050
Short name T608
Test name
Test status
Simulation time 20003386391 ps
CPU time 111.12 seconds
Started Feb 07 02:01:36 PM PST 24
Finished Feb 07 02:03:28 PM PST 24
Peak memory 213944 kb
Host smart-e9d7ef18-ca9e-4374-9210-44cface59085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245844050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.2245844050
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1574510796
Short name T292
Test name
Test status
Simulation time 794714347 ps
CPU time 56 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:02:42 PM PST 24
Peak memory 294000 kb
Host smart-1f8c5922-6fcb-48e0-894d-d5d43921a516
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574510796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1574510796
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1140986247
Short name T753
Test name
Test status
Simulation time 8898154737 ps
CPU time 150.27 seconds
Started Feb 07 02:01:47 PM PST 24
Finished Feb 07 02:04:18 PM PST 24
Peak memory 218516 kb
Host smart-d753bfa3-676b-49d8-8738-98d0cbccd52f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140986247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.1140986247
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.2547430842
Short name T599
Test name
Test status
Simulation time 49233936657 ps
CPU time 293.92 seconds
Started Feb 07 02:01:43 PM PST 24
Finished Feb 07 02:06:38 PM PST 24
Peak memory 202184 kb
Host smart-59153919-efda-4878-95c6-1f3537b6899c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547430842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.2547430842
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.3363309151
Short name T825
Test name
Test status
Simulation time 31467429270 ps
CPU time 575.59 seconds
Started Feb 07 02:01:33 PM PST 24
Finished Feb 07 02:11:10 PM PST 24
Peak memory 376008 kb
Host smart-13d95318-2d05-4a72-a163-77149b44f743
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363309151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.3363309151
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.3932607074
Short name T594
Test name
Test status
Simulation time 3328282950 ps
CPU time 150.93 seconds
Started Feb 07 02:01:37 PM PST 24
Finished Feb 07 02:04:09 PM PST 24
Peak memory 350436 kb
Host smart-cc736226-d0fa-4530-99fe-26e19896079f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932607074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.3932607074
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2508104480
Short name T475
Test name
Test status
Simulation time 13756698520 ps
CPU time 307.15 seconds
Started Feb 07 02:01:34 PM PST 24
Finished Feb 07 02:06:42 PM PST 24
Peak memory 202084 kb
Host smart-5711520b-2ca4-466b-95a6-2ab32e61d57d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508104480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.2508104480
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.3542443816
Short name T827
Test name
Test status
Simulation time 1413978022 ps
CPU time 6.54 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:01:52 PM PST 24
Peak memory 202328 kb
Host smart-68d117f2-3ea3-4aed-afee-54c4dc963d52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542443816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3542443816
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.3243129450
Short name T620
Test name
Test status
Simulation time 26074495174 ps
CPU time 790.74 seconds
Started Feb 07 02:01:40 PM PST 24
Finished Feb 07 02:14:51 PM PST 24
Peak memory 377048 kb
Host smart-3ed5e678-d55f-40aa-920d-37a079846f1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243129450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3243129450
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.2073666513
Short name T411
Test name
Test status
Simulation time 3894732114 ps
CPU time 35.07 seconds
Started Feb 07 02:01:34 PM PST 24
Finished Feb 07 02:02:10 PM PST 24
Peak memory 271216 kb
Host smart-e26c7979-1ea1-4413-af19-8ee47f55a9d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073666513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2073666513
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.4174148937
Short name T462
Test name
Test status
Simulation time 196919209382 ps
CPU time 3050.67 seconds
Started Feb 07 02:01:46 PM PST 24
Finished Feb 07 02:52:38 PM PST 24
Peak memory 373940 kb
Host smart-d9ec167a-fa87-4349-b490-4bcb703c3a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174148937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.4174148937
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2244120902
Short name T516
Test name
Test status
Simulation time 474329822 ps
CPU time 2758.67 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:47:45 PM PST 24
Peak memory 431128 kb
Host smart-bc24e3f5-c527-4a14-8614-5870078cfd8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2244120902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2244120902
Directory /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1825574219
Short name T709
Test name
Test status
Simulation time 8941249231 ps
CPU time 285.41 seconds
Started Feb 07 02:01:41 PM PST 24
Finished Feb 07 02:06:27 PM PST 24
Peak memory 202188 kb
Host smart-fc7dbbdb-007a-41a0-814b-20235d5138bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825574219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.1825574219
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.671366043
Short name T264
Test name
Test status
Simulation time 2959834825 ps
CPU time 78.25 seconds
Started Feb 07 02:01:46 PM PST 24
Finished Feb 07 02:03:05 PM PST 24
Peak memory 309160 kb
Host smart-507e3cd9-455a-4498-abbe-19eb803056ef
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671366043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.671366043
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1408958796
Short name T432
Test name
Test status
Simulation time 2485351508 ps
CPU time 192.79 seconds
Started Feb 07 02:01:40 PM PST 24
Finished Feb 07 02:04:53 PM PST 24
Peak memory 326716 kb
Host smart-295a09f8-1b2d-4b9e-8e2b-7ec4496676da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408958796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.1408958796
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.810163208
Short name T456
Test name
Test status
Simulation time 26053033 ps
CPU time 0.65 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:01:46 PM PST 24
Peak memory 201480 kb
Host smart-169b1203-25aa-4209-9ff7-3cfc6fd092c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810163208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.810163208
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.2572208634
Short name T507
Test name
Test status
Simulation time 77905328226 ps
CPU time 1681.05 seconds
Started Feb 07 02:01:37 PM PST 24
Finished Feb 07 02:29:39 PM PST 24
Peak memory 202176 kb
Host smart-834c7a9b-6eb9-41ee-9e00-2c7340684214
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572208634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.2572208634
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.3075047984
Short name T46
Test name
Test status
Simulation time 55285030891 ps
CPU time 141.29 seconds
Started Feb 07 02:01:41 PM PST 24
Finished Feb 07 02:04:03 PM PST 24
Peak memory 210332 kb
Host smart-09582de8-5ed1-4968-8aab-df51cd5f4f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075047984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.3075047984
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.82158172
Short name T294
Test name
Test status
Simulation time 1518277945 ps
CPU time 151.21 seconds
Started Feb 07 02:01:37 PM PST 24
Finished Feb 07 02:04:09 PM PST 24
Peak memory 354632 kb
Host smart-e2707e56-044a-4e25-bc34-7788d71675da
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82158172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_max_throughput.82158172
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.938363905
Short name T321
Test name
Test status
Simulation time 4553723746 ps
CPU time 149.15 seconds
Started Feb 07 02:01:37 PM PST 24
Finished Feb 07 02:04:07 PM PST 24
Peak memory 214828 kb
Host smart-23814bf7-27eb-4959-bb0e-1822ab3f72b9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938363905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.sram_ctrl_mem_partial_access.938363905
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.3231428222
Short name T323
Test name
Test status
Simulation time 13930367808 ps
CPU time 276.94 seconds
Started Feb 07 02:01:41 PM PST 24
Finished Feb 07 02:06:18 PM PST 24
Peak memory 202156 kb
Host smart-2251a919-585f-45a8-9617-058e1a34aa9e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231428222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.3231428222
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.4035155525
Short name T875
Test name
Test status
Simulation time 36827427619 ps
CPU time 765.9 seconds
Started Feb 07 02:01:37 PM PST 24
Finished Feb 07 02:14:24 PM PST 24
Peak memory 374928 kb
Host smart-95503202-90c2-4e93-87e5-4218ecf5beab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035155525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.4035155525
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.1602522523
Short name T305
Test name
Test status
Simulation time 813086974 ps
CPU time 13.94 seconds
Started Feb 07 02:01:44 PM PST 24
Finished Feb 07 02:01:59 PM PST 24
Peak memory 202164 kb
Host smart-9df49d9b-e788-4247-9e47-04587d4d1a5b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602522523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.1602522523
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2131544702
Short name T819
Test name
Test status
Simulation time 61088633656 ps
CPU time 331.41 seconds
Started Feb 07 02:01:41 PM PST 24
Finished Feb 07 02:07:13 PM PST 24
Peak memory 202152 kb
Host smart-d29261c2-7090-4ac9-8db9-150b393b29b4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131544702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2131544702
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.4094654094
Short name T708
Test name
Test status
Simulation time 349072922 ps
CPU time 12.84 seconds
Started Feb 07 02:01:46 PM PST 24
Finished Feb 07 02:01:59 PM PST 24
Peak memory 202332 kb
Host smart-1ba8955f-6267-4d59-99ef-c5f3885b0a42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094654094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.4094654094
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.2735862167
Short name T811
Test name
Test status
Simulation time 106993034040 ps
CPU time 865.08 seconds
Started Feb 07 02:01:44 PM PST 24
Finished Feb 07 02:16:10 PM PST 24
Peak memory 373908 kb
Host smart-847c4911-886d-496b-a0de-aa139c3f0e15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735862167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2735862167
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.1261279414
Short name T74
Test name
Test status
Simulation time 1721822053 ps
CPU time 29.19 seconds
Started Feb 07 02:01:46 PM PST 24
Finished Feb 07 02:02:16 PM PST 24
Peak memory 202012 kb
Host smart-8c7bb70c-f890-4ad2-99b8-203e4f59b126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261279414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1261279414
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4008514566
Short name T244
Test name
Test status
Simulation time 1981999709 ps
CPU time 9941.85 seconds
Started Feb 07 02:01:38 PM PST 24
Finished Feb 07 04:47:21 PM PST 24
Peak memory 736564 kb
Host smart-1e1307c0-18fb-4019-abda-752b4de674fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4008514566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.4008514566
Directory /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2529742244
Short name T380
Test name
Test status
Simulation time 9635961246 ps
CPU time 342.22 seconds
Started Feb 07 02:01:40 PM PST 24
Finished Feb 07 02:07:23 PM PST 24
Peak memory 202256 kb
Host smart-205f5bed-405b-4ee1-b7e2-770e5bfa7bc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529742244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.2529742244
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1290735348
Short name T10
Test name
Test status
Simulation time 1566066494 ps
CPU time 109.5 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:03:36 PM PST 24
Peak memory 348388 kb
Host smart-d28ebfff-3e27-49dc-a553-5f6a5e905191
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290735348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1290735348
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.1768731477
Short name T272
Test name
Test status
Simulation time 2491606494 ps
CPU time 326.69 seconds
Started Feb 07 02:01:50 PM PST 24
Finished Feb 07 02:07:17 PM PST 24
Peak memory 353512 kb
Host smart-b28a40bd-99fe-44bd-9cb1-a94a811edad8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768731477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.1768731477
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.3356372562
Short name T603
Test name
Test status
Simulation time 57127346 ps
CPU time 0.68 seconds
Started Feb 07 02:01:50 PM PST 24
Finished Feb 07 02:01:51 PM PST 24
Peak memory 201856 kb
Host smart-5c37d539-2e10-46b2-b898-e87c5850f7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356372562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.3356372562
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.4122337861
Short name T390
Test name
Test status
Simulation time 231857654606 ps
CPU time 570.87 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:11:16 PM PST 24
Peak memory 202244 kb
Host smart-8cdd9e69-6f77-46d1-8b10-b3120aab4259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122337861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.4122337861
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.398212692
Short name T329
Test name
Test status
Simulation time 15600246276 ps
CPU time 921.59 seconds
Started Feb 07 02:01:44 PM PST 24
Finished Feb 07 02:17:07 PM PST 24
Peak memory 377040 kb
Host smart-89b4b25e-c54c-4818-9253-6d2e0607aa3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398212692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executabl
e.398212692
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.2751630949
Short name T640
Test name
Test status
Simulation time 5590620325 ps
CPU time 86.89 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:03:13 PM PST 24
Peak memory 210380 kb
Host smart-d56c550a-1232-45dd-938e-82bfc6f5ce82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751630949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.2751630949
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.3875014151
Short name T208
Test name
Test status
Simulation time 2724069086 ps
CPU time 32.57 seconds
Started Feb 07 02:01:46 PM PST 24
Finished Feb 07 02:02:19 PM PST 24
Peak memory 230808 kb
Host smart-810dd0b1-38c4-4a77-b8ad-9555e73dab61
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875014151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.3875014151
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1991100244
Short name T442
Test name
Test status
Simulation time 2366195614 ps
CPU time 77.18 seconds
Started Feb 07 02:01:55 PM PST 24
Finished Feb 07 02:03:12 PM PST 24
Peak memory 218512 kb
Host smart-d0cb1c6d-bf33-45c6-91e8-dea82897fd36
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991100244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.1991100244
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.3847215579
Short name T937
Test name
Test status
Simulation time 114574276515 ps
CPU time 335.35 seconds
Started Feb 07 02:01:48 PM PST 24
Finished Feb 07 02:07:24 PM PST 24
Peak memory 202560 kb
Host smart-0efda6c9-26bf-4d1a-a590-40ae5042fc26
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847215579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.3847215579
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.2658013356
Short name T924
Test name
Test status
Simulation time 18426537130 ps
CPU time 1352.04 seconds
Started Feb 07 02:01:46 PM PST 24
Finished Feb 07 02:24:19 PM PST 24
Peak memory 376996 kb
Host smart-d257c215-56d4-45de-a544-771b8cc457f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658013356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.2658013356
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2969526293
Short name T16
Test name
Test status
Simulation time 499536663 ps
CPU time 58.39 seconds
Started Feb 07 02:01:47 PM PST 24
Finished Feb 07 02:02:46 PM PST 24
Peak memory 309312 kb
Host smart-080c7862-4179-409c-808f-f83a514c07f3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969526293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2969526293
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.622007710
Short name T854
Test name
Test status
Simulation time 6635458470 ps
CPU time 363.92 seconds
Started Feb 07 02:01:45 PM PST 24
Finished Feb 07 02:07:50 PM PST 24
Peak memory 202232 kb
Host smart-cbabd2ff-4974-4611-98c9-ab15f75a859f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622007710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.sram_ctrl_partial_access_b2b.622007710
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.4249309638
Short name T486
Test name
Test status
Simulation time 2811003991 ps
CPU time 6.09 seconds
Started Feb 07 02:01:55 PM PST 24
Finished Feb 07 02:02:02 PM PST 24
Peak memory 202464 kb
Host smart-ec3ff2d8-6bc0-496b-ab2a-6ed9bfa50d59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249309638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4249309638
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.1655450676
Short name T552
Test name
Test status
Simulation time 17296974459 ps
CPU time 957.12 seconds
Started Feb 07 02:01:56 PM PST 24
Finished Feb 07 02:17:53 PM PST 24
Peak memory 378004 kb
Host smart-a3ee25c0-c646-4657-8f27-dcee54733814
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655450676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1655450676
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.663313659
Short name T541
Test name
Test status
Simulation time 1513258014 ps
CPU time 36.01 seconds
Started Feb 07 02:01:43 PM PST 24
Finished Feb 07 02:02:20 PM PST 24
Peak memory 281872 kb
Host smart-12e60307-7d95-4880-8581-e8f5174f271f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663313659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.663313659
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.469177901
Short name T623
Test name
Test status
Simulation time 7724677510 ps
CPU time 450.89 seconds
Started Feb 07 02:01:48 PM PST 24
Finished Feb 07 02:09:20 PM PST 24
Peak memory 202200 kb
Host smart-81bc492f-c441-4886-b92f-a17f791901fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469177901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.sram_ctrl_stress_pipeline.469177901
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2069315127
Short name T220
Test name
Test status
Simulation time 2945185668 ps
CPU time 38.88 seconds
Started Feb 07 02:01:44 PM PST 24
Finished Feb 07 02:02:23 PM PST 24
Peak memory 256492 kb
Host smart-74484d79-9d78-4830-b66d-01e05fd4a0ba
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069315127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2069315127
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3435477443
Short name T885
Test name
Test status
Simulation time 11066030932 ps
CPU time 287.79 seconds
Started Feb 07 02:01:59 PM PST 24
Finished Feb 07 02:06:48 PM PST 24
Peak memory 375836 kb
Host smart-bc2a4d71-8814-4572-a830-dea133754dae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435477443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3435477443
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.3069853886
Short name T917
Test name
Test status
Simulation time 23392825 ps
CPU time 0.69 seconds
Started Feb 07 02:02:12 PM PST 24
Finished Feb 07 02:02:33 PM PST 24
Peak memory 201844 kb
Host smart-d58e0534-eef0-461b-a523-cc9b28e081f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069853886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.3069853886
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.3868301206
Short name T209
Test name
Test status
Simulation time 50067446414 ps
CPU time 888.7 seconds
Started Feb 07 02:01:49 PM PST 24
Finished Feb 07 02:16:39 PM PST 24
Peak memory 202252 kb
Host smart-cb7e580e-6ffa-42c2-907b-915bfff988a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868301206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.3868301206
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.3963863051
Short name T583
Test name
Test status
Simulation time 1423501335 ps
CPU time 52.51 seconds
Started Feb 07 02:01:56 PM PST 24
Finished Feb 07 02:02:50 PM PST 24
Peak memory 274632 kb
Host smart-818c5cb4-d3ef-4706-a8f1-2630c2d116b3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963863051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.3963863051
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.366793273
Short name T679
Test name
Test status
Simulation time 1889844124 ps
CPU time 71.02 seconds
Started Feb 07 02:01:56 PM PST 24
Finished Feb 07 02:03:08 PM PST 24
Peak memory 210752 kb
Host smart-f80aa3f1-b17c-4cd9-9a50-0a89b75405de
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366793273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_mem_partial_access.366793273
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.183106782
Short name T838
Test name
Test status
Simulation time 14177403365 ps
CPU time 283.25 seconds
Started Feb 07 02:01:56 PM PST 24
Finished Feb 07 02:06:40 PM PST 24
Peak memory 202264 kb
Host smart-e7d07d75-d212-4499-907c-861702e4ad29
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183106782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl
_mem_walk.183106782
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.3973977702
Short name T616
Test name
Test status
Simulation time 9965627767 ps
CPU time 1095.39 seconds
Started Feb 07 02:01:47 PM PST 24
Finished Feb 07 02:20:03 PM PST 24
Peak memory 377080 kb
Host smart-34973a65-f45e-4388-9408-8534070d7738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973977702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi
ple_keys.3973977702
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.413403380
Short name T248
Test name
Test status
Simulation time 6968149601 ps
CPU time 32.17 seconds
Started Feb 07 02:01:58 PM PST 24
Finished Feb 07 02:02:31 PM PST 24
Peak memory 202140 kb
Host smart-b8b5f08d-8b35-462a-90ea-bc32da3ef3d2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413403380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.s
ram_ctrl_partial_access.413403380
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1583075546
Short name T572
Test name
Test status
Simulation time 43809279854 ps
CPU time 512.26 seconds
Started Feb 07 02:01:55 PM PST 24
Finished Feb 07 02:10:28 PM PST 24
Peak memory 202144 kb
Host smart-5fecf747-c980-4c89-bff1-a9e4df69d1b0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583075546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1583075546
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.1682468749
Short name T752
Test name
Test status
Simulation time 1354382384 ps
CPU time 13.97 seconds
Started Feb 07 02:01:58 PM PST 24
Finished Feb 07 02:02:13 PM PST 24
Peak memory 202368 kb
Host smart-14b52e35-cc40-4b20-ae15-7f04f3637b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682468749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1682468749
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2509557298
Short name T280
Test name
Test status
Simulation time 23497789579 ps
CPU time 283.77 seconds
Started Feb 07 02:02:01 PM PST 24
Finished Feb 07 02:06:45 PM PST 24
Peak memory 373980 kb
Host smart-ee427a79-c43a-4de5-ae28-5686b46717c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509557298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2509557298
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.537191069
Short name T260
Test name
Test status
Simulation time 547169926 ps
CPU time 28.35 seconds
Started Feb 07 02:01:54 PM PST 24
Finished Feb 07 02:02:23 PM PST 24
Peak memory 202136 kb
Host smart-b227de15-ae55-40e0-a4d9-48330eb006e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537191069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.537191069
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3979943333
Short name T295
Test name
Test status
Simulation time 7967868063 ps
CPU time 7467.35 seconds
Started Feb 07 02:01:59 PM PST 24
Finished Feb 07 04:06:28 PM PST 24
Peak memory 449296 kb
Host smart-904bb076-ce82-4478-a9c0-332615ac19c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3979943333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3979943333
Directory /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1245876639
Short name T920
Test name
Test status
Simulation time 4848476849 ps
CPU time 338.55 seconds
Started Feb 07 02:01:51 PM PST 24
Finished Feb 07 02:07:30 PM PST 24
Peak memory 210400 kb
Host smart-4940e56c-e74f-4e2f-8aee-90102b34eb9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245876639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.1245876639
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.567976526
Short name T553
Test name
Test status
Simulation time 3736217449 ps
CPU time 27.77 seconds
Started Feb 07 02:01:56 PM PST 24
Finished Feb 07 02:02:24 PM PST 24
Peak memory 216720 kb
Host smart-72135212-0e62-4ce2-bb93-e17aefd70258
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567976526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_throughput_w_partial_write.567976526
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2321552766
Short name T428
Test name
Test status
Simulation time 6900299305 ps
CPU time 1010.58 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:17:32 PM PST 24
Peak memory 378920 kb
Host smart-4cb63529-b55f-4d42-b41c-b608de1f076d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321552766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.2321552766
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.423915752
Short name T748
Test name
Test status
Simulation time 18047998 ps
CPU time 0.71 seconds
Started Feb 07 02:00:44 PM PST 24
Finished Feb 07 02:00:47 PM PST 24
Peak memory 201440 kb
Host smart-31df525d-fa4a-4b14-8404-04245a367ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423915752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.423915752
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.2136782193
Short name T49
Test name
Test status
Simulation time 74579663002 ps
CPU time 1639.29 seconds
Started Feb 07 02:00:39 PM PST 24
Finished Feb 07 02:27:59 PM PST 24
Peak memory 202252 kb
Host smart-1cd270fd-ff99-44c5-8225-fbe93bfb6ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136782193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
2136782193
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.1008209479
Short name T837
Test name
Test status
Simulation time 6202196556 ps
CPU time 130.16 seconds
Started Feb 07 02:00:45 PM PST 24
Finished Feb 07 02:02:57 PM PST 24
Peak memory 202236 kb
Host smart-2dba1a0f-85ba-4391-a30f-e3212cda5224
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008209479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.1008209479
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.1352899418
Short name T818
Test name
Test status
Simulation time 2846478098 ps
CPU time 49.56 seconds
Started Feb 07 02:00:42 PM PST 24
Finished Feb 07 02:01:33 PM PST 24
Peak memory 275776 kb
Host smart-697942e1-f8f4-41a0-9f2d-c63564c8a0b2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352899418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.1352899418
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1247414094
Short name T472
Test name
Test status
Simulation time 4931058476 ps
CPU time 73.78 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:01:55 PM PST 24
Peak memory 211268 kb
Host smart-0f12318e-69e8-4b8b-8306-7df02f7a53b5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247414094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.1247414094
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.665804781
Short name T206
Test name
Test status
Simulation time 2409639013 ps
CPU time 122.39 seconds
Started Feb 07 02:00:44 PM PST 24
Finished Feb 07 02:02:49 PM PST 24
Peak memory 202188 kb
Host smart-1ec1db7f-da27-44ec-a901-22d65ee24328
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665804781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
mem_walk.665804781
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.1717955028
Short name T775
Test name
Test status
Simulation time 1326964975 ps
CPU time 27.35 seconds
Started Feb 07 02:00:42 PM PST 24
Finished Feb 07 02:01:11 PM PST 24
Peak memory 202096 kb
Host smart-d4b179a5-c661-4230-bd95-f1f6c83391bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717955028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.1717955028
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.4238314359
Short name T595
Test name
Test status
Simulation time 2154367650 ps
CPU time 20.88 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:01:01 PM PST 24
Peak memory 202148 kb
Host smart-4209b216-0ff9-4f9b-8192-fc234cad0334
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238314359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.4238314359
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.37698747
Short name T316
Test name
Test status
Simulation time 29035774251 ps
CPU time 181.96 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:03:55 PM PST 24
Peak memory 202116 kb
Host smart-74b3abfb-62ca-4108-ba95-458c3919971d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37698747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_partial_access_b2b.37698747
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.2488144606
Short name T848
Test name
Test status
Simulation time 1407026642 ps
CPU time 13.59 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:00:55 PM PST 24
Peak memory 202436 kb
Host smart-19d97ebc-8e86-40da-ae52-31168564a281
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488144606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2488144606
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.3230811353
Short name T495
Test name
Test status
Simulation time 191804290168 ps
CPU time 1622.22 seconds
Started Feb 07 02:00:43 PM PST 24
Finished Feb 07 02:27:48 PM PST 24
Peak memory 372756 kb
Host smart-e2610589-cda5-4e2d-9bb2-50f2a6f13817
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230811353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3230811353
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.1414155860
Short name T22
Test name
Test status
Simulation time 368102373 ps
CPU time 1.79 seconds
Started Feb 07 02:00:41 PM PST 24
Finished Feb 07 02:00:45 PM PST 24
Peak memory 223900 kb
Host smart-3cd7f10a-48c2-4ec8-89da-1528bb113c21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414155860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.1414155860
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.265688951
Short name T713
Test name
Test status
Simulation time 716900754 ps
CPU time 13.14 seconds
Started Feb 07 02:00:45 PM PST 24
Finished Feb 07 02:01:00 PM PST 24
Peak memory 202100 kb
Host smart-78e1d8be-fb94-4d26-9c01-068065844bf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265688951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.265688951
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.4243389453
Short name T483
Test name
Test status
Simulation time 768304045570 ps
CPU time 3391.92 seconds
Started Feb 07 02:00:40 PM PST 24
Finished Feb 07 02:57:13 PM PST 24
Peak memory 371896 kb
Host smart-284a284e-a77b-40ba-bdf5-650af8216dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243389453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.4243389453
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1522520714
Short name T283
Test name
Test status
Simulation time 1908381320 ps
CPU time 1842.63 seconds
Started Feb 07 02:00:39 PM PST 24
Finished Feb 07 02:31:23 PM PST 24
Peak memory 699036 kb
Host smart-06853438-fca4-402d-ae7a-6959a60cae23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1522520714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.1522520714
Directory /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.479800688
Short name T749
Test name
Test status
Simulation time 4465938725 ps
CPU time 161.62 seconds
Started Feb 07 02:00:50 PM PST 24
Finished Feb 07 02:03:34 PM PST 24
Peak memory 202208 kb
Host smart-e4a381bc-41a1-4cb5-ba09-cb8a9404b1ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479800688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_stress_pipeline.479800688
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.509337402
Short name T403
Test name
Test status
Simulation time 4601201824 ps
CPU time 130.87 seconds
Started Feb 07 02:00:45 PM PST 24
Finished Feb 07 02:02:58 PM PST 24
Peak memory 374748 kb
Host smart-f0ef4c95-76d4-4c80-9c7c-063b360d0def
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509337402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.509337402
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.2676957795
Short name T332
Test name
Test status
Simulation time 86963646036 ps
CPU time 1101.04 seconds
Started Feb 07 02:02:23 PM PST 24
Finished Feb 07 02:20:53 PM PST 24
Peak memory 378552 kb
Host smart-082c325f-a07d-411b-b7e8-15c38112acc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676957795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.2676957795
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1889074503
Short name T546
Test name
Test status
Simulation time 102818673 ps
CPU time 0.63 seconds
Started Feb 07 02:02:21 PM PST 24
Finished Feb 07 02:02:32 PM PST 24
Peak memory 201492 kb
Host smart-c5bb92ea-f85a-4c9d-af1d-8f252507c706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889074503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1889074503
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.1566848211
Short name T320
Test name
Test status
Simulation time 51841424382 ps
CPU time 1100.57 seconds
Started Feb 07 02:02:15 PM PST 24
Finished Feb 07 02:20:52 PM PST 24
Peak memory 202244 kb
Host smart-befdda84-88cf-4e05-bd14-ca934cd1b8a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566848211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.1566848211
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.3421760595
Short name T136
Test name
Test status
Simulation time 55281559954 ps
CPU time 293 seconds
Started Feb 07 02:02:12 PM PST 24
Finished Feb 07 02:07:25 PM PST 24
Peak memory 202180 kb
Host smart-89a1a8ef-96d7-4236-9499-8fea1c05a4e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421760595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es
calation.3421760595
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1806891433
Short name T613
Test name
Test status
Simulation time 685487777 ps
CPU time 27.4 seconds
Started Feb 07 02:02:15 PM PST 24
Finished Feb 07 02:02:59 PM PST 24
Peak memory 211340 kb
Host smart-9d84259a-5fc6-44f3-98c6-80086d0e81d7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806891433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1806891433
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.1638955763
Short name T902
Test name
Test status
Simulation time 8747575595 ps
CPU time 155.89 seconds
Started Feb 07 02:02:18 PM PST 24
Finished Feb 07 02:05:08 PM PST 24
Peak memory 214720 kb
Host smart-3cf32f76-b4ef-4434-9d51-ebdd4dee6e0e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638955763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.1638955763
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.585500218
Short name T702
Test name
Test status
Simulation time 42111838464 ps
CPU time 306.9 seconds
Started Feb 07 02:02:12 PM PST 24
Finished Feb 07 02:07:39 PM PST 24
Peak memory 202592 kb
Host smart-1dd2031f-7f64-434c-a133-90a22f199769
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585500218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_mem_walk.585500218
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.3255572684
Short name T494
Test name
Test status
Simulation time 24427224597 ps
CPU time 743.45 seconds
Started Feb 07 02:02:12 PM PST 24
Finished Feb 07 02:14:56 PM PST 24
Peak memory 379008 kb
Host smart-6de1347d-b4f9-4342-a949-a53c8c3eea4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255572684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.3255572684
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.1305879824
Short name T227
Test name
Test status
Simulation time 855120895 ps
CPU time 14.28 seconds
Started Feb 07 02:02:13 PM PST 24
Finished Feb 07 02:02:46 PM PST 24
Peak memory 202104 kb
Host smart-006e8747-d5e3-4517-8e5a-83315e1e51b2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305879824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.1305879824
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1756783659
Short name T853
Test name
Test status
Simulation time 12482808781 ps
CPU time 280.63 seconds
Started Feb 07 02:02:11 PM PST 24
Finished Feb 07 02:07:12 PM PST 24
Peak memory 210336 kb
Host smart-bcb49e90-338f-40ce-8e37-580d752344a0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756783659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.1756783659
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.4248599585
Short name T383
Test name
Test status
Simulation time 1526536748 ps
CPU time 13.18 seconds
Started Feb 07 02:02:25 PM PST 24
Finished Feb 07 02:02:45 PM PST 24
Peak memory 202332 kb
Host smart-bd55aa10-3a37-4d52-8b75-a5912cf49572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248599585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.4248599585
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.2671478621
Short name T364
Test name
Test status
Simulation time 8034283805 ps
CPU time 690.09 seconds
Started Feb 07 02:02:19 PM PST 24
Finished Feb 07 02:14:02 PM PST 24
Peak memory 374896 kb
Host smart-70713092-83e8-4288-ac45-7ba9531da025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671478621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2671478621
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.4048838099
Short name T455
Test name
Test status
Simulation time 3566542001 ps
CPU time 146.34 seconds
Started Feb 07 02:02:14 PM PST 24
Finished Feb 07 02:04:58 PM PST 24
Peak memory 356708 kb
Host smart-400f7e0b-3ac7-431a-b082-2386b622fc96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048838099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4048838099
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.367842914
Short name T129
Test name
Test status
Simulation time 77537880264 ps
CPU time 2750.89 seconds
Started Feb 07 02:02:22 PM PST 24
Finished Feb 07 02:48:23 PM PST 24
Peak memory 377068 kb
Host smart-e276b822-a2f2-42b8-8a7e-6b58d14e3699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367842914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_stress_all.367842914
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1888575747
Short name T573
Test name
Test status
Simulation time 442194055 ps
CPU time 2727.68 seconds
Started Feb 07 02:02:20 PM PST 24
Finished Feb 07 02:48:00 PM PST 24
Peak memory 409892 kb
Host smart-4545e2d1-f59f-42db-af38-d16b6e9d9bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1888575747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1888575747
Directory /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1123617298
Short name T460
Test name
Test status
Simulation time 42564224018 ps
CPU time 447.18 seconds
Started Feb 07 02:02:12 PM PST 24
Finished Feb 07 02:09:59 PM PST 24
Peak memory 202244 kb
Host smart-038d58b2-70e9-4e4e-a71a-e499074b005a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123617298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1123617298
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3102412355
Short name T536
Test name
Test status
Simulation time 763537177 ps
CPU time 50.02 seconds
Started Feb 07 02:02:12 PM PST 24
Finished Feb 07 02:03:22 PM PST 24
Peak memory 267516 kb
Host smart-1393038f-1f2a-4ab7-9267-363fbdf06690
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102412355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.3102412355
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.4120966477
Short name T823
Test name
Test status
Simulation time 4931889038 ps
CPU time 295.04 seconds
Started Feb 07 02:02:23 PM PST 24
Finished Feb 07 02:07:27 PM PST 24
Peak memory 366644 kb
Host smart-b896ecd0-5504-4822-a83e-5656a93f9298
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120966477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.4120966477
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.578234337
Short name T921
Test name
Test status
Simulation time 12894842 ps
CPU time 0.66 seconds
Started Feb 07 02:02:23 PM PST 24
Finished Feb 07 02:02:32 PM PST 24
Peak memory 201876 kb
Host smart-96f42cd0-86b7-4f56-9132-ef4882a71dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578234337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.578234337
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.1120800019
Short name T50
Test name
Test status
Simulation time 55749600745 ps
CPU time 659.53 seconds
Started Feb 07 02:02:24 PM PST 24
Finished Feb 07 02:13:31 PM PST 24
Peak memory 202168 kb
Host smart-efdd971c-3bbb-41cf-88ec-02ffd68c98a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120800019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.1120800019
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.1936752246
Short name T488
Test name
Test status
Simulation time 110792739630 ps
CPU time 1531.52 seconds
Started Feb 07 02:02:21 PM PST 24
Finished Feb 07 02:28:03 PM PST 24
Peak memory 378092 kb
Host smart-1a82d082-88cd-4a11-be6c-7f5d4dfda9bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936752246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab
le.1936752246
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.116953665
Short name T31
Test name
Test status
Simulation time 48605255488 ps
CPU time 249.52 seconds
Started Feb 07 02:02:43 PM PST 24
Finished Feb 07 02:06:56 PM PST 24
Peak memory 210448 kb
Host smart-bdd57a52-8899-4e60-9f22-6ff9880c3042
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116953665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_esc
alation.116953665
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.783841253
Short name T944
Test name
Test status
Simulation time 2988220032 ps
CPU time 64.29 seconds
Started Feb 07 02:02:19 PM PST 24
Finished Feb 07 02:03:36 PM PST 24
Peak memory 285024 kb
Host smart-3126f7d1-7d83-4a98-a307-daa94cc79763
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783841253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.783841253
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.3585710344
Short name T867
Test name
Test status
Simulation time 4004945765 ps
CPU time 72.79 seconds
Started Feb 07 02:02:24 PM PST 24
Finished Feb 07 02:03:44 PM PST 24
Peak memory 211428 kb
Host smart-4300276d-42df-477f-8bbc-5dc1ca730276
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585710344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.3585710344
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.1391227093
Short name T758
Test name
Test status
Simulation time 21967861228 ps
CPU time 309.27 seconds
Started Feb 07 02:02:21 PM PST 24
Finished Feb 07 02:07:41 PM PST 24
Peak memory 202460 kb
Host smart-622320f4-337f-407d-852c-87bf9911e5c4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391227093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.1391227093
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.2516746637
Short name T908
Test name
Test status
Simulation time 819673577 ps
CPU time 71.52 seconds
Started Feb 07 02:02:22 PM PST 24
Finished Feb 07 02:03:44 PM PST 24
Peak memory 300248 kb
Host smart-a8f9a487-0ff9-4d7a-b38f-79780f27582b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516746637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.2516746637
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.2340104663
Short name T916
Test name
Test status
Simulation time 382050064 ps
CPU time 15.71 seconds
Started Feb 07 02:02:27 PM PST 24
Finished Feb 07 02:02:47 PM PST 24
Peak memory 213564 kb
Host smart-037000a5-7e6f-40eb-b95b-6ffbbd545169
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340104663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.2340104663
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1389509945
Short name T644
Test name
Test status
Simulation time 7468898628 ps
CPU time 244.53 seconds
Started Feb 07 02:02:21 PM PST 24
Finished Feb 07 02:06:36 PM PST 24
Peak memory 202280 kb
Host smart-7b8a4a5d-d602-428a-9688-c123461a21e2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389509945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.1389509945
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.2118117388
Short name T832
Test name
Test status
Simulation time 1401332615 ps
CPU time 13.48 seconds
Started Feb 07 02:02:43 PM PST 24
Finished Feb 07 02:03:00 PM PST 24
Peak memory 202400 kb
Host smart-c78827f2-4f6f-4d99-a97d-42853fdc0d4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118117388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2118117388
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.466493385
Short name T131
Test name
Test status
Simulation time 5355898057 ps
CPU time 689.46 seconds
Started Feb 07 02:02:22 PM PST 24
Finished Feb 07 02:14:01 PM PST 24
Peak memory 370852 kb
Host smart-aa6655a3-d1d9-4a3e-9fa1-d2b83b414897
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466493385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.466493385
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.2667062518
Short name T701
Test name
Test status
Simulation time 2694517808 ps
CPU time 25.3 seconds
Started Feb 07 02:02:22 PM PST 24
Finished Feb 07 02:02:57 PM PST 24
Peak memory 202208 kb
Host smart-55339173-63d6-478a-b939-f8ddc3ae1535
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667062518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2667062518
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.4161299522
Short name T325
Test name
Test status
Simulation time 1126833239 ps
CPU time 3398.28 seconds
Started Feb 07 02:02:22 PM PST 24
Finished Feb 07 02:59:10 PM PST 24
Peak memory 619132 kb
Host smart-5d1691cd-0d0d-4b2b-a18f-1f0576ab6c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4161299522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.4161299522
Directory /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.4192983782
Short name T242
Test name
Test status
Simulation time 40950267035 ps
CPU time 358.41 seconds
Started Feb 07 02:02:18 PM PST 24
Finished Feb 07 02:08:30 PM PST 24
Peak memory 202204 kb
Host smart-103a5c82-d949-49a8-b70c-42235b67d0d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192983782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.4192983782
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1109541936
Short name T776
Test name
Test status
Simulation time 715202445 ps
CPU time 42.29 seconds
Started Feb 07 02:02:24 PM PST 24
Finished Feb 07 02:03:14 PM PST 24
Peak memory 267428 kb
Host smart-d1a96666-4935-48ed-be57-9f879e914a6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109541936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.1109541936
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3209830488
Short name T405
Test name
Test status
Simulation time 30479816968 ps
CPU time 1094.9 seconds
Started Feb 07 02:02:40 PM PST 24
Finished Feb 07 02:20:58 PM PST 24
Peak memory 377412 kb
Host smart-c8cfc37f-c1e0-41f4-a8a1-94acabcfc99d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209830488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.3209830488
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.3057830811
Short name T778
Test name
Test status
Simulation time 31017322 ps
CPU time 0.62 seconds
Started Feb 07 02:02:44 PM PST 24
Finished Feb 07 02:02:48 PM PST 24
Peak memory 201476 kb
Host smart-e4435871-240a-4694-bae1-6c5c6ea91de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057830811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.3057830811
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.2176831314
Short name T822
Test name
Test status
Simulation time 105961281580 ps
CPU time 1003.86 seconds
Started Feb 07 02:02:19 PM PST 24
Finished Feb 07 02:19:16 PM PST 24
Peak memory 202228 kb
Host smart-2110515c-52c3-4f6a-8aea-275bf73cb2a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176831314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.2176831314
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.782246491
Short name T278
Test name
Test status
Simulation time 19594100330 ps
CPU time 214.31 seconds
Started Feb 07 02:02:43 PM PST 24
Finished Feb 07 02:06:21 PM PST 24
Peak memory 213952 kb
Host smart-c7388a95-9536-4334-ac2b-041eedfd1cf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782246491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc
alation.782246491
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.1123900933
Short name T829
Test name
Test status
Simulation time 829373067 ps
CPU time 177.13 seconds
Started Feb 07 02:02:18 PM PST 24
Finished Feb 07 02:05:29 PM PST 24
Peak memory 370716 kb
Host smart-12a42c74-f30b-4265-891e-a7b458f8d4c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123900933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.1123900933
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1750395197
Short name T372
Test name
Test status
Simulation time 4701160855 ps
CPU time 149.82 seconds
Started Feb 07 02:02:40 PM PST 24
Finished Feb 07 02:05:12 PM PST 24
Peak memory 214652 kb
Host smart-fe2847c0-b827-4b51-9241-379622410550
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750395197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.1750395197
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.2924670912
Short name T309
Test name
Test status
Simulation time 10339080877 ps
CPU time 147.39 seconds
Started Feb 07 02:02:45 PM PST 24
Finished Feb 07 02:05:14 PM PST 24
Peak memory 202276 kb
Host smart-5793672f-d8cf-42a8-a1a4-368b6fb99647
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924670912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.2924670912
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.807556312
Short name T715
Test name
Test status
Simulation time 15733348921 ps
CPU time 856.94 seconds
Started Feb 07 02:02:22 PM PST 24
Finished Feb 07 02:16:49 PM PST 24
Peak memory 372320 kb
Host smart-cc43703a-9b07-4872-af45-906303e7aefa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807556312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multip
le_keys.807556312
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.3090705099
Short name T142
Test name
Test status
Simulation time 6924722589 ps
CPU time 23.85 seconds
Started Feb 07 02:02:27 PM PST 24
Finished Feb 07 02:02:56 PM PST 24
Peak memory 202248 kb
Host smart-7659ca69-7e0c-40e9-9d7c-ae796ca72604
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090705099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.3090705099
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.3965998728
Short name T480
Test name
Test status
Simulation time 7260608733 ps
CPU time 445.28 seconds
Started Feb 07 02:02:27 PM PST 24
Finished Feb 07 02:09:57 PM PST 24
Peak memory 202248 kb
Host smart-dabdd760-129c-4870-a5ab-fcf66d94331f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965998728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.3965998728
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.1469467606
Short name T887
Test name
Test status
Simulation time 1398246442 ps
CPU time 5.42 seconds
Started Feb 07 02:02:39 PM PST 24
Finished Feb 07 02:02:48 PM PST 24
Peak memory 202356 kb
Host smart-8754a0d7-f38b-48a9-ac30-b7333549082e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469467606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1469467606
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.3717024099
Short name T130
Test name
Test status
Simulation time 6724158704 ps
CPU time 179.92 seconds
Started Feb 07 02:02:37 PM PST 24
Finished Feb 07 02:05:38 PM PST 24
Peak memory 374916 kb
Host smart-326096bb-9339-4fac-9297-4f597c0b9431
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717024099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3717024099
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.1449314086
Short name T609
Test name
Test status
Simulation time 3752040869 ps
CPU time 84.27 seconds
Started Feb 07 02:02:24 PM PST 24
Finished Feb 07 02:03:56 PM PST 24
Peak memory 339168 kb
Host smart-5a089092-cb18-460f-8cd8-2d0882b2f789
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449314086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1449314086
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.1466548439
Short name T939
Test name
Test status
Simulation time 359013558381 ps
CPU time 3178.65 seconds
Started Feb 07 02:02:40 PM PST 24
Finished Feb 07 02:55:42 PM PST 24
Peak memory 377100 kb
Host smart-16b184be-525a-400a-9a53-96a803952def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466548439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.1466548439
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3272975295
Short name T768
Test name
Test status
Simulation time 4814042969 ps
CPU time 6426.36 seconds
Started Feb 07 02:02:45 PM PST 24
Finished Feb 07 03:49:54 PM PST 24
Peak memory 758132 kb
Host smart-e37cfd8e-f9b9-46b1-8214-3ff0ddf4d1c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3272975295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3272975295
Directory /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.655253931
Short name T593
Test name
Test status
Simulation time 4793501581 ps
CPU time 358.89 seconds
Started Feb 07 02:02:22 PM PST 24
Finished Feb 07 02:08:31 PM PST 24
Peak memory 202264 kb
Host smart-3082f2f0-b9e6-441e-8278-552149ac0439
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655253931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_stress_pipeline.655253931
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1232702628
Short name T781
Test name
Test status
Simulation time 739117725 ps
CPU time 49.67 seconds
Started Feb 07 02:02:44 PM PST 24
Finished Feb 07 02:03:37 PM PST 24
Peak memory 283944 kb
Host smart-0806208c-09e2-4f77-a588-352862a8185a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232702628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1232702628
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.2464074794
Short name T299
Test name
Test status
Simulation time 4342699266 ps
CPU time 439.76 seconds
Started Feb 07 02:02:42 PM PST 24
Finished Feb 07 02:10:03 PM PST 24
Peak memory 376000 kb
Host smart-624679b3-013d-4695-bf66-0a6f68ce685c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464074794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.2464074794
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.3604771958
Short name T567
Test name
Test status
Simulation time 44235896 ps
CPU time 0.65 seconds
Started Feb 07 02:02:37 PM PST 24
Finished Feb 07 02:02:42 PM PST 24
Peak memory 201848 kb
Host smart-1c82f403-2a09-4220-affc-ad5296e1ba9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604771958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.3604771958
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.3246246446
Short name T262
Test name
Test status
Simulation time 33480207004 ps
CPU time 2153.86 seconds
Started Feb 07 02:02:44 PM PST 24
Finished Feb 07 02:38:41 PM PST 24
Peak memory 202208 kb
Host smart-74c3657a-baae-4290-bfd7-7abce9866d8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246246446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.3246246446
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.1159801471
Short name T726
Test name
Test status
Simulation time 11312290008 ps
CPU time 32.27 seconds
Started Feb 07 02:02:41 PM PST 24
Finished Feb 07 02:03:15 PM PST 24
Peak memory 232708 kb
Host smart-c3894e1c-0da8-4aa9-a4ad-d1064b2176fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159801471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.1159801471
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1666616075
Short name T565
Test name
Test status
Simulation time 4559903343 ps
CPU time 145.69 seconds
Started Feb 07 02:02:39 PM PST 24
Finished Feb 07 02:05:08 PM PST 24
Peak memory 210384 kb
Host smart-0db94a15-7cf2-48f9-ab8b-5a5f829cc9a9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666616075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.1666616075
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.721605218
Short name T137
Test name
Test status
Simulation time 44948097465 ps
CPU time 165.55 seconds
Started Feb 07 02:02:44 PM PST 24
Finished Feb 07 02:05:33 PM PST 24
Peak memory 202236 kb
Host smart-dbe0a349-5a56-4907-853e-c4f73481a058
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721605218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl
_mem_walk.721605218
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.479558813
Short name T537
Test name
Test status
Simulation time 8245071128 ps
CPU time 515.79 seconds
Started Feb 07 02:02:45 PM PST 24
Finished Feb 07 02:11:23 PM PST 24
Peak memory 379016 kb
Host smart-cf24035b-04a7-46a3-8ac0-6a585f0a227a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479558813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip
le_keys.479558813
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.3656415098
Short name T219
Test name
Test status
Simulation time 809452041 ps
CPU time 102.42 seconds
Started Feb 07 02:02:39 PM PST 24
Finished Feb 07 02:04:25 PM PST 24
Peak memory 320872 kb
Host smart-95bc0cfb-c272-46fd-834f-04dfa7fc8408
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656415098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.3656415098
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1419537760
Short name T101
Test name
Test status
Simulation time 71167024080 ps
CPU time 415.84 seconds
Started Feb 07 02:02:41 PM PST 24
Finished Feb 07 02:09:39 PM PST 24
Peak memory 202172 kb
Host smart-c904a969-e8bf-45c2-9dcf-f052958a3ee9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419537760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.1419537760
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.3222213028
Short name T909
Test name
Test status
Simulation time 1091813247 ps
CPU time 13.58 seconds
Started Feb 07 02:02:38 PM PST 24
Finished Feb 07 02:02:56 PM PST 24
Peak memory 202380 kb
Host smart-652b57b9-f214-49fe-a877-50f7f748cfcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222213028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3222213028
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.2828241728
Short name T328
Test name
Test status
Simulation time 48465112563 ps
CPU time 1234.91 seconds
Started Feb 07 02:02:37 PM PST 24
Finished Feb 07 02:23:17 PM PST 24
Peak memory 370836 kb
Host smart-e1d107b8-405b-4895-8f78-2af0b3489724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828241728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2828241728
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.283983113
Short name T952
Test name
Test status
Simulation time 6991500874 ps
CPU time 16.1 seconds
Started Feb 07 02:02:37 PM PST 24
Finished Feb 07 02:02:54 PM PST 24
Peak memory 210380 kb
Host smart-1262491c-7f28-481f-bd81-865684c6b31d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283983113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.283983113
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2199464938
Short name T426
Test name
Test status
Simulation time 86495954190 ps
CPU time 4411.77 seconds
Started Feb 07 02:02:36 PM PST 24
Finished Feb 07 03:16:10 PM PST 24
Peak memory 725424 kb
Host smart-3bde61bb-77c7-4541-8d2d-1abd763ae12a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2199464938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2199464938
Directory /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2453975097
Short name T744
Test name
Test status
Simulation time 11549186680 ps
CPU time 297.52 seconds
Started Feb 07 02:02:40 PM PST 24
Finished Feb 07 02:07:40 PM PST 24
Peak memory 201572 kb
Host smart-98562fb8-273e-49c1-bcbf-0616e80c7e91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453975097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.2453975097
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2887637539
Short name T830
Test name
Test status
Simulation time 715759820 ps
CPU time 45.19 seconds
Started Feb 07 02:02:42 PM PST 24
Finished Feb 07 02:03:29 PM PST 24
Peak memory 267480 kb
Host smart-84283da4-e5ff-4bf9-bdaa-c29e6404b8be
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887637539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.2887637539
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.367165149
Short name T363
Test name
Test status
Simulation time 2336360878 ps
CPU time 426.7 seconds
Started Feb 07 02:02:45 PM PST 24
Finished Feb 07 02:09:54 PM PST 24
Peak memory 359168 kb
Host smart-0da5799f-0d3e-4c4c-b0c5-dc8d2ba335d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367165149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.sram_ctrl_access_during_key_req.367165149
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.820142748
Short name T943
Test name
Test status
Simulation time 12944403 ps
CPU time 0.62 seconds
Started Feb 07 02:02:55 PM PST 24
Finished Feb 07 02:02:57 PM PST 24
Peak memory 201784 kb
Host smart-3ce43980-f0f8-4b1e-b186-37624b6026d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820142748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.820142748
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.4199316163
Short name T290
Test name
Test status
Simulation time 230732735779 ps
CPU time 1334.29 seconds
Started Feb 07 02:02:41 PM PST 24
Finished Feb 07 02:24:57 PM PST 24
Peak memory 202288 kb
Host smart-81828a27-979a-4215-9704-359749ed1568
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199316163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.4199316163
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.2481546019
Short name T345
Test name
Test status
Simulation time 54217040568 ps
CPU time 876.44 seconds
Started Feb 07 02:02:53 PM PST 24
Finished Feb 07 02:17:32 PM PST 24
Peak memory 378032 kb
Host smart-45d4a95d-bfb4-473d-b0e1-c861a094eecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481546019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.2481546019
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.3610869937
Short name T509
Test name
Test status
Simulation time 40991741230 ps
CPU time 115.35 seconds
Started Feb 07 02:02:45 PM PST 24
Finished Feb 07 02:04:42 PM PST 24
Peak memory 213960 kb
Host smart-96c1dbd1-25ff-4359-bf3b-8f72fd22bcbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610869937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.3610869937
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.3301536472
Short name T787
Test name
Test status
Simulation time 2719322372 ps
CPU time 49.58 seconds
Started Feb 07 02:02:44 PM PST 24
Finished Feb 07 02:03:37 PM PST 24
Peak memory 267480 kb
Host smart-d9d6c702-4989-4520-a0af-c8a86343aa74
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301536472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.3301536472
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2616714735
Short name T393
Test name
Test status
Simulation time 3952006390 ps
CPU time 71.8 seconds
Started Feb 07 02:02:52 PM PST 24
Finished Feb 07 02:04:07 PM PST 24
Peak memory 211276 kb
Host smart-74321376-8503-4901-b71c-420775bad0e9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616714735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.2616714735
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.4071258815
Short name T629
Test name
Test status
Simulation time 4116217929 ps
CPU time 117.46 seconds
Started Feb 07 02:02:47 PM PST 24
Finished Feb 07 02:04:46 PM PST 24
Peak memory 202168 kb
Host smart-60f34233-4621-4b85-87f4-9c1589808966
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071258815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.4071258815
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.1527821060
Short name T285
Test name
Test status
Simulation time 16421337027 ps
CPU time 422.92 seconds
Started Feb 07 02:02:37 PM PST 24
Finished Feb 07 02:09:41 PM PST 24
Peak memory 373880 kb
Host smart-b863010a-a70c-4d42-8c76-def0044eec6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527821060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.1527821060
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.3517581998
Short name T243
Test name
Test status
Simulation time 1455430755 ps
CPU time 37.6 seconds
Started Feb 07 02:02:46 PM PST 24
Finished Feb 07 02:03:25 PM PST 24
Peak memory 237468 kb
Host smart-b1df4cdf-8419-4ef2-ace8-f30d6867ee46
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517581998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.3517581998
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3806444889
Short name T751
Test name
Test status
Simulation time 15970491658 ps
CPU time 370.32 seconds
Started Feb 07 02:02:45 PM PST 24
Finished Feb 07 02:08:57 PM PST 24
Peak memory 202160 kb
Host smart-c41ef0d3-6f7c-4af4-9953-be5fe9eefa2e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806444889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.3806444889
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.1662188828
Short name T681
Test name
Test status
Simulation time 689467732 ps
CPU time 5.71 seconds
Started Feb 07 02:02:48 PM PST 24
Finished Feb 07 02:02:54 PM PST 24
Peak memory 202312 kb
Host smart-18f94075-47b4-4cba-9881-83feb0432ee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662188828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1662188828
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.175049414
Short name T796
Test name
Test status
Simulation time 4990200378 ps
CPU time 432.97 seconds
Started Feb 07 02:02:44 PM PST 24
Finished Feb 07 02:10:00 PM PST 24
Peak memory 373912 kb
Host smart-e02a8868-2a18-43aa-aa3e-fc9e8ed36a0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175049414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.175049414
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.942043977
Short name T490
Test name
Test status
Simulation time 893243752 ps
CPU time 41.89 seconds
Started Feb 07 02:02:38 PM PST 24
Finished Feb 07 02:03:24 PM PST 24
Peak memory 202068 kb
Host smart-7da1e6ba-913a-4e4c-b682-eea01632cdcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942043977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.942043977
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.244663114
Short name T213
Test name
Test status
Simulation time 5075058215 ps
CPU time 3545.78 seconds
Started Feb 07 02:02:46 PM PST 24
Finished Feb 07 03:01:54 PM PST 24
Peak memory 811040 kb
Host smart-26793668-7c82-4277-9621-3ba1f45efb5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=244663114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.244663114
Directory /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1256546577
Short name T106
Test name
Test status
Simulation time 3829294883 ps
CPU time 310.89 seconds
Started Feb 07 02:02:38 PM PST 24
Finished Feb 07 02:07:53 PM PST 24
Peak memory 202244 kb
Host smart-f8a22662-5012-429a-ab69-40db387c1e21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256546577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.1256546577
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.3858065358
Short name T800
Test name
Test status
Simulation time 1685908049 ps
CPU time 78.17 seconds
Started Feb 07 02:02:45 PM PST 24
Finished Feb 07 02:04:05 PM PST 24
Peak memory 331904 kb
Host smart-af3c57e3-5723-4182-bfec-eb1a9e9b0b04
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858065358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.3858065358
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2693288728
Short name T86
Test name
Test status
Simulation time 7135719959 ps
CPU time 115.18 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:05:17 PM PST 24
Peak memory 307248 kb
Host smart-7753331e-ff99-41b0-b92c-10923971d17b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693288728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.2693288728
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.2255185498
Short name T672
Test name
Test status
Simulation time 15861334 ps
CPU time 0.65 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:03:23 PM PST 24
Peak memory 201888 kb
Host smart-3e1a11f5-c395-4a34-bc65-39566fde57a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255185498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.2255185498
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.1540411874
Short name T590
Test name
Test status
Simulation time 167193947744 ps
CPU time 2724.51 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:48:47 PM PST 24
Peak memory 202164 kb
Host smart-ffc2a68b-c955-4bef-a4cc-519808763977
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540411874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.1540411874
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.1858994686
Short name T308
Test name
Test status
Simulation time 2555746689 ps
CPU time 59.76 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:04:22 PM PST 24
Peak memory 283964 kb
Host smart-25b24e0e-6353-479a-9bfa-018021abce70
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858994686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.1858994686
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.354986248
Short name T561
Test name
Test status
Simulation time 4284215922 ps
CPU time 73.36 seconds
Started Feb 07 02:03:21 PM PST 24
Finished Feb 07 02:04:36 PM PST 24
Peak memory 211284 kb
Host smart-761311ba-4446-4084-962e-16709d3e8c66
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354986248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.sram_ctrl_mem_partial_access.354986248
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.555447193
Short name T936
Test name
Test status
Simulation time 8233403892 ps
CPU time 127.86 seconds
Started Feb 07 02:03:22 PM PST 24
Finished Feb 07 02:05:33 PM PST 24
Peak memory 202244 kb
Host smart-2771fe22-4651-47ad-8535-e99abc068731
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555447193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_mem_walk.555447193
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.2376888327
Short name T382
Test name
Test status
Simulation time 14790311784 ps
CPU time 2719.68 seconds
Started Feb 07 02:02:58 PM PST 24
Finished Feb 07 02:48:19 PM PST 24
Peak memory 378484 kb
Host smart-cafb568b-ebd9-4b98-87e2-99ffdee7b420
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376888327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.2376888327
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.2067494499
Short name T635
Test name
Test status
Simulation time 5060252336 ps
CPU time 23.84 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:03:46 PM PST 24
Peak memory 202120 kb
Host smart-d048b51c-b2de-4fd5-9e8d-e43f7338d267
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067494499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.2067494499
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1557620454
Short name T805
Test name
Test status
Simulation time 36255544265 ps
CPU time 454.07 seconds
Started Feb 07 02:03:22 PM PST 24
Finished Feb 07 02:11:00 PM PST 24
Peak memory 202144 kb
Host smart-d6d241fb-e7cf-45e1-abe9-7ed1bbc202f8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557620454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.1557620454
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.2237735101
Short name T580
Test name
Test status
Simulation time 8943881962 ps
CPU time 1184.61 seconds
Started Feb 07 02:03:18 PM PST 24
Finished Feb 07 02:23:06 PM PST 24
Peak memory 371872 kb
Host smart-33c3d843-11e4-4138-8290-e3d7943695d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237735101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2237735101
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.3109906680
Short name T249
Test name
Test status
Simulation time 1490727293 ps
CPU time 31.43 seconds
Started Feb 07 02:02:58 PM PST 24
Finished Feb 07 02:03:31 PM PST 24
Peak memory 202080 kb
Host smart-6d78e5a9-d036-4b4c-a4a2-4731e74bf625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109906680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.3109906680
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3743359075
Short name T653
Test name
Test status
Simulation time 2547110552 ps
CPU time 4798.23 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 03:23:20 PM PST 24
Peak memory 418788 kb
Host smart-139f89fa-68bd-4e53-9198-ceb7888ab5b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3743359075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3743359075
Directory /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3769305498
Short name T841
Test name
Test status
Simulation time 6009627050 ps
CPU time 231.01 seconds
Started Feb 07 02:03:21 PM PST 24
Finished Feb 07 02:07:14 PM PST 24
Peak memory 202240 kb
Host smart-8b7447d3-adf2-4a91-a2a4-44cf3e75ffe4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769305498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.3769305498
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1460037040
Short name T228
Test name
Test status
Simulation time 2586065168 ps
CPU time 27.61 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:03:50 PM PST 24
Peak memory 215540 kb
Host smart-d7c3b0c4-951a-4b53-a75e-b31f697f9baf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460037040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1460037040
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.789077232
Short name T772
Test name
Test status
Simulation time 14752886446 ps
CPU time 873.59 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:17:56 PM PST 24
Peak memory 375024 kb
Host smart-6e2f1632-a00c-4d62-b09e-b8f18bd3071c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789077232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.sram_ctrl_access_during_key_req.789077232
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.3408482236
Short name T647
Test name
Test status
Simulation time 45089630 ps
CPU time 0.63 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:03:22 PM PST 24
Peak memory 201844 kb
Host smart-bf3009af-6522-4036-8d6e-16d3cc4f1290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408482236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.3408482236
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.664817725
Short name T497
Test name
Test status
Simulation time 135885188084 ps
CPU time 673.82 seconds
Started Feb 07 02:03:18 PM PST 24
Finished Feb 07 02:14:36 PM PST 24
Peak memory 202260 kb
Host smart-a777d6d2-4f22-4a6c-81e1-d2755626dc1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664817725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.
664817725
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.799015905
Short name T652
Test name
Test status
Simulation time 43303699100 ps
CPU time 1623 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:30:25 PM PST 24
Peak memory 375004 kb
Host smart-75584f7e-6f0b-4dd1-b7ef-02d9d3d533b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799015905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl
e.799015905
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.4015230712
Short name T740
Test name
Test status
Simulation time 17791702381 ps
CPU time 85.65 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:04:47 PM PST 24
Peak memory 202156 kb
Host smart-154bd3a9-242d-4998-95e5-4aed0520814a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015230712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.4015230712
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3322786226
Short name T860
Test name
Test status
Simulation time 727834215 ps
CPU time 63 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:04:25 PM PST 24
Peak memory 289016 kb
Host smart-7ceb8e12-c282-4eaa-903d-fa56d3b4db42
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322786226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3322786226
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.1169788823
Short name T907
Test name
Test status
Simulation time 2701228820 ps
CPU time 79.4 seconds
Started Feb 07 02:03:24 PM PST 24
Finished Feb 07 02:04:46 PM PST 24
Peak memory 211140 kb
Host smart-41fdea07-b0cf-46e5-8134-ed77acc4f03d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169788823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.1169788823
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.1900612002
Short name T858
Test name
Test status
Simulation time 44879330074 ps
CPU time 153.02 seconds
Started Feb 07 02:03:21 PM PST 24
Finished Feb 07 02:05:58 PM PST 24
Peak memory 202548 kb
Host smart-9da96701-5179-4688-a3e7-9feec31b6b79
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900612002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.1900612002
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.1886081315
Short name T235
Test name
Test status
Simulation time 13111337622 ps
CPU time 688.16 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:14:50 PM PST 24
Peak memory 358632 kb
Host smart-ba2f5715-f311-4d02-8bdd-af67f6002373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886081315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.1886081315
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.3009762260
Short name T816
Test name
Test status
Simulation time 1065836146 ps
CPU time 52.85 seconds
Started Feb 07 02:03:21 PM PST 24
Finished Feb 07 02:04:16 PM PST 24
Peak memory 290632 kb
Host smart-c825ab28-13c6-4624-a6e9-4315b5903cb8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009762260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.3009762260
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2215485350
Short name T348
Test name
Test status
Simulation time 12614909488 ps
CPU time 412.38 seconds
Started Feb 07 02:03:21 PM PST 24
Finished Feb 07 02:10:15 PM PST 24
Peak memory 202212 kb
Host smart-8af5b4a8-f740-4290-8b07-9888e47a2398
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215485350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.2215485350
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.2128932164
Short name T433
Test name
Test status
Simulation time 718351049 ps
CPU time 13.62 seconds
Started Feb 07 02:03:18 PM PST 24
Finished Feb 07 02:03:35 PM PST 24
Peak memory 202484 kb
Host smart-d8069532-d090-43ab-8891-d3a049042860
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128932164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2128932164
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.1649693302
Short name T48
Test name
Test status
Simulation time 2031712472 ps
CPU time 858.95 seconds
Started Feb 07 02:03:21 PM PST 24
Finished Feb 07 02:17:44 PM PST 24
Peak memory 375876 kb
Host smart-a82cb3b9-769c-40eb-93a3-4afe7b283afe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649693302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1649693302
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.498647993
Short name T514
Test name
Test status
Simulation time 2688242805 ps
CPU time 27.81 seconds
Started Feb 07 02:03:18 PM PST 24
Finished Feb 07 02:03:50 PM PST 24
Peak memory 202196 kb
Host smart-4e2b3f65-7536-409c-8417-12cd413146cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498647993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.498647993
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.2298860072
Short name T621
Test name
Test status
Simulation time 85872922559 ps
CPU time 3351.57 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:59:14 PM PST 24
Peak memory 382136 kb
Host smart-8eeb5189-ca81-4f20-b6b9-5803fed0c577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298860072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.2298860072
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2126957251
Short name T531
Test name
Test status
Simulation time 1393821898 ps
CPU time 6991.44 seconds
Started Feb 07 02:03:25 PM PST 24
Finished Feb 07 03:59:58 PM PST 24
Peak memory 651200 kb
Host smart-a9816472-31cc-4c89-898d-52dc427891ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2126957251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.2126957251
Directory /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.267520550
Short name T373
Test name
Test status
Simulation time 3005153450 ps
CPU time 203.24 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:06:45 PM PST 24
Peak memory 202220 kb
Host smart-f7bcdd53-7be9-4bec-acf0-691bed09ba3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267520550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.sram_ctrl_stress_pipeline.267520550
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.707510093
Short name T625
Test name
Test status
Simulation time 2700004742 ps
CPU time 124.23 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:05:26 PM PST 24
Peak memory 365740 kb
Host smart-79f4292b-82c3-4dc5-b96f-89ee5247bc83
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707510093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.707510093
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.4256425803
Short name T338
Test name
Test status
Simulation time 13095181803 ps
CPU time 914.78 seconds
Started Feb 07 02:03:26 PM PST 24
Finished Feb 07 02:18:42 PM PST 24
Peak memory 373956 kb
Host smart-c570344c-dc4b-4b31-873c-277e4319c9fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256425803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.4256425803
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.3828124066
Short name T27
Test name
Test status
Simulation time 36417728 ps
CPU time 0.66 seconds
Started Feb 07 02:03:37 PM PST 24
Finished Feb 07 02:03:39 PM PST 24
Peak memory 201428 kb
Host smart-588aed42-dea6-40f5-a72f-15b82146d2a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828124066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.3828124066
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.41250389
Short name T44
Test name
Test status
Simulation time 997044319642 ps
CPU time 1808.45 seconds
Started Feb 07 02:03:18 PM PST 24
Finished Feb 07 02:33:30 PM PST 24
Peak memory 202172 kb
Host smart-dd6e5d37-af76-4c67-b916-19cdde3ca2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41250389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.41250389
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.1726021073
Short name T43
Test name
Test status
Simulation time 2664259949 ps
CPU time 153.43 seconds
Started Feb 07 02:03:25 PM PST 24
Finished Feb 07 02:06:00 PM PST 24
Peak memory 364712 kb
Host smart-9a68a4ad-779b-47bd-9665-18ddf5ada9e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726021073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.1726021073
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.49100786
Short name T447
Test name
Test status
Simulation time 20237674818 ps
CPU time 61.71 seconds
Started Feb 07 02:03:26 PM PST 24
Finished Feb 07 02:04:29 PM PST 24
Peak memory 213864 kb
Host smart-4a78500c-f5b1-4cdf-aa5b-0ad711d5515f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49100786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_esca
lation.49100786
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.1228811790
Short name T919
Test name
Test status
Simulation time 1912378060 ps
CPU time 169.75 seconds
Started Feb 07 02:03:27 PM PST 24
Finished Feb 07 02:06:17 PM PST 24
Peak memory 368804 kb
Host smart-957312bb-e8e5-47d4-a6b2-bdea3491b7ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228811790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.1228811790
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.442691307
Short name T570
Test name
Test status
Simulation time 1024063550 ps
CPU time 74.2 seconds
Started Feb 07 02:03:36 PM PST 24
Finished Feb 07 02:04:51 PM PST 24
Peak memory 211312 kb
Host smart-c4e07f23-ffe7-4750-becc-08e843f104cb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442691307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.sram_ctrl_mem_partial_access.442691307
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.580927335
Short name T448
Test name
Test status
Simulation time 34358482704 ps
CPU time 333.54 seconds
Started Feb 07 02:03:38 PM PST 24
Finished Feb 07 02:09:13 PM PST 24
Peak memory 202300 kb
Host smart-cc89ad51-e6ce-4b18-a0d0-43e4a177788b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580927335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl
_mem_walk.580927335
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.365886371
Short name T246
Test name
Test status
Simulation time 14052104599 ps
CPU time 607.8 seconds
Started Feb 07 02:03:20 PM PST 24
Finished Feb 07 02:13:30 PM PST 24
Peak memory 367504 kb
Host smart-31a4ac27-661e-4192-8b75-ec382c2d5c36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365886371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip
le_keys.365886371
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.1004102482
Short name T14
Test name
Test status
Simulation time 756753084 ps
CPU time 57.51 seconds
Started Feb 07 02:03:27 PM PST 24
Finished Feb 07 02:04:25 PM PST 24
Peak memory 299248 kb
Host smart-ad339412-706c-4b98-941d-47383a2fc853
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004102482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.1004102482
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.369258697
Short name T350
Test name
Test status
Simulation time 7980226956 ps
CPU time 499.86 seconds
Started Feb 07 02:03:25 PM PST 24
Finished Feb 07 02:11:46 PM PST 24
Peak memory 202180 kb
Host smart-f7b05e48-916e-4a79-8ab8-37aff261091e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369258697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.sram_ctrl_partial_access_b2b.369258697
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.2222913689
Short name T40
Test name
Test status
Simulation time 684199061 ps
CPU time 6.64 seconds
Started Feb 07 02:03:39 PM PST 24
Finished Feb 07 02:03:46 PM PST 24
Peak memory 202312 kb
Host smart-0dee3dcd-a735-41b7-8b1b-a9b7c5ba3106
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222913689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2222913689
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.3981113589
Short name T2
Test name
Test status
Simulation time 1062697772 ps
CPU time 100.59 seconds
Started Feb 07 02:03:37 PM PST 24
Finished Feb 07 02:05:18 PM PST 24
Peak memory 299268 kb
Host smart-abca96f8-9866-4853-a68d-f68471da4dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981113589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3981113589
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.388604184
Short name T476
Test name
Test status
Simulation time 1677481067 ps
CPU time 33.59 seconds
Started Feb 07 02:03:19 PM PST 24
Finished Feb 07 02:03:55 PM PST 24
Peak memory 202248 kb
Host smart-670a3b68-3a92-484b-8070-13f90cd2ed0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388604184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.388604184
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3737624782
Short name T419
Test name
Test status
Simulation time 215280387 ps
CPU time 1494.64 seconds
Started Feb 07 02:03:39 PM PST 24
Finished Feb 07 02:28:35 PM PST 24
Peak memory 521432 kb
Host smart-e2f3cc36-112a-4a3c-b131-50ed42de870e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3737624782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3737624782
Directory /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2200981816
Short name T60
Test name
Test status
Simulation time 14425524012 ps
CPU time 296.42 seconds
Started Feb 07 02:03:25 PM PST 24
Finished Feb 07 02:08:23 PM PST 24
Peak memory 202200 kb
Host smart-fff7b820-ce40-4bd8-a74d-3e4dfcfee201
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200981816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.2200981816
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3865317192
Short name T468
Test name
Test status
Simulation time 3155212990 ps
CPU time 96.41 seconds
Started Feb 07 02:03:25 PM PST 24
Finished Feb 07 02:05:03 PM PST 24
Peak memory 320816 kb
Host smart-ffe07ab1-ec32-41a9-ac7c-827d685464b6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865317192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3865317192
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3128296253
Short name T607
Test name
Test status
Simulation time 31731818193 ps
CPU time 706.34 seconds
Started Feb 07 02:03:56 PM PST 24
Finished Feb 07 02:15:43 PM PST 24
Peak memory 378428 kb
Host smart-9567aeb5-81d8-44c2-90ae-7adc88b35554
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128296253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.3128296253
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.2120786075
Short name T505
Test name
Test status
Simulation time 88923498 ps
CPU time 0.66 seconds
Started Feb 07 02:03:54 PM PST 24
Finished Feb 07 02:03:56 PM PST 24
Peak memory 201476 kb
Host smart-b4cc6ab9-8d50-4d03-81fc-e6f71141e6d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120786075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.2120786075
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.2060332309
Short name T233
Test name
Test status
Simulation time 225198331825 ps
CPU time 1781.48 seconds
Started Feb 07 02:03:38 PM PST 24
Finished Feb 07 02:33:20 PM PST 24
Peak memory 202232 kb
Host smart-6f5079ac-3a26-4d18-bd1b-0d963f0e6aaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060332309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.2060332309
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.705827549
Short name T843
Test name
Test status
Simulation time 105292769694 ps
CPU time 1203.75 seconds
Started Feb 07 02:03:55 PM PST 24
Finished Feb 07 02:24:00 PM PST 24
Peak memory 372908 kb
Host smart-524da99a-333f-411a-939b-3869d6d3e17c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705827549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executabl
e.705827549
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.1763742518
Short name T634
Test name
Test status
Simulation time 43740938491 ps
CPU time 82.01 seconds
Started Feb 07 02:03:56 PM PST 24
Finished Feb 07 02:05:19 PM PST 24
Peak memory 202168 kb
Host smart-8a7e63a9-a280-468e-90a8-0aeb013f9102
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763742518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.1763742518
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.2544803069
Short name T576
Test name
Test status
Simulation time 1374733348 ps
CPU time 31.05 seconds
Started Feb 07 02:03:55 PM PST 24
Finished Feb 07 02:04:27 PM PST 24
Peak memory 234876 kb
Host smart-46cc8dd0-b7e3-4040-9871-efede1c641ff
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544803069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.2544803069
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.2564423436
Short name T88
Test name
Test status
Simulation time 2452009086 ps
CPU time 74.75 seconds
Started Feb 07 02:03:57 PM PST 24
Finished Feb 07 02:05:13 PM PST 24
Peak memory 211672 kb
Host smart-7bb0284c-a69e-4783-9542-2601213ddd18
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564423436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.2564423436
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.881964541
Short name T688
Test name
Test status
Simulation time 28113458499 ps
CPU time 266.4 seconds
Started Feb 07 02:03:56 PM PST 24
Finished Feb 07 02:08:23 PM PST 24
Peak memory 202168 kb
Host smart-f31d6c5c-786a-4569-a3c9-07367e39ffa0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881964541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_mem_walk.881964541
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.3229785613
Short name T876
Test name
Test status
Simulation time 78690025173 ps
CPU time 741.29 seconds
Started Feb 07 02:03:39 PM PST 24
Finished Feb 07 02:16:01 PM PST 24
Peak memory 374768 kb
Host smart-ba55aa63-e9fe-4b71-81ea-223d244ec1ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229785613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.3229785613
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.73851362
Short name T871
Test name
Test status
Simulation time 985166865 ps
CPU time 37.17 seconds
Started Feb 07 02:03:38 PM PST 24
Finished Feb 07 02:04:16 PM PST 24
Peak memory 202136 kb
Host smart-bb22804a-0dc6-4565-b4b8-d2ff8f85ec37
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73851362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sr
am_ctrl_partial_access.73851362
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.756376834
Short name T610
Test name
Test status
Simulation time 14003206888 ps
CPU time 466.47 seconds
Started Feb 07 02:03:38 PM PST 24
Finished Feb 07 02:11:26 PM PST 24
Peak memory 202248 kb
Host smart-d0ce307b-3ec8-4e14-aa2b-ec2c1e23347e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756376834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.sram_ctrl_partial_access_b2b.756376834
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.1614664019
Short name T440
Test name
Test status
Simulation time 363513538 ps
CPU time 13.38 seconds
Started Feb 07 02:03:50 PM PST 24
Finished Feb 07 02:04:04 PM PST 24
Peak memory 202412 kb
Host smart-1350aca4-858a-49b2-a710-8bf7ae228b96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614664019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1614664019
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.1840787847
Short name T864
Test name
Test status
Simulation time 2271124201 ps
CPU time 94.71 seconds
Started Feb 07 02:03:51 PM PST 24
Finished Feb 07 02:05:26 PM PST 24
Peak memory 282932 kb
Host smart-0163337f-c967-4d85-9826-ec090e5f4402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840787847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1840787847
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.3098955849
Short name T923
Test name
Test status
Simulation time 20957238670 ps
CPU time 24.18 seconds
Started Feb 07 02:03:39 PM PST 24
Finished Feb 07 02:04:04 PM PST 24
Peak memory 202136 kb
Host smart-1e59716b-0426-440e-bedb-23eb2eafa12d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098955849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3098955849
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3339399371
Short name T866
Test name
Test status
Simulation time 4214111755 ps
CPU time 5816.33 seconds
Started Feb 07 02:03:49 PM PST 24
Finished Feb 07 03:40:47 PM PST 24
Peak memory 491620 kb
Host smart-b9bbcd33-abad-4842-b11c-b8fe9a317914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3339399371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.3339399371
Directory /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.488994516
Short name T517
Test name
Test status
Simulation time 17516175223 ps
CPU time 333.53 seconds
Started Feb 07 02:03:37 PM PST 24
Finished Feb 07 02:09:11 PM PST 24
Peak memory 202244 kb
Host smart-57b87195-d316-42fe-8117-8f3a591869ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488994516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.sram_ctrl_stress_pipeline.488994516
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1995267805
Short name T425
Test name
Test status
Simulation time 1372046309 ps
CPU time 26.59 seconds
Started Feb 07 02:03:48 PM PST 24
Finished Feb 07 02:04:15 PM PST 24
Peak memory 210352 kb
Host smart-4f03026b-6da7-407d-98c1-6fb1a5fde867
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995267805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1995267805
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2906499637
Short name T564
Test name
Test status
Simulation time 11211007718 ps
CPU time 1573.93 seconds
Started Feb 07 02:04:03 PM PST 24
Finished Feb 07 02:30:18 PM PST 24
Peak memory 379128 kb
Host smart-7b3a425e-9b9e-4e64-9718-8acd7f623e6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906499637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.2906499637
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.79630341
Short name T430
Test name
Test status
Simulation time 17572180 ps
CPU time 0.65 seconds
Started Feb 07 02:04:04 PM PST 24
Finished Feb 07 02:04:05 PM PST 24
Peak memory 201860 kb
Host smart-489344ba-ab7a-4977-850c-428a81fa6ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79630341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_alert_test.79630341
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.128959883
Short name T535
Test name
Test status
Simulation time 30742420180 ps
CPU time 2012.61 seconds
Started Feb 07 02:03:55 PM PST 24
Finished Feb 07 02:37:29 PM PST 24
Peak memory 202172 kb
Host smart-da169517-f64d-42d9-99c0-c40e1ae3eb07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128959883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.
128959883
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.789322187
Short name T13
Test name
Test status
Simulation time 19126642479 ps
CPU time 1074.08 seconds
Started Feb 07 02:04:03 PM PST 24
Finished Feb 07 02:21:58 PM PST 24
Peak memory 378120 kb
Host smart-19c26d3a-b5d6-45cb-a300-56425b5f86c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789322187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executabl
e.789322187
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.3759017298
Short name T880
Test name
Test status
Simulation time 6346766006 ps
CPU time 43.47 seconds
Started Feb 07 02:04:03 PM PST 24
Finished Feb 07 02:04:47 PM PST 24
Peak memory 258820 kb
Host smart-630421c6-e719-431a-b09f-f5b498f7e1ae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759017298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.3759017298
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2912059922
Short name T598
Test name
Test status
Simulation time 2982616013 ps
CPU time 78.6 seconds
Started Feb 07 02:04:07 PM PST 24
Finished Feb 07 02:05:26 PM PST 24
Peak memory 211288 kb
Host smart-11d5b9b2-3e4b-49e6-9190-e1121cce6161
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912059922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.2912059922
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.1658311336
Short name T605
Test name
Test status
Simulation time 229647467923 ps
CPU time 355.32 seconds
Started Feb 07 02:04:05 PM PST 24
Finished Feb 07 02:10:01 PM PST 24
Peak memory 202436 kb
Host smart-9b4e6596-4777-4141-95b4-c5cefd18244a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658311336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.1658311336
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.3947007631
Short name T777
Test name
Test status
Simulation time 31267540156 ps
CPU time 2375.51 seconds
Started Feb 07 02:03:55 PM PST 24
Finished Feb 07 02:43:31 PM PST 24
Peak memory 380100 kb
Host smart-2fb3bc9e-78c1-4990-9786-db838b934375
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947007631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.3947007631
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.103730764
Short name T826
Test name
Test status
Simulation time 2988014372 ps
CPU time 34.85 seconds
Started Feb 07 02:03:49 PM PST 24
Finished Feb 07 02:04:25 PM PST 24
Peak memory 240852 kb
Host smart-9ca496b6-d5a4-4238-953a-0060ea9b0bff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103730764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.s
ram_ctrl_partial_access.103730764
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4114051573
Short name T779
Test name
Test status
Simulation time 39148256791 ps
CPU time 474.79 seconds
Started Feb 07 02:03:56 PM PST 24
Finished Feb 07 02:11:51 PM PST 24
Peak memory 202172 kb
Host smart-267febd0-dcac-4265-a87a-a9630a8b1161
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114051573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.sram_ctrl_partial_access_b2b.4114051573
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.3048044393
Short name T739
Test name
Test status
Simulation time 4783993809 ps
CPU time 5.73 seconds
Started Feb 07 02:04:05 PM PST 24
Finished Feb 07 02:04:11 PM PST 24
Peak memory 202456 kb
Host smart-f4509b34-f100-4ad4-9ea5-5775467a201e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048044393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3048044393
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.2010901100
Short name T427
Test name
Test status
Simulation time 4040521199 ps
CPU time 160.33 seconds
Started Feb 07 02:04:03 PM PST 24
Finished Feb 07 02:06:44 PM PST 24
Peak memory 351384 kb
Host smart-b34f76ff-5d90-4ee5-9b0b-0b19aff0666e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010901100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2010901100
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3342498911
Short name T519
Test name
Test status
Simulation time 1006484714 ps
CPU time 20.17 seconds
Started Feb 07 02:03:50 PM PST 24
Finished Feb 07 02:04:10 PM PST 24
Peak memory 202028 kb
Host smart-32040fea-c329-4650-9a7e-2cd79cb08050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342498911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3342498911
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1904869849
Short name T694
Test name
Test status
Simulation time 12490315818 ps
CPU time 3054.75 seconds
Started Feb 07 02:04:04 PM PST 24
Finished Feb 07 02:54:59 PM PST 24
Peak memory 465548 kb
Host smart-b1f358ff-db6e-4863-938c-2e2a3f3488c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1904869849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1904869849
Directory /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2981249881
Short name T501
Test name
Test status
Simulation time 27105447767 ps
CPU time 227.92 seconds
Started Feb 07 02:03:54 PM PST 24
Finished Feb 07 02:07:43 PM PST 24
Peak memory 202224 kb
Host smart-69a782cf-beb6-43a7-a85e-78324ccc6756
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981249881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_stress_pipeline.2981249881
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4021591692
Short name T138
Test name
Test status
Simulation time 1984312719 ps
CPU time 32.71 seconds
Started Feb 07 02:04:04 PM PST 24
Finished Feb 07 02:04:37 PM PST 24
Peak memory 238280 kb
Host smart-299a87ac-1cdc-4c39-b7f8-0f022c221c9b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021591692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.4021591692
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.2260381189
Short name T276
Test name
Test status
Simulation time 9382403380 ps
CPU time 96.57 seconds
Started Feb 07 02:00:55 PM PST 24
Finished Feb 07 02:02:33 PM PST 24
Peak memory 306892 kb
Host smart-8b3208c6-1d86-460c-8cab-9f5a78c61bd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260381189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.2260381189
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.1583655563
Short name T250
Test name
Test status
Simulation time 56235756 ps
CPU time 0.67 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:01:06 PM PST 24
Peak memory 201900 kb
Host smart-a30ba76f-3539-4fcc-a5ec-22896d905baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583655563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.1583655563
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.4132762323
Short name T342
Test name
Test status
Simulation time 45092613740 ps
CPU time 726.48 seconds
Started Feb 07 02:00:45 PM PST 24
Finished Feb 07 02:12:54 PM PST 24
Peak memory 202184 kb
Host smart-e73ef983-1047-4276-a7e8-5780d6ab2e45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132762323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
4132762323
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.4151194117
Short name T132
Test name
Test status
Simulation time 10848980280 ps
CPU time 51.82 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:01:57 PM PST 24
Peak memory 239032 kb
Host smart-54c9e371-ed63-4679-8b0d-038d9dc1ad89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151194117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.4151194117
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.4281503650
Short name T330
Test name
Test status
Simulation time 6643429736 ps
CPU time 146.91 seconds
Started Feb 07 02:00:55 PM PST 24
Finished Feb 07 02:03:24 PM PST 24
Peak memory 210436 kb
Host smart-a47901e0-1ac1-4fca-8d71-462190675751
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281503650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.4281503650
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.3181000383
Short name T955
Test name
Test status
Simulation time 732019033 ps
CPU time 61.41 seconds
Started Feb 07 02:00:56 PM PST 24
Finished Feb 07 02:01:58 PM PST 24
Peak memory 302288 kb
Host smart-58b73843-a693-4026-862f-125d35d5f1ac
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181000383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.3181000383
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.4288877963
Short name T492
Test name
Test status
Simulation time 19934076148 ps
CPU time 158.1 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:03:45 PM PST 24
Peak memory 214832 kb
Host smart-5fe087d5-6cb4-49fa-b4f5-827d760db6ce
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288877963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.4288877963
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.4211981118
Short name T747
Test name
Test status
Simulation time 18276968147 ps
CPU time 147.16 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:03:32 PM PST 24
Peak memory 202272 kb
Host smart-1d355492-fabe-4353-8625-3de272fc65a4
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211981118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.4211981118
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.3082910699
Short name T268
Test name
Test status
Simulation time 13273386473 ps
CPU time 786.17 seconds
Started Feb 07 02:00:41 PM PST 24
Finished Feb 07 02:13:49 PM PST 24
Peak memory 370920 kb
Host smart-e4a129eb-5671-405c-85e8-a2e341c84200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082910699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.3082910699
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.3793439245
Short name T558
Test name
Test status
Simulation time 3152253199 ps
CPU time 18.05 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:24 PM PST 24
Peak memory 240964 kb
Host smart-7af54fc4-7015-4a2e-930e-f35ac8fe4d6e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793439245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.3793439245
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.718099036
Short name T506
Test name
Test status
Simulation time 46868444480 ps
CPU time 458.07 seconds
Started Feb 07 02:00:54 PM PST 24
Finished Feb 07 02:08:35 PM PST 24
Peak memory 202176 kb
Host smart-b7392947-3c59-441b-8cbf-400c1042a896
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718099036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.sram_ctrl_partial_access_b2b.718099036
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.3410842919
Short name T582
Test name
Test status
Simulation time 1343639968 ps
CPU time 13.36 seconds
Started Feb 07 02:00:54 PM PST 24
Finished Feb 07 02:01:10 PM PST 24
Peak memory 202432 kb
Host smart-bbde7c42-5a78-4a21-9ec2-99af3947a99c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410842919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.3410842919
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1617277499
Short name T743
Test name
Test status
Simulation time 3200631256 ps
CPU time 136.48 seconds
Started Feb 07 02:00:56 PM PST 24
Finished Feb 07 02:03:14 PM PST 24
Peak memory 344288 kb
Host smart-64a52866-d06b-40eb-b7cf-1e269df08581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617277499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1617277499
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.2907043009
Short name T236
Test name
Test status
Simulation time 1631038565 ps
CPU time 72.99 seconds
Started Feb 07 02:00:41 PM PST 24
Finished Feb 07 02:01:56 PM PST 24
Peak memory 303352 kb
Host smart-bd116562-45dc-4a4f-844e-9b86d80091b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907043009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2907043009
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.1496863494
Short name T842
Test name
Test status
Simulation time 172416623332 ps
CPU time 1923.61 seconds
Started Feb 07 02:01:10 PM PST 24
Finished Feb 07 02:33:15 PM PST 24
Peak memory 378156 kb
Host smart-d4a912e2-872a-41b9-a0eb-ecd8603331ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496863494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.1496863494
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.718776184
Short name T229
Test name
Test status
Simulation time 4231135831 ps
CPU time 4295.75 seconds
Started Feb 07 02:00:53 PM PST 24
Finished Feb 07 03:12:32 PM PST 24
Peak memory 422780 kb
Host smart-5136ca3f-f10b-4713-928d-a41952c32283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=718776184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.718776184
Directory /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.4105191755
Short name T881
Test name
Test status
Simulation time 14301101714 ps
CPU time 276.7 seconds
Started Feb 07 02:01:01 PM PST 24
Finished Feb 07 02:05:40 PM PST 24
Peak memory 202188 kb
Host smart-c8eba501-b757-4eb2-b107-b11049edfe52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105191755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.4105191755
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3417495987
Short name T929
Test name
Test status
Simulation time 836410447 ps
CPU time 128.14 seconds
Started Feb 07 02:00:53 PM PST 24
Finished Feb 07 02:03:04 PM PST 24
Peak memory 370856 kb
Host smart-44e42006-8d30-49ce-bdf3-ef9dc85f06ef
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417495987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3417495987
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1855322956
Short name T579
Test name
Test status
Simulation time 7495857675 ps
CPU time 1031.35 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:25:12 PM PST 24
Peak memory 379324 kb
Host smart-bf38dfa9-86eb-4bac-85f0-52c15fba52ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855322956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.1855322956
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.1651743164
Short name T457
Test name
Test status
Simulation time 38897126 ps
CPU time 0.64 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:08:06 PM PST 24
Peak memory 201872 kb
Host smart-7f8a0bf3-4f1d-40fd-b620-67843de0cf2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651743164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.1651743164
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.1844626413
Short name T450
Test name
Test status
Simulation time 64610232999 ps
CPU time 1492.35 seconds
Started Feb 07 02:04:06 PM PST 24
Finished Feb 07 02:29:00 PM PST 24
Peak memory 202320 kb
Host smart-8de34e41-d26e-41e8-8f49-f8e310556c08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844626413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.1844626413
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.4116635949
Short name T423
Test name
Test status
Simulation time 20929275944 ps
CPU time 1144.59 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:27:05 PM PST 24
Peak memory 379820 kb
Host smart-6bb1c714-c0dd-4a18-b32a-cc4625514d62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116635949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.4116635949
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.401647202
Short name T680
Test name
Test status
Simulation time 60650980989 ps
CPU time 93.81 seconds
Started Feb 07 02:04:05 PM PST 24
Finished Feb 07 02:05:40 PM PST 24
Peak memory 210380 kb
Host smart-65bf0729-96ed-4c3a-8e14-bc837ea02f8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401647202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc
alation.401647202
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.2970566770
Short name T588
Test name
Test status
Simulation time 701687410 ps
CPU time 28.25 seconds
Started Feb 07 02:04:04 PM PST 24
Finished Feb 07 02:04:33 PM PST 24
Peak memory 210324 kb
Host smart-202fad48-5192-419d-a5d0-3ed5190732e0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970566770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.2970566770
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1208529451
Short name T90
Test name
Test status
Simulation time 23670771232 ps
CPU time 147.8 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:10:26 PM PST 24
Peak memory 211312 kb
Host smart-5cf9b7ef-58bb-4b3e-9322-08af12339eb5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208529451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.1208529451
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.3109705830
Short name T669
Test name
Test status
Simulation time 28663670916 ps
CPU time 291.56 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:12:50 PM PST 24
Peak memory 202264 kb
Host smart-adfaf566-b9a9-4b08-af12-01b7cf8ed238
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109705830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.3109705830
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.3191058858
Short name T481
Test name
Test status
Simulation time 2659511949 ps
CPU time 147.81 seconds
Started Feb 07 02:04:04 PM PST 24
Finished Feb 07 02:06:33 PM PST 24
Peak memory 308964 kb
Host smart-eaae7c41-986f-44b0-b073-8829aeb50851
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191058858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.3191058858
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.4248491243
Short name T144
Test name
Test status
Simulation time 1417668088 ps
CPU time 26.26 seconds
Started Feb 07 02:04:06 PM PST 24
Finished Feb 07 02:04:33 PM PST 24
Peak memory 202024 kb
Host smart-1faf1449-c03e-4df9-8191-7095074f3db5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248491243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.4248491243
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4243346293
Short name T922
Test name
Test status
Simulation time 12641127605 ps
CPU time 324.01 seconds
Started Feb 07 02:04:04 PM PST 24
Finished Feb 07 02:09:29 PM PST 24
Peak memory 202164 kb
Host smart-30ab5418-65d9-4107-b03d-00d52bff0f90
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243346293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.4243346293
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.2885728207
Short name T904
Test name
Test status
Simulation time 347018362 ps
CPU time 5.69 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:08:03 PM PST 24
Peak memory 202372 kb
Host smart-f2070ef2-854a-4525-af50-0955c4d4f7c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885728207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2885728207
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.332570312
Short name T734
Test name
Test status
Simulation time 51256672673 ps
CPU time 1149.87 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:27:11 PM PST 24
Peak memory 376996 kb
Host smart-0c19ef1c-b2f1-467f-8e4d-b73dfb7c34f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332570312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.332570312
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.1813456596
Short name T559
Test name
Test status
Simulation time 9704601837 ps
CPU time 36.21 seconds
Started Feb 07 02:04:05 PM PST 24
Finished Feb 07 02:04:42 PM PST 24
Peak memory 202176 kb
Host smart-218af341-7723-47a3-8ad8-c28f978aa3ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813456596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1813456596
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4204319614
Short name T532
Test name
Test status
Simulation time 1968067234 ps
CPU time 6240.36 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 03:52:02 PM PST 24
Peak memory 466600 kb
Host smart-5a4e36c5-67f6-4a82-8026-380740cc916b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4204319614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.4204319614
Directory /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1777595922
Short name T271
Test name
Test status
Simulation time 3702173661 ps
CPU time 275.2 seconds
Started Feb 07 02:04:05 PM PST 24
Finished Feb 07 02:08:41 PM PST 24
Peak memory 210436 kb
Host smart-e94cb7d4-b834-4ea7-bea4-151c87dab02c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777595922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.1777595922
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1866081260
Short name T859
Test name
Test status
Simulation time 691800197 ps
CPU time 28.51 seconds
Started Feb 07 02:04:06 PM PST 24
Finished Feb 07 02:04:35 PM PST 24
Peak memory 220040 kb
Host smart-415ac0d3-9a23-4743-bf24-04c91a4a6175
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866081260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1866081260
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2644171208
Short name T365
Test name
Test status
Simulation time 29187580618 ps
CPU time 1410.2 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:31:34 PM PST 24
Peak memory 379088 kb
Host smart-b20fb466-2460-4978-8bf0-e2bba848784b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644171208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.2644171208
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.3024348784
Short name T628
Test name
Test status
Simulation time 42338144 ps
CPU time 0.63 seconds
Started Feb 07 02:07:58 PM PST 24
Finished Feb 07 02:07:59 PM PST 24
Peak memory 201844 kb
Host smart-9fbdf0f8-fcc5-4212-9efc-e883b056261e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024348784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.3024348784
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2061416786
Short name T670
Test name
Test status
Simulation time 364864160890 ps
CPU time 1975.94 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:40:59 PM PST 24
Peak memory 202244 kb
Host smart-4edc1784-da9e-4a48-8332-b08618664222
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061416786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2061416786
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.1869554305
Short name T606
Test name
Test status
Simulation time 58300307139 ps
CPU time 1004.51 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:24:49 PM PST 24
Peak memory 370956 kb
Host smart-56bee2d2-cbac-430d-bbce-11c056187a04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869554305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.1869554305
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2978236431
Short name T946
Test name
Test status
Simulation time 32697836307 ps
CPU time 178.39 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:10:57 PM PST 24
Peak memory 210368 kb
Host smart-71babbb8-342f-44f2-99db-b4317090a1e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978236431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2978236431
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.4212801782
Short name T852
Test name
Test status
Simulation time 3360907300 ps
CPU time 26.68 seconds
Started Feb 07 02:08:04 PM PST 24
Finished Feb 07 02:08:32 PM PST 24
Peak memory 211416 kb
Host smart-7340db59-b700-470e-892d-5d9db7577f02
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212801782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.4212801782
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.3473220347
Short name T746
Test name
Test status
Simulation time 21269551047 ps
CPU time 84.8 seconds
Started Feb 07 02:07:58 PM PST 24
Finished Feb 07 02:09:24 PM PST 24
Peak memory 218516 kb
Host smart-94933eb5-39d3-405a-a985-e3f23e039310
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473220347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.3473220347
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.3858994552
Short name T284
Test name
Test status
Simulation time 74602764732 ps
CPU time 300.53 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:13:02 PM PST 24
Peak memory 202204 kb
Host smart-4d7c8e9d-071a-4708-ab25-c3112ee4f73b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858994552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.3858994552
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.1139876041
Short name T657
Test name
Test status
Simulation time 1550810225 ps
CPU time 143.64 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:10:28 PM PST 24
Peak memory 361872 kb
Host smart-d71a32bb-b976-4d26-88ed-f80234c506fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139876041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.1139876041
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.3618728065
Short name T378
Test name
Test status
Simulation time 1789684587 ps
CPU time 8.08 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:08:13 PM PST 24
Peak memory 202056 kb
Host smart-32a4ffbb-001c-472b-a02b-f5aef59c930e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618728065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.3618728065
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3046630822
Short name T675
Test name
Test status
Simulation time 9852010674 ps
CPU time 220.87 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:11:42 PM PST 24
Peak memory 202168 kb
Host smart-7b76c453-c4b9-447c-9f2a-78d075c0eda4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046630822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.3046630822
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.1898521533
Short name T851
Test name
Test status
Simulation time 1532508738 ps
CPU time 6.26 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:06 PM PST 24
Peak memory 202348 kb
Host smart-e1b55afb-ec87-4955-9c5c-df5fbad7cfeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898521533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1898521533
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2729927426
Short name T24
Test name
Test status
Simulation time 39567273580 ps
CPU time 594.43 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:17:55 PM PST 24
Peak memory 372160 kb
Host smart-d8c4b544-835b-4038-8027-be2508e141be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729927426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2729927426
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.717497926
Short name T441
Test name
Test status
Simulation time 6410442773 ps
CPU time 12.47 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:08:15 PM PST 24
Peak memory 202144 kb
Host smart-3d03b379-8c75-4420-bbce-77d8143675e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717497926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.717497926
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3352615753
Short name T306
Test name
Test status
Simulation time 2315568047 ps
CPU time 3132.48 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 03:00:13 PM PST 24
Peak memory 519288 kb
Host smart-7c5d2bcf-7368-470d-bd9e-aa946dc78247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3352615753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3352615753
Directory /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2819523386
Short name T307
Test name
Test status
Simulation time 2257168208 ps
CPU time 151.31 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:10:36 PM PST 24
Peak memory 202244 kb
Host smart-ce05a0db-4af1-49ec-b01b-63ca03193461
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819523386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2819523386
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3156739393
Short name T914
Test name
Test status
Simulation time 3718454901 ps
CPU time 164.27 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:10:45 PM PST 24
Peak memory 364852 kb
Host smart-1f60eea8-257e-4aad-9fcb-dd9ce6832fc8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156739393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.3156739393
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2684887865
Short name T513
Test name
Test status
Simulation time 8162241153 ps
CPU time 1266.73 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:29:04 PM PST 24
Peak memory 377028 kb
Host smart-4f5af8c2-9c98-42d7-9770-df5444dc9aa1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684887865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.2684887865
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.4005276350
Short name T716
Test name
Test status
Simulation time 16159064 ps
CPU time 0.66 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:07:59 PM PST 24
Peak memory 201840 kb
Host smart-f621ccb4-a9bc-448e-b271-4f10b59c599c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005276350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.4005276350
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.552221455
Short name T873
Test name
Test status
Simulation time 488961243928 ps
CPU time 1957.07 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:40:38 PM PST 24
Peak memory 202232 kb
Host smart-f3b10e67-1848-4968-ab7c-0a762dbc0d6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552221455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.
552221455
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.3748065564
Short name T789
Test name
Test status
Simulation time 19065150066 ps
CPU time 261.63 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:12:20 PM PST 24
Peak memory 376424 kb
Host smart-534008cd-92a4-4b9b-9957-a9bb1fcbbdbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748065564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.3748065564
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.3613267822
Short name T297
Test name
Test status
Simulation time 3208233946 ps
CPU time 26.55 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:08:25 PM PST 24
Peak memory 202180 kb
Host smart-2cc7026b-2a6f-4174-aa05-adadc3a047a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613267822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.3613267822
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.3169807367
Short name T612
Test name
Test status
Simulation time 706256814 ps
CPU time 37.81 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:39 PM PST 24
Peak memory 254976 kb
Host smart-e9970fa3-ab5f-405c-9862-008f40a81d36
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169807367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.3169807367
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.754205326
Short name T951
Test name
Test status
Simulation time 27261193188 ps
CPU time 164.35 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:10:42 PM PST 24
Peak memory 211320 kb
Host smart-85f7a3a1-de60-4634-8265-5bad24831e8c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754205326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_mem_partial_access.754205326
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.2061592586
Short name T543
Test name
Test status
Simulation time 8581288400 ps
CPU time 125.1 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:10:03 PM PST 24
Peak memory 202216 kb
Host smart-8d8c69e5-ab6e-4a4a-822c-9e1ee4cc6886
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061592586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr
l_mem_walk.2061592586
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.2340956290
Short name T217
Test name
Test status
Simulation time 7561367555 ps
CPU time 46.54 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:48 PM PST 24
Peak memory 233948 kb
Host smart-8bdc1688-90a4-4e64-ae24-a0a6a820a649
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340956290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.2340956290
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.346369658
Short name T685
Test name
Test status
Simulation time 727260424 ps
CPU time 14.64 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:08:20 PM PST 24
Peak memory 202064 kb
Host smart-c783632f-87f6-49ef-b7c4-95f80f137022
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346369658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.s
ram_ctrl_partial_access.346369658
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2837864894
Short name T223
Test name
Test status
Simulation time 10545398232 ps
CPU time 260.09 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:12:20 PM PST 24
Peak memory 202100 kb
Host smart-c33f401e-a65b-4b03-9c04-10874b1ccd1e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837864894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.2837864894
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.4122934431
Short name T958
Test name
Test status
Simulation time 357051063 ps
CPU time 13.26 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:13 PM PST 24
Peak memory 202396 kb
Host smart-0dfdd7e7-9c2a-4297-8fe5-c73049a6f530
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122934431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.4122934431
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.688763833
Short name T135
Test name
Test status
Simulation time 704253083 ps
CPU time 320.44 seconds
Started Feb 07 02:08:05 PM PST 24
Finished Feb 07 02:13:27 PM PST 24
Peak memory 373544 kb
Host smart-1a4afb26-726c-4e4c-8b29-8bcc8d7d6601
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688763833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.688763833
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.1488782288
Short name T788
Test name
Test status
Simulation time 4863315011 ps
CPU time 22.62 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:23 PM PST 24
Peak memory 202056 kb
Host smart-b00534b0-ed77-4349-8606-175697b4a800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488782288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1488782288
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.204171074
Short name T409
Test name
Test status
Simulation time 103409166369 ps
CPU time 6102.52 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 03:49:44 PM PST 24
Peak memory 382108 kb
Host smart-cff9de97-496d-42f4-a9f7-e8b88672d337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204171074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_stress_all.204171074
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3480211228
Short name T645
Test name
Test status
Simulation time 538825213 ps
CPU time 4814.46 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 03:28:16 PM PST 24
Peak memory 718236 kb
Host smart-f1f84e09-5593-4a03-bca1-a49f93c25ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3480211228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3480211228
Directory /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1779738624
Short name T386
Test name
Test status
Simulation time 2879620770 ps
CPU time 197.45 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:11:22 PM PST 24
Peak memory 202076 kb
Host smart-f7ed213f-bb84-4cfd-ba42-ae3910be8e8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779738624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.1779738624
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3277586834
Short name T584
Test name
Test status
Simulation time 2957086694 ps
CPU time 41.44 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:08:40 PM PST 24
Peak memory 267576 kb
Host smart-3ca673a3-79cf-4381-b252-7cdd6f049a0d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277586834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3277586834
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3192715295
Short name T398
Test name
Test status
Simulation time 41651123394 ps
CPU time 1466.77 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:32:30 PM PST 24
Peak memory 372976 kb
Host smart-687cdded-98b4-4748-a816-8672f759a883
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192715295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.3192715295
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.1628920595
Short name T549
Test name
Test status
Simulation time 16240796 ps
CPU time 0.64 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:08:06 PM PST 24
Peak memory 201392 kb
Host smart-9259b04c-56a4-4d16-a15c-d073adc1f4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628920595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.1628920595
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.1149975795
Short name T239
Test name
Test status
Simulation time 119855425091 ps
CPU time 2776.39 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:54:22 PM PST 24
Peak memory 202204 kb
Host smart-a42b88fd-94e3-4b68-8168-bb4282afbe9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149975795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.1149975795
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.3094137404
Short name T813
Test name
Test status
Simulation time 12622171236 ps
CPU time 325.96 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:13:32 PM PST 24
Peak memory 367820 kb
Host smart-af37ef55-c681-4eaa-a9e3-d15a50828f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094137404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.3094137404
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.1601519853
Short name T396
Test name
Test status
Simulation time 28147099468 ps
CPU time 62.21 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:09:02 PM PST 24
Peak memory 202180 kb
Host smart-859aed73-cd79-437f-a621-50fad2d17c68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601519853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es
calation.1601519853
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.598792926
Short name T797
Test name
Test status
Simulation time 798499239 ps
CPU time 118.81 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:10:02 PM PST 24
Peak memory 365692 kb
Host smart-2150250d-d9e6-4229-aa41-ba94b8cc3dfa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598792926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.sram_ctrl_max_throughput.598792926
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.1330002451
Short name T889
Test name
Test status
Simulation time 3773962507 ps
CPU time 72.23 seconds
Started Feb 07 02:08:04 PM PST 24
Finished Feb 07 02:09:18 PM PST 24
Peak memory 211236 kb
Host smart-a1a342f9-5157-45ef-ab17-bc113bd7642d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330002451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.1330002451
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.1155120538
Short name T291
Test name
Test status
Simulation time 44891641487 ps
CPU time 166.27 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:10:51 PM PST 24
Peak memory 202540 kb
Host smart-f466f2f3-3d31-4d1c-a501-738208209090
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155120538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.1155120538
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.3401888109
Short name T134
Test name
Test status
Simulation time 35727795419 ps
CPU time 1777.56 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:37:39 PM PST 24
Peak memory 374976 kb
Host smart-77cef673-12b5-4672-a9c6-9c084dd1eca3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401888109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.3401888109
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.1939198308
Short name T699
Test name
Test status
Simulation time 3845376263 ps
CPU time 112.94 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:09:51 PM PST 24
Peak memory 372880 kb
Host smart-0f2e91fa-f059-49be-a252-31932cf21888
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939198308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.1939198308
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.3740971375
Short name T489
Test name
Test status
Simulation time 676882541 ps
CPU time 13.46 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:08:18 PM PST 24
Peak memory 202432 kb
Host smart-f8b1fa8b-ebe8-4114-a792-070aa854f942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740971375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3740971375
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.1313833574
Short name T868
Test name
Test status
Simulation time 12810851554 ps
CPU time 511.67 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:16:36 PM PST 24
Peak memory 370820 kb
Host smart-791de157-0d55-4cd8-9cdb-ddd4d48a8078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313833574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1313833574
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.1903494060
Short name T530
Test name
Test status
Simulation time 916817973 ps
CPU time 161.53 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:10:40 PM PST 24
Peak memory 366800 kb
Host smart-d7f69f4e-998d-4998-804b-c0a07e695f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903494060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1903494060
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.626676356
Short name T431
Test name
Test status
Simulation time 1252575007315 ps
CPU time 6928.01 seconds
Started Feb 07 02:07:58 PM PST 24
Finished Feb 07 04:03:28 PM PST 24
Peak memory 388284 kb
Host smart-b1613cbf-bdee-4e68-b78a-32edcc4550ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626676356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_stress_all.626676356
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.852120122
Short name T334
Test name
Test status
Simulation time 571202792 ps
CPU time 6553.08 seconds
Started Feb 07 02:08:00 PM PST 24
Finished Feb 07 03:57:16 PM PST 24
Peak memory 698308 kb
Host smart-1f3e0f30-8cb6-4fcc-a24a-0e4b4b152e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=852120122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.852120122
Directory /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3379888966
Short name T883
Test name
Test status
Simulation time 23637519949 ps
CPU time 421.15 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:15:03 PM PST 24
Peak memory 202168 kb
Host smart-71d34290-c609-4830-b421-5469e616cb43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379888966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.3379888966
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.64407676
Short name T269
Test name
Test status
Simulation time 682266312 ps
CPU time 30.02 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:08:36 PM PST 24
Peak memory 224716 kb
Host smart-ffea457d-40a6-47b3-b6e5-242ded5a7ac3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64407676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.sram_ctrl_throughput_w_partial_write.64407676
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2217935580
Short name T18
Test name
Test status
Simulation time 10006265505 ps
CPU time 472.28 seconds
Started Feb 07 02:07:58 PM PST 24
Finished Feb 07 02:15:51 PM PST 24
Peak memory 373028 kb
Host smart-4d05b102-f1a5-4610-ac0f-523ea128c93c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217935580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2217935580
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.659931339
Short name T589
Test name
Test status
Simulation time 25364437 ps
CPU time 0.67 seconds
Started Feb 07 02:08:05 PM PST 24
Finished Feb 07 02:08:08 PM PST 24
Peak memory 201844 kb
Host smart-708d1987-2cfe-4ba3-a10c-9d26f6eb93ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659931339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.659931339
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1619616659
Short name T238
Test name
Test status
Simulation time 23268972045 ps
CPU time 520.41 seconds
Started Feb 07 02:08:04 PM PST 24
Finished Feb 07 02:16:46 PM PST 24
Peak memory 202212 kb
Host smart-4fca2074-b724-4048-8056-031ec2d7d16d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619616659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1619616659
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.2926320669
Short name T745
Test name
Test status
Simulation time 7210362979 ps
CPU time 119.94 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:10:01 PM PST 24
Peak memory 342064 kb
Host smart-ff5f64c1-59f6-435e-b049-07190a4eff3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926320669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.2926320669
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.35281937
Short name T222
Test name
Test status
Simulation time 791272693 ps
CPU time 135.66 seconds
Started Feb 07 02:07:58 PM PST 24
Finished Feb 07 02:10:15 PM PST 24
Peak memory 340136 kb
Host smart-14c70209-6a03-4bbd-88f9-0022c45c1e93
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.sram_ctrl_max_throughput.35281937
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1603638590
Short name T413
Test name
Test status
Simulation time 5321445966 ps
CPU time 83.56 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:09:21 PM PST 24
Peak memory 211264 kb
Host smart-f8af928e-2220-4117-9053-7556f55d0dd2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603638590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_mem_partial_access.1603638590
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.460375098
Short name T415
Test name
Test status
Simulation time 54248250975 ps
CPU time 156.58 seconds
Started Feb 07 02:08:00 PM PST 24
Finished Feb 07 02:10:38 PM PST 24
Peak memory 202408 kb
Host smart-ae61fcdd-3c43-46ef-b578-c7894ad07696
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460375098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl
_mem_walk.460375098
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.2894899899
Short name T591
Test name
Test status
Simulation time 9544122880 ps
CPU time 132.41 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:10:10 PM PST 24
Peak memory 290532 kb
Host smart-e1cbd603-7955-4ab1-b3af-714924988a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894899899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.2894899899
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.3954756120
Short name T146
Test name
Test status
Simulation time 3021057794 ps
CPU time 15.57 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:16 PM PST 24
Peak memory 202212 kb
Host smart-650523be-3fcd-467a-9d54-7ff55d8634c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954756120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.3954756120
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.669602009
Short name T861
Test name
Test status
Simulation time 8326189975 ps
CPU time 388.37 seconds
Started Feb 07 02:08:00 PM PST 24
Finished Feb 07 02:14:31 PM PST 24
Peak memory 202236 kb
Host smart-b67685a0-67cb-41e0-a037-7ec5ceec2673
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669602009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.sram_ctrl_partial_access_b2b.669602009
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3489619951
Short name T302
Test name
Test status
Simulation time 660176661 ps
CPU time 6.36 seconds
Started Feb 07 02:08:05 PM PST 24
Finished Feb 07 02:08:13 PM PST 24
Peak memory 202364 kb
Host smart-7969bae7-e217-4e27-b271-8d287764dc10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489619951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3489619951
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.3646849110
Short name T298
Test name
Test status
Simulation time 82437145715 ps
CPU time 1050.54 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:25:36 PM PST 24
Peak memory 374788 kb
Host smart-189e77a2-b35a-4d20-a098-ac66d5ca5b52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646849110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3646849110
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.2724799479
Short name T961
Test name
Test status
Simulation time 859068753 ps
CPU time 87.56 seconds
Started Feb 07 02:08:00 PM PST 24
Finished Feb 07 02:09:29 PM PST 24
Peak memory 326940 kb
Host smart-8b86d2e9-19d1-413f-937b-403bac6aa20c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724799479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2724799479
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.88806109
Short name T663
Test name
Test status
Simulation time 1121664098 ps
CPU time 2090.25 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:42:51 PM PST 24
Peak memory 630768 kb
Host smart-0eec2fe0-b5ff-402c-a323-1556dd09f513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=88806109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.88806109
Directory /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2212833167
Short name T900
Test name
Test status
Simulation time 3745771836 ps
CPU time 277.18 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:12:35 PM PST 24
Peak memory 202264 kb
Host smart-806c971a-6947-47a4-ae46-3a0cd594e8bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212833167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.2212833167
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3167435516
Short name T15
Test name
Test status
Simulation time 906469886 ps
CPU time 34.22 seconds
Started Feb 07 02:07:58 PM PST 24
Finished Feb 07 02:08:33 PM PST 24
Peak memory 238692 kb
Host smart-0c464fcc-dc6a-40bf-9a3d-bb89c19e42ed
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167435516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.3167435516
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2283707812
Short name T844
Test name
Test status
Simulation time 765822743 ps
CPU time 63.43 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:09:08 PM PST 24
Peak memory 290268 kb
Host smart-12356386-d9ad-4914-ae47-52c979356b2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283707812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.2283707812
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.4272621454
Short name T347
Test name
Test status
Simulation time 131736124 ps
CPU time 0.7 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:02 PM PST 24
Peak memory 201824 kb
Host smart-6b02cba9-7ecc-455a-be27-d3d5e024a4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272621454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.4272621454
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.2934142404
Short name T806
Test name
Test status
Simulation time 10845001671 ps
CPU time 752.06 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:20:35 PM PST 24
Peak memory 202384 kb
Host smart-17bd764b-56d5-4fd5-861e-70f94fbb5cef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934142404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.2934142404
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.3860144928
Short name T387
Test name
Test status
Simulation time 24456422494 ps
CPU time 155.4 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:10:38 PM PST 24
Peak memory 369740 kb
Host smart-7dcb7730-f694-4871-9977-360fbf9a5a39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860144928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.3860144928
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.2409832317
Short name T774
Test name
Test status
Simulation time 23779910159 ps
CPU time 204.14 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:11:28 PM PST 24
Peak memory 210448 kb
Host smart-aef256e9-223d-4024-93ee-78bcac8e0447
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409832317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.2409832317
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.1901884032
Short name T911
Test name
Test status
Simulation time 1997981787 ps
CPU time 57.05 seconds
Started Feb 07 02:08:04 PM PST 24
Finished Feb 07 02:09:03 PM PST 24
Peak memory 288004 kb
Host smart-2cf1235d-f029-4732-9a6e-2332051b7dd2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901884032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.1901884032
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.637347031
Short name T371
Test name
Test status
Simulation time 22854594080 ps
CPU time 146.92 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:10:30 PM PST 24
Peak memory 211304 kb
Host smart-a1dc1bcb-2afc-40b2-9683-3ded2e970f57
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637347031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.637347031
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.3546878593
Short name T240
Test name
Test status
Simulation time 8045980845 ps
CPU time 240.92 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:12:04 PM PST 24
Peak memory 202232 kb
Host smart-2c68bf99-2e9d-4cf5-976e-3ac33b28b99e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546878593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.3546878593
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.312820189
Short name T485
Test name
Test status
Simulation time 15565462267 ps
CPU time 660.07 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:19:05 PM PST 24
Peak memory 374776 kb
Host smart-35abbfcc-bb57-4aac-97cb-c984d02a83e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312820189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip
le_keys.312820189
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.4094935944
Short name T417
Test name
Test status
Simulation time 1424880688 ps
CPU time 24.15 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:08:27 PM PST 24
Peak memory 202032 kb
Host smart-112ad400-7e90-48e2-abf4-6726d019e711
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094935944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.4094935944
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.958243919
Short name T563
Test name
Test status
Simulation time 36679890642 ps
CPU time 557.72 seconds
Started Feb 07 02:08:00 PM PST 24
Finished Feb 07 02:17:20 PM PST 24
Peak memory 210360 kb
Host smart-ae4fd783-ca3e-49b0-b60a-3d827e82461c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958243919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.sram_ctrl_partial_access_b2b.958243919
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2743123871
Short name T39
Test name
Test status
Simulation time 708740309 ps
CPU time 5.52 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:08:10 PM PST 24
Peak memory 202308 kb
Host smart-7378a3b9-9b32-4151-bb91-4f649d3690cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743123871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2743123871
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.2716633657
Short name T696
Test name
Test status
Simulation time 15972137629 ps
CPU time 753.86 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:20:37 PM PST 24
Peak memory 375740 kb
Host smart-00658fc3-e6f6-49db-9d15-769978aa89a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716633657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2716633657
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.1540018921
Short name T857
Test name
Test status
Simulation time 7567294506 ps
CPU time 29.13 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:08:34 PM PST 24
Peak memory 202100 kb
Host smart-9491a304-7052-4c10-8012-aadf63dfa394
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540018921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1540018921
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.4117788891
Short name T32
Test name
Test status
Simulation time 572558312475 ps
CPU time 3577.11 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 03:07:35 PM PST 24
Peak memory 374660 kb
Host smart-c2552812-7334-4bd7-a18b-c540b0b5083b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117788891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.4117788891
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3436840983
Short name T491
Test name
Test status
Simulation time 7051715379 ps
CPU time 5982.79 seconds
Started Feb 07 02:08:00 PM PST 24
Finished Feb 07 03:47:45 PM PST 24
Peak memory 451380 kb
Host smart-f9092c4a-41a8-4977-8fe6-8f87188e8e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3436840983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3436840983
Directory /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2590262473
Short name T357
Test name
Test status
Simulation time 6840314877 ps
CPU time 225.44 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:11:50 PM PST 24
Peak memory 202196 kb
Host smart-5a93d2ab-78df-4c04-8494-8ff88d2d3386
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590262473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.2590262473
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1079521504
Short name T560
Test name
Test status
Simulation time 2887133245 ps
CPU time 32.53 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:08:37 PM PST 24
Peak memory 236992 kb
Host smart-91e4f2b5-ae40-4d33-ab80-9b65f2030dfc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079521504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1079521504
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.897744186
Short name T712
Test name
Test status
Simulation time 8358935311 ps
CPU time 1495.65 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:32:53 PM PST 24
Peak memory 376008 kb
Host smart-cc093ffb-c904-4c1e-acb5-4c4b702098b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897744186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.sram_ctrl_access_during_key_req.897744186
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.3879820760
Short name T449
Test name
Test status
Simulation time 34880365 ps
CPU time 0.63 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:08:14 PM PST 24
Peak memory 201896 kb
Host smart-6e0fb97b-3b6f-4efd-bb8c-9388c955817d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879820760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.3879820760
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.3701123916
Short name T459
Test name
Test status
Simulation time 198241802274 ps
CPU time 685.47 seconds
Started Feb 07 02:08:03 PM PST 24
Finished Feb 07 02:19:31 PM PST 24
Peak memory 202208 kb
Host smart-c799b535-a54a-4f16-ad42-7b49c6e4c134
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701123916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.3701123916
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.2366530523
Short name T627
Test name
Test status
Simulation time 49008866247 ps
CPU time 687.25 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:19:25 PM PST 24
Peak memory 377012 kb
Host smart-5bf67080-8ba2-498c-9b35-d6de6af27798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366530523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.2366530523
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.3899563353
Short name T817
Test name
Test status
Simulation time 53584116633 ps
CPU time 143.29 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:10:23 PM PST 24
Peak memory 210368 kb
Host smart-fb7b6bff-9a4a-430b-a693-cb715433d775
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899563353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.3899563353
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.642537166
Short name T140
Test name
Test status
Simulation time 2951005360 ps
CPU time 89.13 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:09:32 PM PST 24
Peak memory 328032 kb
Host smart-5f48e64e-6dd1-4828-8103-17ca55739624
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642537166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.sram_ctrl_max_throughput.642537166
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2598482909
Short name T85
Test name
Test status
Simulation time 19753802974 ps
CPU time 152.55 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:10:47 PM PST 24
Peak memory 211268 kb
Host smart-1534c355-e62b-4658-87a4-574479faf3fc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598482909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_mem_partial_access.2598482909
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.3711633386
Short name T384
Test name
Test status
Simulation time 15767832278 ps
CPU time 242.43 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:12:07 PM PST 24
Peak memory 202248 kb
Host smart-953bb249-d48f-46d4-a83f-a57275c61690
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711633386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr
l_mem_walk.3711633386
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.438823737
Short name T461
Test name
Test status
Simulation time 102991593430 ps
CPU time 1625.98 seconds
Started Feb 07 02:08:00 PM PST 24
Finished Feb 07 02:35:08 PM PST 24
Peak memory 377032 kb
Host smart-bed2a378-23cd-4557-b1c3-551cadbacecc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438823737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multip
le_keys.438823737
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.3597674748
Short name T658
Test name
Test status
Simulation time 1337073060 ps
CPU time 136.94 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:10:15 PM PST 24
Peak memory 370820 kb
Host smart-f9d616eb-4cdd-4108-99de-5ae9519e6894
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597674748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.3597674748
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.771225281
Short name T659
Test name
Test status
Simulation time 14900862015 ps
CPU time 302.62 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:13:05 PM PST 24
Peak memory 202116 kb
Host smart-77fd7192-2a4a-4c75-bc32-dbbb8097d410
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771225281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.sram_ctrl_partial_access_b2b.771225281
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.681000031
Short name T695
Test name
Test status
Simulation time 349640002 ps
CPU time 5.35 seconds
Started Feb 07 02:07:59 PM PST 24
Finished Feb 07 02:08:05 PM PST 24
Peak memory 202348 kb
Host smart-98a3b442-b592-46e6-afe0-7d34e63d9608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681000031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.681000031
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.2594350047
Short name T145
Test name
Test status
Simulation time 9724122923 ps
CPU time 103.46 seconds
Started Feb 07 02:07:57 PM PST 24
Finished Feb 07 02:09:41 PM PST 24
Peak memory 339116 kb
Host smart-32fba308-dce3-4354-98b2-0ec78f5733e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594350047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2594350047
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3550406201
Short name T59
Test name
Test status
Simulation time 62977969467 ps
CPU time 327.67 seconds
Started Feb 07 02:08:02 PM PST 24
Finished Feb 07 02:13:33 PM PST 24
Peak memory 202100 kb
Host smart-b32ab723-2747-4db6-9535-5ecce91591c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550406201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.3550406201
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2649665628
Short name T724
Test name
Test status
Simulation time 3434190973 ps
CPU time 100.31 seconds
Started Feb 07 02:08:01 PM PST 24
Finished Feb 07 02:09:44 PM PST 24
Peak memory 325076 kb
Host smart-cf3ebc76-a82b-4cf0-a7a3-f62471e62b12
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649665628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2649665628
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.306694930
Short name T703
Test name
Test status
Simulation time 53724257665 ps
CPU time 1938.13 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:40:31 PM PST 24
Peak memory 374992 kb
Host smart-6e22728f-d010-4c26-b6fc-e48d3dbba1e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306694930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.306694930
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.2397076534
Short name T314
Test name
Test status
Simulation time 16519927 ps
CPU time 0.66 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:08:14 PM PST 24
Peak memory 201872 kb
Host smart-2027e966-c790-4d19-9964-f1d585cba875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397076534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.2397076534
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.4025008569
Short name T451
Test name
Test status
Simulation time 111584598225 ps
CPU time 2453.07 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:49:06 PM PST 24
Peak memory 202188 kb
Host smart-7a5e56ab-46f4-4044-8d8f-86c15a8beafb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025008569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.4025008569
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.1074919414
Short name T394
Test name
Test status
Simulation time 20418493386 ps
CPU time 1313.63 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:30:07 PM PST 24
Peak memory 371980 kb
Host smart-4802525d-2f8f-4ad1-9f8c-b48a185626ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074919414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.1074919414
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.2184667258
Short name T241
Test name
Test status
Simulation time 5215898998 ps
CPU time 27.73 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:08:43 PM PST 24
Peak memory 210356 kb
Host smart-9160e75d-0d92-45f4-a28c-e4372ecebc93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184667258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es
calation.2184667258
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.4229854122
Short name T884
Test name
Test status
Simulation time 1593503879 ps
CPU time 166.99 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:10:59 PM PST 24
Peak memory 367720 kb
Host smart-b634b83b-5f79-48f7-9087-fc2a80ed9b02
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229854122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.4229854122
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.449349049
Short name T759
Test name
Test status
Simulation time 26082835834 ps
CPU time 80.25 seconds
Started Feb 07 02:08:13 PM PST 24
Finished Feb 07 02:09:34 PM PST 24
Peak memory 218528 kb
Host smart-7ecda2f9-216d-4992-b049-42c5947f125b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449349049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_mem_partial_access.449349049
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.981961533
Short name T352
Test name
Test status
Simulation time 14083030017 ps
CPU time 146.57 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:10:42 PM PST 24
Peak memory 202248 kb
Host smart-01a41bb8-20f2-4295-a6ec-bf8856685874
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981961533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl
_mem_walk.981961533
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.897991308
Short name T389
Test name
Test status
Simulation time 36439771345 ps
CPU time 1386.31 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:31:22 PM PST 24
Peak memory 378044 kb
Host smart-57199f20-00bc-4d96-8318-5a417f057b31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897991308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multip
le_keys.897991308
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.292099022
Short name T479
Test name
Test status
Simulation time 23069469799 ps
CPU time 36.4 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:08:51 PM PST 24
Peak memory 202092 kb
Host smart-55906135-13c9-4b23-b228-be6b35292630
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292099022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s
ram_ctrl_partial_access.292099022
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.650354276
Short name T251
Test name
Test status
Simulation time 36963563494 ps
CPU time 292.65 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:13:05 PM PST 24
Peak memory 202300 kb
Host smart-e397e923-dc07-4130-bd04-1f51cfa505e5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650354276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.sram_ctrl_partial_access_b2b.650354276
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.525170940
Short name T662
Test name
Test status
Simulation time 360279591 ps
CPU time 6.23 seconds
Started Feb 07 02:08:40 PM PST 24
Finished Feb 07 02:08:47 PM PST 24
Peak memory 202324 kb
Host smart-eaf7f851-c1e2-4ed3-a53a-9a683d485c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525170940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.525170940
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.2826771759
Short name T467
Test name
Test status
Simulation time 69168694957 ps
CPU time 1058.56 seconds
Started Feb 07 02:08:10 PM PST 24
Finished Feb 07 02:25:49 PM PST 24
Peak memory 370932 kb
Host smart-ea0107c2-765e-4a39-b705-d6b9a5be5179
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826771759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2826771759
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.639646831
Short name T643
Test name
Test status
Simulation time 3715186990 ps
CPU time 141.01 seconds
Started Feb 07 02:08:13 PM PST 24
Finished Feb 07 02:10:35 PM PST 24
Peak memory 362620 kb
Host smart-31dd344f-c0bc-4bb0-898e-09881d9bdba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639646831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.639646831
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3331934906
Short name T12
Test name
Test status
Simulation time 574808471 ps
CPU time 4030.06 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 03:15:34 PM PST 24
Peak memory 707040 kb
Host smart-8da5e8dd-3fa1-4632-8ae2-f25320533c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3331934906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3331934906
Directory /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1685497973
Short name T439
Test name
Test status
Simulation time 3863614536 ps
CPU time 314.57 seconds
Started Feb 07 02:08:06 PM PST 24
Finished Feb 07 02:13:22 PM PST 24
Peak memory 202244 kb
Host smart-5550f5fa-ebbb-4a85-8875-dcaeb75e0af1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685497973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.1685497973
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2845605406
Short name T835
Test name
Test status
Simulation time 1429166221 ps
CPU time 26.31 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:08:39 PM PST 24
Peak memory 210364 kb
Host smart-c1171114-9dc4-4d8f-bc2d-67fdaaa22141
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845605406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2845605406
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.1650628899
Short name T638
Test name
Test status
Simulation time 15944966 ps
CPU time 0.65 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:08:12 PM PST 24
Peak memory 201492 kb
Host smart-913a894f-aab2-44c6-9eec-85a37da94ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650628899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.1650628899
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.2843155350
Short name T791
Test name
Test status
Simulation time 24422382318 ps
CPU time 1662.88 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:35:56 PM PST 24
Peak memory 202252 kb
Host smart-26937fec-0810-4f11-933c-04738d5982a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843155350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.2843155350
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.189781266
Short name T551
Test name
Test status
Simulation time 17888951696 ps
CPU time 1117.82 seconds
Started Feb 07 02:08:10 PM PST 24
Finished Feb 07 02:26:49 PM PST 24
Peak memory 374932 kb
Host smart-60887982-e409-4332-bc71-6a844ea89ca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189781266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executabl
e.189781266
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.2818139273
Short name T51
Test name
Test status
Simulation time 7499598164 ps
CPU time 203.99 seconds
Started Feb 07 02:08:13 PM PST 24
Finished Feb 07 02:11:38 PM PST 24
Peak memory 210392 kb
Host smart-1aaa26c7-b474-491d-ad0f-a4130637c1ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818139273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.2818139273
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2786426966
Short name T466
Test name
Test status
Simulation time 765620575 ps
CPU time 100.28 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:09:52 PM PST 24
Peak memory 330032 kb
Host smart-c50c0be9-cdfb-4528-bff3-8728ea361d0f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786426966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2786426966
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1158984023
Short name T358
Test name
Test status
Simulation time 18032136848 ps
CPU time 91.75 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:09:44 PM PST 24
Peak memory 218584 kb
Host smart-41541778-05d8-4d72-8b19-125d1b88cb0a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158984023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_mem_partial_access.1158984023
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1900578617
Short name T706
Test name
Test status
Simulation time 2060956631 ps
CPU time 123.5 seconds
Started Feb 07 02:08:13 PM PST 24
Finished Feb 07 02:10:17 PM PST 24
Peak memory 202064 kb
Host smart-fc8d6e6a-e7dc-4234-8f2f-bf7f40522449
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900578617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1900578617
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.807816255
Short name T899
Test name
Test status
Simulation time 18452759895 ps
CPU time 1528.57 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:33:44 PM PST 24
Peak memory 379080 kb
Host smart-3b3daab7-13bf-4464-9238-b7833b308dae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807816255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip
le_keys.807816255
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.1163177152
Short name T707
Test name
Test status
Simulation time 464153381 ps
CPU time 14.3 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:08:26 PM PST 24
Peak memory 228728 kb
Host smart-2ab75670-81a0-4c5c-89b4-ba168e2f4da5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163177152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.1163177152
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3561091828
Short name T856
Test name
Test status
Simulation time 51689108728 ps
CPU time 432.27 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:15:27 PM PST 24
Peak memory 202172 kb
Host smart-a5383d82-a42b-4701-81be-26de51a265a5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561091828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.3561091828
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.449382951
Short name T755
Test name
Test status
Simulation time 363261151 ps
CPU time 5.32 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:08:19 PM PST 24
Peak memory 202376 kb
Host smart-d590c479-acd1-4ce7-9e46-bdad5915165b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449382951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.449382951
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.443318599
Short name T812
Test name
Test status
Simulation time 25591373024 ps
CPU time 762.18 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:20:54 PM PST 24
Peak memory 377612 kb
Host smart-7c936255-4eca-4c26-8002-56b4c7934668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443318599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.443318599
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.3758102121
Short name T954
Test name
Test status
Simulation time 1246138189 ps
CPU time 10.71 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:08:23 PM PST 24
Peak memory 202156 kb
Host smart-9b7c65b9-e59c-4181-ae1d-d1f265bd93a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758102121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3758102121
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.1548404879
Short name T533
Test name
Test status
Simulation time 174055017347 ps
CPU time 4155.53 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 03:17:31 PM PST 24
Peak memory 379188 kb
Host smart-4f40084c-8d7d-4dba-ae7f-e4c4ec16ed91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548404879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.1548404879
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3883895602
Short name T30
Test name
Test status
Simulation time 2456740336 ps
CPU time 3866.27 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 03:12:39 PM PST 24
Peak memory 654968 kb
Host smart-24391559-01ae-4036-b4fb-c62acd8362d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3883895602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3883895602
Directory /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2980356802
Short name T773
Test name
Test status
Simulation time 25996609346 ps
CPU time 458.34 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:15:53 PM PST 24
Peak memory 202188 kb
Host smart-9c26243f-a6c3-4d9c-84e9-0ac0f59845dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980356802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.2980356802
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.398134044
Short name T521
Test name
Test status
Simulation time 12210823992 ps
CPU time 70.52 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:09:26 PM PST 24
Peak memory 293152 kb
Host smart-94e92312-125c-4726-bba7-7ebb889430f5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398134044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.398134044
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.1954928322
Short name T717
Test name
Test status
Simulation time 14663575674 ps
CPU time 901.54 seconds
Started Feb 07 02:08:21 PM PST 24
Finished Feb 07 02:23:24 PM PST 24
Peak memory 380064 kb
Host smart-69de9cd3-18ea-488f-adc5-b4c5a2733aa2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954928322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.1954928322
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.2886376213
Short name T29
Test name
Test status
Simulation time 25538717 ps
CPU time 0.64 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:08:19 PM PST 24
Peak memory 201460 kb
Host smart-195b46b9-dacd-4175-adaf-6cf9a701263a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886376213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.2886376213
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.3096549972
Short name T303
Test name
Test status
Simulation time 192100247893 ps
CPU time 929.95 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:23:45 PM PST 24
Peak memory 202220 kb
Host smart-baac1a17-2d94-420b-9a2c-fe9fb6247290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096549972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.3096549972
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1027072649
Short name T836
Test name
Test status
Simulation time 22796011038 ps
CPU time 147.9 seconds
Started Feb 07 02:08:17 PM PST 24
Finished Feb 07 02:10:46 PM PST 24
Peak memory 210496 kb
Host smart-a715415c-9510-4fe5-8ceb-f81530460c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027072649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1027072649
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.206301703
Short name T581
Test name
Test status
Simulation time 8040938930 ps
CPU time 69.62 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:09:21 PM PST 24
Peak memory 300320 kb
Host smart-6f01a5bf-5304-4311-87bc-ffd687a29a42
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206301703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.sram_ctrl_max_throughput.206301703
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.2080614142
Short name T524
Test name
Test status
Simulation time 2749553085 ps
CPU time 79.13 seconds
Started Feb 07 02:08:16 PM PST 24
Finished Feb 07 02:09:36 PM PST 24
Peak memory 211220 kb
Host smart-18edc886-dd75-4cc1-b1ce-ee675bbb6bd6
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080614142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.2080614142
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.444322242
Short name T761
Test name
Test status
Simulation time 19691030484 ps
CPU time 252.42 seconds
Started Feb 07 02:08:16 PM PST 24
Finished Feb 07 02:12:30 PM PST 24
Peak memory 202428 kb
Host smart-141b9aa3-f679-48f1-946d-d74c0da87aa3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444322242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl
_mem_walk.444322242
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3422695084
Short name T674
Test name
Test status
Simulation time 6925269799 ps
CPU time 1329.06 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:30:24 PM PST 24
Peak memory 374076 kb
Host smart-df513e67-9a82-480b-ae79-31cf7d09292d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422695084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3422695084
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.2504945983
Short name T412
Test name
Test status
Simulation time 1770278986 ps
CPU time 21.94 seconds
Started Feb 07 02:08:13 PM PST 24
Finished Feb 07 02:08:36 PM PST 24
Peak memory 202056 kb
Host smart-9033fd4c-3bd9-4751-9ad2-517dc8176304
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504945983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
sram_ctrl_partial_access.2504945983
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2239659982
Short name T784
Test name
Test status
Simulation time 8110906656 ps
CPU time 254.04 seconds
Started Feb 07 02:08:14 PM PST 24
Finished Feb 07 02:12:28 PM PST 24
Peak memory 202208 kb
Host smart-51bd8406-30c3-4581-9234-e10c80b891dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239659982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.2239659982
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.543157583
Short name T824
Test name
Test status
Simulation time 3745925013 ps
CPU time 13.52 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:08:26 PM PST 24
Peak memory 202472 kb
Host smart-09a639c4-d7ce-456c-9dfa-ace5112299e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543157583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.543157583
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.1690608408
Short name T111
Test name
Test status
Simulation time 45811741142 ps
CPU time 841.72 seconds
Started Feb 07 02:08:15 PM PST 24
Finished Feb 07 02:22:18 PM PST 24
Peak memory 374872 kb
Host smart-411fcb75-9d98-4123-90d5-33bdc986d031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690608408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1690608408
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.4193265664
Short name T794
Test name
Test status
Simulation time 419966958 ps
CPU time 19.59 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:08:32 PM PST 24
Peak memory 202144 kb
Host smart-d7260791-238d-4590-9e54-f282c04d4830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193265664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.4193265664
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2507968395
Short name T754
Test name
Test status
Simulation time 22959779653 ps
CPU time 291.79 seconds
Started Feb 07 02:08:11 PM PST 24
Finished Feb 07 02:13:03 PM PST 24
Peak memory 202296 kb
Host smart-e23c607e-0029-4046-b411-2cdda1fb2260
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507968395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.2507968395
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.228758554
Short name T690
Test name
Test status
Simulation time 3045737650 ps
CPU time 102.5 seconds
Started Feb 07 02:08:12 PM PST 24
Finished Feb 07 02:09:56 PM PST 24
Peak memory 326492 kb
Host smart-ca342f3a-8746-43c8-9953-1d38ffbc8ece
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228758554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_throughput_w_partial_write.228758554
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1041207880
Short name T834
Test name
Test status
Simulation time 7256120679 ps
CPU time 1087.11 seconds
Started Feb 07 02:00:54 PM PST 24
Finished Feb 07 02:19:04 PM PST 24
Peak memory 379212 kb
Host smart-2ea67a34-89fe-4b13-9358-53b38ad803dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041207880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.1041207880
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1514975474
Short name T496
Test name
Test status
Simulation time 17116115 ps
CPU time 0.69 seconds
Started Feb 07 02:01:01 PM PST 24
Finished Feb 07 02:01:04 PM PST 24
Peak memory 201812 kb
Host smart-2ef164eb-bebe-4ac8-be3d-4a6d447403cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514975474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1514975474
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2561459098
Short name T470
Test name
Test status
Simulation time 34166422844 ps
CPU time 587.31 seconds
Started Feb 07 02:01:00 PM PST 24
Finished Feb 07 02:10:48 PM PST 24
Peak memory 202248 kb
Host smart-9342dd4e-ad97-4c9e-aea2-0fbc217b4daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561459098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2561459098
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.3184750939
Short name T617
Test name
Test status
Simulation time 11581071987 ps
CPU time 765.1 seconds
Started Feb 07 02:00:58 PM PST 24
Finished Feb 07 02:13:44 PM PST 24
Peak memory 372928 kb
Host smart-048edce9-5349-47c8-a814-2ffdad9024b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184750939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.3184750939
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.3110641346
Short name T498
Test name
Test status
Simulation time 40421727205 ps
CPU time 133.13 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:03:18 PM PST 24
Peak memory 210376 kb
Host smart-e75e3188-900a-4fad-baf2-77f46f6eb841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110641346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.3110641346
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.318548642
Short name T523
Test name
Test status
Simulation time 10179909520 ps
CPU time 52.07 seconds
Started Feb 07 02:00:52 PM PST 24
Finished Feb 07 02:01:47 PM PST 24
Peak memory 283964 kb
Host smart-d4f5ec81-47cf-4347-8e33-690b1cf35cfd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318548642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.sram_ctrl_max_throughput.318548642
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2491802955
Short name T850
Test name
Test status
Simulation time 10665704492 ps
CPU time 79.83 seconds
Started Feb 07 02:00:55 PM PST 24
Finished Feb 07 02:02:17 PM PST 24
Peak memory 211284 kb
Host smart-06cb78c7-1309-4a72-b61b-5a489d2bda3c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491802955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.2491802955
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.720629979
Short name T723
Test name
Test status
Simulation time 21916420273 ps
CPU time 153.03 seconds
Started Feb 07 02:00:56 PM PST 24
Finished Feb 07 02:03:30 PM PST 24
Peak memory 202276 kb
Host smart-7ae31a22-3828-4bd7-ba55-dba4c6b8b110
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720629979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
mem_walk.720629979
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.3740542776
Short name T933
Test name
Test status
Simulation time 19324435237 ps
CPU time 1149.78 seconds
Started Feb 07 02:00:54 PM PST 24
Finished Feb 07 02:20:06 PM PST 24
Peak memory 378028 kb
Host smart-1dcff03c-a88a-476d-a9b9-bbf958fd139e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740542776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.3740542776
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.4238136246
Short name T769
Test name
Test status
Simulation time 1573619339 ps
CPU time 39.27 seconds
Started Feb 07 02:00:53 PM PST 24
Finished Feb 07 02:01:35 PM PST 24
Peak memory 282832 kb
Host smart-a4d06f14-afa6-4458-8b5d-d5a743e4a38b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238136246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.4238136246
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2785807288
Short name T484
Test name
Test status
Simulation time 6503816566 ps
CPU time 394.83 seconds
Started Feb 07 02:00:55 PM PST 24
Finished Feb 07 02:07:32 PM PST 24
Peak memory 202208 kb
Host smart-8f0ea478-5b7e-497f-8032-60be843914b1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785807288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.2785807288
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.428616921
Short name T429
Test name
Test status
Simulation time 1203890728 ps
CPU time 6.67 seconds
Started Feb 07 02:00:56 PM PST 24
Finished Feb 07 02:01:04 PM PST 24
Peak memory 202364 kb
Host smart-a33b2eea-1270-4be6-93b7-546a2da6ab58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428616921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.428616921
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.4050390180
Short name T310
Test name
Test status
Simulation time 4113779521 ps
CPU time 96.99 seconds
Started Feb 07 02:00:54 PM PST 24
Finished Feb 07 02:02:33 PM PST 24
Peak memory 302368 kb
Host smart-87641e0f-3d3e-440c-9f58-cab64cf72d98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050390180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.4050390180
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.3820788437
Short name T20
Test name
Test status
Simulation time 288242502 ps
CPU time 3.27 seconds
Started Feb 07 02:00:54 PM PST 24
Finished Feb 07 02:00:59 PM PST 24
Peak memory 221020 kb
Host smart-fb2fd558-2625-4fa4-b62b-ec16cda9e52a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820788437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.3820788437
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.2306259605
Short name T689
Test name
Test status
Simulation time 3397774309 ps
CPU time 36.17 seconds
Started Feb 07 02:00:55 PM PST 24
Finished Feb 07 02:01:33 PM PST 24
Peak memory 202208 kb
Host smart-78c8cdbb-c12f-440b-850c-5845099e6c5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306259605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2306259605
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.2821074513
Short name T312
Test name
Test status
Simulation time 58009673697 ps
CPU time 3555.66 seconds
Started Feb 07 02:00:57 PM PST 24
Finished Feb 07 03:00:14 PM PST 24
Peak memory 218520 kb
Host smart-3e8f24dd-5915-4682-9b2d-754e849ac0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821074513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.2821074513
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.298311010
Short name T444
Test name
Test status
Simulation time 272965284 ps
CPU time 1412.97 seconds
Started Feb 07 02:01:03 PM PST 24
Finished Feb 07 02:24:38 PM PST 24
Peak memory 455744 kb
Host smart-a2bfd944-2789-4897-92f4-9c66e4893bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=298311010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.298311010
Directory /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3652095252
Short name T756
Test name
Test status
Simulation time 4126227600 ps
CPU time 337.39 seconds
Started Feb 07 02:00:53 PM PST 24
Finished Feb 07 02:06:33 PM PST 24
Peak memory 202204 kb
Host smart-5faee3a2-2be3-492e-837b-d5a099856607
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652095252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.3652095252
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.692380699
Short name T377
Test name
Test status
Simulation time 2167228906 ps
CPU time 147.37 seconds
Started Feb 07 02:01:06 PM PST 24
Finished Feb 07 02:03:35 PM PST 24
Peak memory 358636 kb
Host smart-07c163a8-636d-473e-8230-7b9de56504da
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692380699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.692380699
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3228625676
Short name T550
Test name
Test status
Simulation time 1772762425 ps
CPU time 216.87 seconds
Started Feb 07 02:08:21 PM PST 24
Finished Feb 07 02:11:59 PM PST 24
Peak memory 363188 kb
Host smart-fec407dd-6f44-44ec-9d20-3964054cfa4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228625676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.3228625676
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.2698482017
Short name T863
Test name
Test status
Simulation time 12231047 ps
CPU time 0.62 seconds
Started Feb 07 02:08:29 PM PST 24
Finished Feb 07 02:08:30 PM PST 24
Peak memory 201472 kb
Host smart-d06b8459-f38d-4ed5-90e2-3731804bd9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698482017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.2698482017
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.2010568778
Short name T344
Test name
Test status
Simulation time 58793362339 ps
CPU time 1987.5 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:41:27 PM PST 24
Peak memory 210320 kb
Host smart-5ec326ea-5adb-472f-aeb3-c26ec768a9b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010568778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.2010568778
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.871661546
Short name T785
Test name
Test status
Simulation time 5220162598 ps
CPU time 55.68 seconds
Started Feb 07 02:08:16 PM PST 24
Finished Feb 07 02:09:12 PM PST 24
Peak memory 202232 kb
Host smart-53744700-1836-4710-8ab3-4c1f686683ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871661546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_esc
alation.871661546
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.119947091
Short name T862
Test name
Test status
Simulation time 1520487585 ps
CPU time 78.8 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:09:37 PM PST 24
Peak memory 337208 kb
Host smart-99e67922-3dd0-40a6-9af9-d616b7f6b68b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119947091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.119947091
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2403066646
Short name T474
Test name
Test status
Simulation time 3191332846 ps
CPU time 136.87 seconds
Started Feb 07 02:08:28 PM PST 24
Finished Feb 07 02:10:45 PM PST 24
Peak memory 214580 kb
Host smart-eff6260b-f9d7-477e-b278-9a9f19672c1e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403066646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.2403066646
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.751841733
Short name T799
Test name
Test status
Simulation time 6903031607 ps
CPU time 143.59 seconds
Started Feb 07 02:08:21 PM PST 24
Finished Feb 07 02:10:45 PM PST 24
Peak memory 202188 kb
Host smart-947583ff-adbf-4f14-99c3-e9ec32af8805
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751841733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl
_mem_walk.751841733
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.3584528637
Short name T399
Test name
Test status
Simulation time 63229437703 ps
CPU time 659.47 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:19:18 PM PST 24
Peak memory 378740 kb
Host smart-cfb9d0f1-137f-4a82-bf10-cc280b851e5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584528637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.3584528637
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.2302867489
Short name T618
Test name
Test status
Simulation time 956645496 ps
CPU time 42.35 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:09:01 PM PST 24
Peak memory 202100 kb
Host smart-a05b2a6f-07b3-4e2e-afb3-28e497cdc420
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302867489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
sram_ctrl_partial_access.2302867489
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1046724359
Short name T619
Test name
Test status
Simulation time 32080339279 ps
CPU time 209.67 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 02:11:53 PM PST 24
Peak memory 202052 kb
Host smart-306c993a-f652-46fd-bb3e-7af818ceb787
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046724359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.1046724359
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.512381561
Short name T798
Test name
Test status
Simulation time 715244047 ps
CPU time 5.5 seconds
Started Feb 07 02:08:28 PM PST 24
Finished Feb 07 02:08:34 PM PST 24
Peak memory 202356 kb
Host smart-d920a4b7-ad08-4981-adff-04c37624c8e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512381561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.512381561
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.1584928258
Short name T254
Test name
Test status
Simulation time 1573745071 ps
CPU time 368.41 seconds
Started Feb 07 02:08:28 PM PST 24
Finished Feb 07 02:14:37 PM PST 24
Peak memory 346328 kb
Host smart-565d8ce0-247d-4ea9-89ed-17ad0fa654c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584928258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1584928258
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.1922154470
Short name T722
Test name
Test status
Simulation time 404758654 ps
CPU time 8.09 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:08:27 PM PST 24
Peak memory 207392 kb
Host smart-f8d3fbbf-7dc6-4082-9819-b1eb8a9fb5df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922154470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1922154470
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1256534117
Short name T831
Test name
Test status
Simulation time 6140393133 ps
CPU time 4641.51 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 03:25:46 PM PST 24
Peak memory 645056 kb
Host smart-9c351ad9-4ae8-4eb4-b199-bb4f7fd368e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1256534117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1256534117
Directory /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3953664340
Short name T107
Test name
Test status
Simulation time 5698513110 ps
CPU time 364.92 seconds
Started Feb 07 02:08:17 PM PST 24
Finished Feb 07 02:14:23 PM PST 24
Peak memory 202192 kb
Host smart-c8dd5738-60af-4aed-bfa6-e496f6275c3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953664340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.3953664340
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3186084821
Short name T700
Test name
Test status
Simulation time 2097730917 ps
CPU time 151.53 seconds
Started Feb 07 02:08:21 PM PST 24
Finished Feb 07 02:10:54 PM PST 24
Peak memory 354460 kb
Host smart-a448bfcc-25b0-4581-9f60-c16f4d6fff5d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186084821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.3186084821
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3949779633
Short name T277
Test name
Test status
Simulation time 14076090952 ps
CPU time 1170.62 seconds
Started Feb 07 02:08:20 PM PST 24
Finished Feb 07 02:27:52 PM PST 24
Peak memory 377784 kb
Host smart-cc1d3fdb-a402-430f-81c6-14a0164723e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949779633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.3949779633
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.1746472228
Short name T886
Test name
Test status
Simulation time 19437765 ps
CPU time 0.63 seconds
Started Feb 07 02:08:16 PM PST 24
Finished Feb 07 02:08:17 PM PST 24
Peak memory 201868 kb
Host smart-fe22ed4f-e11f-4221-9896-c81814590f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746472228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.1746472228
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.3679859191
Short name T762
Test name
Test status
Simulation time 176374466405 ps
CPU time 1359.28 seconds
Started Feb 07 02:08:34 PM PST 24
Finished Feb 07 02:31:15 PM PST 24
Peak memory 202300 kb
Host smart-306b3562-6f25-4f45-a79e-c13e4eca3f13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679859191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.3679859191
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.3571829753
Short name T7
Test name
Test status
Simulation time 13529706549 ps
CPU time 40.12 seconds
Started Feb 07 02:08:10 PM PST 24
Finished Feb 07 02:08:51 PM PST 24
Peak memory 210432 kb
Host smart-580dd7b1-70c6-4e9a-bc74-2c42f2412171
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571829753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.3571829753
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.1872942893
Short name T732
Test name
Test status
Simulation time 1657716656 ps
CPU time 69.82 seconds
Started Feb 07 02:08:25 PM PST 24
Finished Feb 07 02:09:35 PM PST 24
Peak memory 311096 kb
Host smart-87f0c4f5-811e-4e52-aef1-b41108802168
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872942893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.1872942893
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1626280187
Short name T89
Test name
Test status
Simulation time 988837488 ps
CPU time 70.85 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 02:09:35 PM PST 24
Peak memory 210648 kb
Host smart-1271f0e6-8fff-44e8-ab37-a595adf60afc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626280187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1626280187
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.3345644288
Short name T953
Test name
Test status
Simulation time 43025791464 ps
CPU time 152.24 seconds
Started Feb 07 02:08:16 PM PST 24
Finished Feb 07 02:10:49 PM PST 24
Peak memory 202244 kb
Host smart-dfcd9c2d-8f3e-458c-9ac8-6b47f4d64e15
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345644288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.3345644288
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.1212733669
Short name T339
Test name
Test status
Simulation time 2191429575 ps
CPU time 72.04 seconds
Started Feb 07 02:08:34 PM PST 24
Finished Feb 07 02:09:47 PM PST 24
Peak memory 295224 kb
Host smart-a5e7bc56-a447-41b6-90a7-3e963932a8de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212733669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.1212733669
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.2530112948
Short name T956
Test name
Test status
Simulation time 488794595 ps
CPU time 13.16 seconds
Started Feb 07 02:08:28 PM PST 24
Finished Feb 07 02:08:42 PM PST 24
Peak memory 224996 kb
Host smart-daaed59f-c7a2-4768-9e95-b8c80d1aea4d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530112948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.2530112948
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1976624446
Short name T771
Test name
Test status
Simulation time 70611768352 ps
CPU time 235.46 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 02:12:20 PM PST 24
Peak memory 202100 kb
Host smart-5ba9ce20-dfb1-488c-a7c5-8729894f31e3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976624446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.1976624446
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2165394280
Short name T261
Test name
Test status
Simulation time 1401479290 ps
CPU time 5.58 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 02:08:29 PM PST 24
Peak memory 202456 kb
Host smart-7e61f07d-4ada-4885-afa8-f51fa451451d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165394280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2165394280
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.2763872034
Short name T478
Test name
Test status
Simulation time 7644863533 ps
CPU time 621.57 seconds
Started Feb 07 02:08:24 PM PST 24
Finished Feb 07 02:18:46 PM PST 24
Peak memory 380144 kb
Host smart-0034cbad-1204-4b3c-a003-fe635c657f5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763872034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2763872034
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.2302270766
Short name T790
Test name
Test status
Simulation time 454053619 ps
CPU time 21.26 seconds
Started Feb 07 02:08:29 PM PST 24
Finished Feb 07 02:08:51 PM PST 24
Peak memory 202128 kb
Host smart-6fbc9ef8-8ca0-4379-814c-12a16da5f09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302270766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2302270766
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.3148918500
Short name T331
Test name
Test status
Simulation time 76967506023 ps
CPU time 3253.57 seconds
Started Feb 07 02:08:15 PM PST 24
Finished Feb 07 03:02:30 PM PST 24
Peak memory 378016 kb
Host smart-da1359be-25a6-4f63-8e53-367d5ce722a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148918500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.3148918500
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1599509334
Short name T356
Test name
Test status
Simulation time 777084097 ps
CPU time 3279.49 seconds
Started Feb 07 02:08:24 PM PST 24
Finished Feb 07 03:03:04 PM PST 24
Peak memory 611728 kb
Host smart-7fcecfd9-d4a0-44e8-8a5e-292b9311d8f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1599509334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1599509334
Directory /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.372362568
Short name T604
Test name
Test status
Simulation time 20746299274 ps
CPU time 213.99 seconds
Started Feb 07 02:08:27 PM PST 24
Finished Feb 07 02:12:02 PM PST 24
Peak memory 202236 kb
Host smart-086f4824-29fa-4daa-905e-4564014934f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372362568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.sram_ctrl_stress_pipeline.372362568
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1710080927
Short name T340
Test name
Test status
Simulation time 1573700925 ps
CPU time 89.21 seconds
Started Feb 07 02:08:27 PM PST 24
Finished Feb 07 02:09:57 PM PST 24
Peak memory 333876 kb
Host smart-1757e68a-4383-4d4c-8de5-8e8c1369d3e7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710080927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.1710080927
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1248983097
Short name T676
Test name
Test status
Simulation time 16925539630 ps
CPU time 1564.4 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:34:23 PM PST 24
Peak memory 378172 kb
Host smart-de6f5961-664d-462b-a1a0-571e67f50579
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248983097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1248983097
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.985390787
Short name T381
Test name
Test status
Simulation time 13284715 ps
CPU time 0.64 seconds
Started Feb 07 02:08:15 PM PST 24
Finished Feb 07 02:08:17 PM PST 24
Peak memory 201952 kb
Host smart-c265ee14-ad90-4fc3-9fea-f24d9d834eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985390787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.985390787
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.2150171428
Short name T263
Test name
Test status
Simulation time 18943059609 ps
CPU time 894.49 seconds
Started Feb 07 02:08:15 PM PST 24
Finished Feb 07 02:23:11 PM PST 24
Peak memory 202236 kb
Host smart-22559c4e-adec-4a68-a796-06f677db9e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150171428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.2150171428
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.1928411165
Short name T820
Test name
Test status
Simulation time 19847332381 ps
CPU time 1155.35 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:27:35 PM PST 24
Peak memory 367996 kb
Host smart-4ef5196b-33ad-4889-8444-d68330055148
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928411165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.1928411165
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.1722846853
Short name T760
Test name
Test status
Simulation time 40740596132 ps
CPU time 215.27 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:11:55 PM PST 24
Peak memory 210428 kb
Host smart-56d8a5a8-dce8-42f4-b233-20170b241def
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722846853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.1722846853
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.3649988933
Short name T931
Test name
Test status
Simulation time 5346024500 ps
CPU time 34.51 seconds
Started Feb 07 02:08:17 PM PST 24
Finished Feb 07 02:08:53 PM PST 24
Peak memory 243520 kb
Host smart-61202f74-82da-4d8f-bfaf-994a8bbf51c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649988933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.3649988933
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3141386333
Short name T665
Test name
Test status
Simulation time 22955352749 ps
CPU time 139.15 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:10:38 PM PST 24
Peak memory 210568 kb
Host smart-cac187f3-af2c-4074-8186-5e1c7d3dd4eb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141386333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.3141386333
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.2967803836
Short name T293
Test name
Test status
Simulation time 31356926751 ps
CPU time 142.82 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:10:42 PM PST 24
Peak memory 202560 kb
Host smart-24c9287c-6804-41d6-95aa-121da1666301
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967803836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.2967803836
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.930823022
Short name T687
Test name
Test status
Simulation time 12288376861 ps
CPU time 927.91 seconds
Started Feb 07 02:08:16 PM PST 24
Finished Feb 07 02:23:45 PM PST 24
Peak memory 372936 kb
Host smart-51fdb3b4-2f75-485a-b555-f74602fec5de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930823022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip
le_keys.930823022
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.938993331
Short name T940
Test name
Test status
Simulation time 532069674 ps
CPU time 122.98 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:10:23 PM PST 24
Peak memory 360520 kb
Host smart-820024b4-3a64-4466-8745-bbd8a412f422
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938993331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s
ram_ctrl_partial_access.938993331
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1617388637
Short name T105
Test name
Test status
Simulation time 28652765761 ps
CPU time 361.1 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:14:21 PM PST 24
Peak memory 202208 kb
Host smart-2a55f954-d333-4afa-87e3-3fd97f0f9150
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617388637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1617388637
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3937828635
Short name T720
Test name
Test status
Simulation time 347180892 ps
CPU time 13.72 seconds
Started Feb 07 02:08:17 PM PST 24
Finished Feb 07 02:08:32 PM PST 24
Peak memory 202380 kb
Host smart-0585d180-0818-4b2f-bccc-8d134ba8a5b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937828635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3937828635
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.3564713453
Short name T557
Test name
Test status
Simulation time 14246556920 ps
CPU time 986.05 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:24:46 PM PST 24
Peak memory 378068 kb
Host smart-0296ac40-972f-4477-a0f7-a192282e4474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564713453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3564713453
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.3611589179
Short name T895
Test name
Test status
Simulation time 453825700 ps
CPU time 10.45 seconds
Started Feb 07 02:08:16 PM PST 24
Finished Feb 07 02:08:27 PM PST 24
Peak memory 220196 kb
Host smart-e59eeb17-6520-4142-a82e-1892f822e512
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611589179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3611589179
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4046395749
Short name T510
Test name
Test status
Simulation time 2123308459 ps
CPU time 6951.55 seconds
Started Feb 07 02:08:20 PM PST 24
Finished Feb 07 04:04:13 PM PST 24
Peak memory 651884 kb
Host smart-5dfb0b48-f64f-402f-85c1-3b2db27648d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4046395749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.4046395749
Directory /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.985395195
Short name T894
Test name
Test status
Simulation time 5044890371 ps
CPU time 416.97 seconds
Started Feb 07 02:08:13 PM PST 24
Finished Feb 07 02:15:11 PM PST 24
Peak memory 210320 kb
Host smart-2d3f22d9-77dc-4169-99ec-cad50058a67c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985395195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.sram_ctrl_stress_pipeline.985395195
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2233300256
Short name T888
Test name
Test status
Simulation time 2602676480 ps
CPU time 167.06 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:11:06 PM PST 24
Peak memory 365716 kb
Host smart-ceba2de5-98e4-499c-924c-274bcb36f59d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233300256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2233300256
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2358052552
Short name T404
Test name
Test status
Simulation time 46628470595 ps
CPU time 819.55 seconds
Started Feb 07 02:08:33 PM PST 24
Finished Feb 07 02:22:14 PM PST 24
Peak memory 375992 kb
Host smart-5ff1871e-8c0a-4895-b725-3fa74c2c98a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358052552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2358052552
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.820374432
Short name T368
Test name
Test status
Simulation time 22824679 ps
CPU time 0.62 seconds
Started Feb 07 02:08:33 PM PST 24
Finished Feb 07 02:08:35 PM PST 24
Peak memory 201936 kb
Host smart-baecccb5-ccae-40bf-b0ef-d733479b8475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820374432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.820374432
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.3354532428
Short name T318
Test name
Test status
Simulation time 103774042961 ps
CPU time 1165.26 seconds
Started Feb 07 02:08:23 PM PST 24
Finished Feb 07 02:27:49 PM PST 24
Peak memory 202024 kb
Host smart-78b7ba99-dd2b-4b5b-8a4f-dbf72ecffaf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354532428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.3354532428
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.2268791501
Short name T600
Test name
Test status
Simulation time 21347866272 ps
CPU time 1123.76 seconds
Started Feb 07 02:08:29 PM PST 24
Finished Feb 07 02:27:13 PM PST 24
Peak memory 376480 kb
Host smart-ea26ced5-75ea-4dad-b769-5d02ecfed592
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268791501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executab
le.2268791501
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.2494555519
Short name T304
Test name
Test status
Simulation time 11054085185 ps
CPU time 57.17 seconds
Started Feb 07 02:08:27 PM PST 24
Finished Feb 07 02:09:25 PM PST 24
Peak memory 210372 kb
Host smart-d8d5462e-9c55-4434-ac2c-98f081092a58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494555519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.2494555519
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.994229597
Short name T289
Test name
Test status
Simulation time 1441166242 ps
CPU time 67.23 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:09:27 PM PST 24
Peak memory 292268 kb
Host smart-37155332-5c8f-4160-a549-ab40b5c22e08
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994229597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.sram_ctrl_max_throughput.994229597
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3755096823
Short name T279
Test name
Test status
Simulation time 2457396146 ps
CPU time 79.07 seconds
Started Feb 07 02:08:28 PM PST 24
Finished Feb 07 02:09:48 PM PST 24
Peak memory 211804 kb
Host smart-c044b908-8150-4f4c-bf93-63971692b23c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755096823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.3755096823
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.3327080336
Short name T139
Test name
Test status
Simulation time 28703359251 ps
CPU time 143.87 seconds
Started Feb 07 02:08:34 PM PST 24
Finished Feb 07 02:10:59 PM PST 24
Peak memory 202272 kb
Host smart-13b3aff8-3205-4d5d-9af5-17b6b7167908
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327080336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.3327080336
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.452101398
Short name T327
Test name
Test status
Simulation time 108531388925 ps
CPU time 1676.74 seconds
Started Feb 07 02:08:29 PM PST 24
Finished Feb 07 02:36:26 PM PST 24
Peak memory 378084 kb
Host smart-b302d937-5a81-47fb-b7c1-eef1f8261486
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452101398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multip
le_keys.452101398
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.4044815368
Short name T252
Test name
Test status
Simulation time 4054021761 ps
CPU time 19.31 seconds
Started Feb 07 02:08:20 PM PST 24
Finished Feb 07 02:08:40 PM PST 24
Peak memory 210336 kb
Host smart-c5635ebc-c8b3-4f17-851c-8a8c005e3e11
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044815368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.4044815368
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.284899439
Short name T366
Test name
Test status
Simulation time 71826783914 ps
CPU time 451 seconds
Started Feb 07 02:08:17 PM PST 24
Finished Feb 07 02:15:49 PM PST 24
Peak memory 202140 kb
Host smart-5b1a6cf2-62f9-4ef7-bda1-7a82f5bba2bd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284899439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.sram_ctrl_partial_access_b2b.284899439
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.275669259
Short name T948
Test name
Test status
Simulation time 1294268688 ps
CPU time 6.79 seconds
Started Feb 07 02:08:20 PM PST 24
Finished Feb 07 02:08:28 PM PST 24
Peak memory 202440 kb
Host smart-2cd8b41d-7faa-4882-89cd-64c00e575dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275669259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.275669259
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3816558175
Short name T727
Test name
Test status
Simulation time 14025132232 ps
CPU time 908.42 seconds
Started Feb 07 02:08:27 PM PST 24
Finished Feb 07 02:23:36 PM PST 24
Peak memory 375932 kb
Host smart-557b675f-7f0c-4da5-852f-8cf07635c934
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816558175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3816558175
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.388439668
Short name T575
Test name
Test status
Simulation time 372205731 ps
CPU time 15.66 seconds
Started Feb 07 02:08:18 PM PST 24
Finished Feb 07 02:08:34 PM PST 24
Peak memory 202116 kb
Host smart-06f0aa7e-69d3-4414-a517-760ecdec50a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388439668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.388439668
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.495703108
Short name T950
Test name
Test status
Simulation time 560789464 ps
CPU time 4633.19 seconds
Started Feb 07 02:08:33 PM PST 24
Finished Feb 07 03:25:48 PM PST 24
Peak memory 788716 kb
Host smart-73d4c451-b03c-41c3-9155-3cd9670d9994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=495703108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.495703108
Directory /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1602736184
Short name T445
Test name
Test status
Simulation time 10451697756 ps
CPU time 316.69 seconds
Started Feb 07 02:08:17 PM PST 24
Finished Feb 07 02:13:35 PM PST 24
Peak memory 202232 kb
Host smart-0b7d4fa6-0600-461e-bcaf-bcdcc0c9e50a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602736184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1602736184
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3078456511
Short name T443
Test name
Test status
Simulation time 3258058458 ps
CPU time 114.89 seconds
Started Feb 07 02:08:19 PM PST 24
Finished Feb 07 02:10:15 PM PST 24
Peak memory 367512 kb
Host smart-eb159b75-6300-4c62-97d8-ae26956e283a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078456511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3078456511
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1361219884
Short name T353
Test name
Test status
Simulation time 19459792134 ps
CPU time 563.82 seconds
Started Feb 07 02:08:30 PM PST 24
Finished Feb 07 02:17:54 PM PST 24
Peak memory 371932 kb
Host smart-eb6bcb7d-7978-4a14-8f75-a139eda03046
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361219884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.1361219884
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.2857058386
Short name T918
Test name
Test status
Simulation time 45049445 ps
CPU time 0.66 seconds
Started Feb 07 02:08:48 PM PST 24
Finished Feb 07 02:08:50 PM PST 24
Peak memory 201868 kb
Host smart-144be670-98f2-4dd8-a52c-3d13df74c112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857058386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.2857058386
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.3615090340
Short name T803
Test name
Test status
Simulation time 144668117272 ps
CPU time 2163.7 seconds
Started Feb 07 02:08:33 PM PST 24
Finished Feb 07 02:44:37 PM PST 24
Peak memory 202344 kb
Host smart-a15c49be-e79e-4191-bd4c-271b4a68c716
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615090340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.3615090340
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.3918230698
Short name T903
Test name
Test status
Simulation time 31950338679 ps
CPU time 150.47 seconds
Started Feb 07 02:08:29 PM PST 24
Finished Feb 07 02:11:00 PM PST 24
Peak memory 202088 kb
Host smart-90ca7b2f-4b65-4841-9a03-be4941f016bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918230698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.3918230698
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.3126605932
Short name T626
Test name
Test status
Simulation time 1606670764 ps
CPU time 68.9 seconds
Started Feb 07 02:08:36 PM PST 24
Finished Feb 07 02:09:45 PM PST 24
Peak memory 318608 kb
Host smart-6c16f382-ee9d-4e3d-a3db-520292fa869c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126605932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.3126605932
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3436341867
Short name T555
Test name
Test status
Simulation time 6728876900 ps
CPU time 147.03 seconds
Started Feb 07 02:08:48 PM PST 24
Finished Feb 07 02:11:16 PM PST 24
Peak memory 211304 kb
Host smart-670724b6-c394-4229-ad43-a1d71fc7d6ce
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436341867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.3436341867
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.1892015329
Short name T544
Test name
Test status
Simulation time 55122443854 ps
CPU time 291.85 seconds
Started Feb 07 02:08:39 PM PST 24
Finished Feb 07 02:13:32 PM PST 24
Peak memory 202612 kb
Host smart-89870279-c1e3-4750-a1a1-384413b07683
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892015329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.1892015329
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.1530967305
Short name T786
Test name
Test status
Simulation time 8243694650 ps
CPU time 477.29 seconds
Started Feb 07 02:08:34 PM PST 24
Finished Feb 07 02:16:32 PM PST 24
Peak memory 378780 kb
Host smart-a17211b2-e75e-4196-bfb1-74cb86f0c137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530967305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.1530967305
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.3866113368
Short name T274
Test name
Test status
Simulation time 2419907651 ps
CPU time 106.93 seconds
Started Feb 07 02:08:30 PM PST 24
Finished Feb 07 02:10:18 PM PST 24
Peak memory 336032 kb
Host smart-f829ae63-6f02-456d-8915-3243f0453117
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866113368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.3866113368
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3393389264
Short name T828
Test name
Test status
Simulation time 14145327666 ps
CPU time 310.51 seconds
Started Feb 07 02:08:31 PM PST 24
Finished Feb 07 02:13:42 PM PST 24
Peak memory 210360 kb
Host smart-fce11959-764b-4885-ac35-e9ead8272b24
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393389264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.3393389264
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.373676546
Short name T874
Test name
Test status
Simulation time 826705968 ps
CPU time 14.36 seconds
Started Feb 07 02:08:38 PM PST 24
Finished Feb 07 02:08:53 PM PST 24
Peak memory 202356 kb
Host smart-32aedceb-b466-4362-a5f6-326873447ebc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373676546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.373676546
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.3652143009
Short name T847
Test name
Test status
Simulation time 40181321894 ps
CPU time 2237.48 seconds
Started Feb 07 02:08:39 PM PST 24
Finished Feb 07 02:45:57 PM PST 24
Peak memory 377056 kb
Host smart-84a2e7a9-a54a-4722-b2ee-a7c339e871db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652143009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3652143009
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.2792294217
Short name T232
Test name
Test status
Simulation time 971239501 ps
CPU time 149.71 seconds
Started Feb 07 02:08:34 PM PST 24
Finished Feb 07 02:11:04 PM PST 24
Peak memory 364652 kb
Host smart-133b5329-c91c-4be7-b1d6-851b46cf1932
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792294217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2792294217
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3177255903
Short name T266
Test name
Test status
Simulation time 62187650876 ps
CPU time 2169.38 seconds
Started Feb 07 02:08:49 PM PST 24
Finished Feb 07 02:45:00 PM PST 24
Peak memory 377000 kb
Host smart-453c379e-1395-4351-973e-0b1295a07799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177255903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3177255903
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3926540629
Short name T525
Test name
Test status
Simulation time 12403402900 ps
CPU time 211.34 seconds
Started Feb 07 02:08:27 PM PST 24
Finished Feb 07 02:11:59 PM PST 24
Peak memory 202228 kb
Host smart-5873b7ca-b99f-43dc-b0dc-63945070aa3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926540629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3926540629
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1349392757
Short name T207
Test name
Test status
Simulation time 752745551 ps
CPU time 40.54 seconds
Started Feb 07 02:08:30 PM PST 24
Finished Feb 07 02:09:11 PM PST 24
Peak memory 261324 kb
Host smart-52aefded-7c5c-4d38-a779-f8ac9183229e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349392757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1349392757
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1536274938
Short name T671
Test name
Test status
Simulation time 27872366717 ps
CPU time 1834.91 seconds
Started Feb 07 02:09:01 PM PST 24
Finished Feb 07 02:39:37 PM PST 24
Peak memory 378992 kb
Host smart-bd482d4d-c3cd-4c47-b32d-1e7a4b80f0a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536274938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.sram_ctrl_access_during_key_req.1536274938
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2136617766
Short name T256
Test name
Test status
Simulation time 25017613 ps
CPU time 0.69 seconds
Started Feb 07 02:09:02 PM PST 24
Finished Feb 07 02:09:03 PM PST 24
Peak memory 201428 kb
Host smart-3e955c7e-e2c5-4084-835e-fe2f6cd103cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136617766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2136617766
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.2021227475
Short name T502
Test name
Test status
Simulation time 43873443927 ps
CPU time 806.86 seconds
Started Feb 07 02:08:49 PM PST 24
Finished Feb 07 02:22:16 PM PST 24
Peak memory 202296 kb
Host smart-e67aed22-c287-459b-b3ad-cb20df2e7e20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021227475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.2021227475
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.194290117
Short name T697
Test name
Test status
Simulation time 10303116850 ps
CPU time 99.6 seconds
Started Feb 07 02:08:49 PM PST 24
Finished Feb 07 02:10:29 PM PST 24
Peak memory 213816 kb
Host smart-e350c086-7865-4c20-b3a8-351ae638b18c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194290117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esc
alation.194290117
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.3147983710
Short name T808
Test name
Test status
Simulation time 752935005 ps
CPU time 75.84 seconds
Started Feb 07 02:08:51 PM PST 24
Finished Feb 07 02:10:07 PM PST 24
Peak memory 325744 kb
Host smart-e02cc0cb-d3cc-48f5-adda-f4cb1463b17f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147983710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.3147983710
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4212941308
Short name T503
Test name
Test status
Simulation time 72769238458 ps
CPU time 147.25 seconds
Started Feb 07 02:09:01 PM PST 24
Finished Feb 07 02:11:29 PM PST 24
Peak memory 214644 kb
Host smart-fd8686e5-23f9-4091-ba27-4734c9f8ff87
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212941308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.4212941308
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.3916346242
Short name T237
Test name
Test status
Simulation time 13780312816 ps
CPU time 144.5 seconds
Started Feb 07 02:09:02 PM PST 24
Finished Feb 07 02:11:27 PM PST 24
Peak memory 202256 kb
Host smart-61a5ae30-d3aa-4387-a0a4-7e1e85405622
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916346242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.3916346242
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.289917345
Short name T795
Test name
Test status
Simulation time 346210488058 ps
CPU time 1181.97 seconds
Started Feb 07 02:08:48 PM PST 24
Finished Feb 07 02:28:31 PM PST 24
Peak memory 372976 kb
Host smart-d59fe5c5-83dc-4160-94cc-784788034bfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289917345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multip
le_keys.289917345
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.4291202178
Short name T141
Test name
Test status
Simulation time 1026932548 ps
CPU time 19.33 seconds
Started Feb 07 02:08:50 PM PST 24
Finished Feb 07 02:09:10 PM PST 24
Peak memory 202060 kb
Host smart-cae5b43c-5255-4307-ba1d-ecc39e242ae9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291202178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.4291202178
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3531183864
Short name T473
Test name
Test status
Simulation time 28760915938 ps
CPU time 323.11 seconds
Started Feb 07 02:08:48 PM PST 24
Finished Feb 07 02:14:12 PM PST 24
Peak memory 202144 kb
Host smart-3cf47da3-568a-4d4b-bf78-6fa3a9532f96
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531183864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.3531183864
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.2255365368
Short name T397
Test name
Test status
Simulation time 342953772 ps
CPU time 5.57 seconds
Started Feb 07 02:09:00 PM PST 24
Finished Feb 07 02:09:06 PM PST 24
Peak memory 202356 kb
Host smart-d46ef161-4167-4b7d-ac32-c02ea39cb430
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255365368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2255365368
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.3152105482
Short name T452
Test name
Test status
Simulation time 27188801524 ps
CPU time 332.22 seconds
Started Feb 07 02:08:59 PM PST 24
Finished Feb 07 02:14:32 PM PST 24
Peak memory 369828 kb
Host smart-7102d0ef-b1e2-433e-b34a-1a76c58f02ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152105482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3152105482
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.994851181
Short name T4
Test name
Test status
Simulation time 3026239865 ps
CPU time 37.39 seconds
Started Feb 07 02:08:48 PM PST 24
Finished Feb 07 02:09:26 PM PST 24
Peak memory 210376 kb
Host smart-677103f2-15f9-4ed0-97f0-747c1a530397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994851181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.994851181
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.428645844
Short name T767
Test name
Test status
Simulation time 89561923669 ps
CPU time 2289.57 seconds
Started Feb 07 02:09:02 PM PST 24
Finished Feb 07 02:47:13 PM PST 24
Peak memory 377652 kb
Host smart-7bf3b6ff-5aca-4871-8fe8-3ffd49d1327a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428645844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_stress_all.428645844
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2830771208
Short name T728
Test name
Test status
Simulation time 6461179201 ps
CPU time 5887.69 seconds
Started Feb 07 02:09:01 PM PST 24
Finished Feb 07 03:47:10 PM PST 24
Peak memory 606604 kb
Host smart-952160bc-e842-45af-8a61-294bffb42bf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2830771208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2830771208
Directory /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2397853079
Short name T315
Test name
Test status
Simulation time 5183562715 ps
CPU time 207.19 seconds
Started Feb 07 02:08:49 PM PST 24
Finished Feb 07 02:12:17 PM PST 24
Peak memory 202180 kb
Host smart-6bc64afb-f97f-437e-b459-e32276e49412
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397853079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.2397853079
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3569365279
Short name T538
Test name
Test status
Simulation time 735093520 ps
CPU time 43.31 seconds
Started Feb 07 02:08:48 PM PST 24
Finished Feb 07 02:09:32 PM PST 24
Peak memory 258368 kb
Host smart-8026c2ad-23aa-4f4c-9313-06bf566f0511
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569365279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3569365279
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3637417158
Short name T19
Test name
Test status
Simulation time 11452331344 ps
CPU time 927.1 seconds
Started Feb 07 02:09:13 PM PST 24
Finished Feb 07 02:24:41 PM PST 24
Peak memory 378172 kb
Host smart-5e556c07-3619-4b35-b82f-12dd5d8241e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637417158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.3637417158
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.1522873872
Short name T938
Test name
Test status
Simulation time 15147379 ps
CPU time 0.67 seconds
Started Feb 07 02:09:11 PM PST 24
Finished Feb 07 02:09:12 PM PST 24
Peak memory 201848 kb
Host smart-6a053791-3a71-4f42-875c-c7c341fad3d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522873872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.1522873872
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.1079882570
Short name T602
Test name
Test status
Simulation time 117333908163 ps
CPU time 1872.44 seconds
Started Feb 07 02:08:59 PM PST 24
Finished Feb 07 02:40:12 PM PST 24
Peak memory 202232 kb
Host smart-8faadb36-c33d-4d11-a73e-51cc7f8ff462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079882570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.1079882570
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.464797125
Short name T870
Test name
Test status
Simulation time 20641684515 ps
CPU time 236.85 seconds
Started Feb 07 02:09:12 PM PST 24
Finished Feb 07 02:13:10 PM PST 24
Peak memory 202236 kb
Host smart-de29b7df-40cc-41c8-a79e-96dc853d0504
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464797125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc
alation.464797125
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3466639188
Short name T839
Test name
Test status
Simulation time 797704711 ps
CPU time 128.15 seconds
Started Feb 07 02:09:01 PM PST 24
Finished Feb 07 02:11:10 PM PST 24
Peak memory 346240 kb
Host smart-689c7d2a-33df-4ba5-86e1-7196ef1f90a5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466639188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3466639188
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2800150822
Short name T504
Test name
Test status
Simulation time 13568848591 ps
CPU time 79.3 seconds
Started Feb 07 02:09:07 PM PST 24
Finished Feb 07 02:10:27 PM PST 24
Peak memory 210644 kb
Host smart-d1d3dd04-70d5-4990-a5b7-55f6c9338847
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800150822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.2800150822
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.235926978
Short name T322
Test name
Test status
Simulation time 4113767017 ps
CPU time 125.48 seconds
Started Feb 07 02:09:13 PM PST 24
Finished Feb 07 02:11:19 PM PST 24
Peak memory 202220 kb
Host smart-044f6227-053c-44c4-9963-f7bf42382a48
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235926978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_mem_walk.235926978
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.2855319357
Short name T926
Test name
Test status
Simulation time 15351958662 ps
CPU time 789.91 seconds
Started Feb 07 02:09:01 PM PST 24
Finished Feb 07 02:22:12 PM PST 24
Peak memory 353216 kb
Host smart-00828504-aece-4088-9d7f-f1b84d433478
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855319357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.2855319357
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.4136584348
Short name T471
Test name
Test status
Simulation time 727910320 ps
CPU time 39.45 seconds
Started Feb 07 02:08:59 PM PST 24
Finished Feb 07 02:09:40 PM PST 24
Peak memory 279784 kb
Host smart-e4803c19-ea37-435c-9b2c-32f98e3b14ab
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136584348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.4136584348
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1602363931
Short name T360
Test name
Test status
Simulation time 57741843780 ps
CPU time 329.56 seconds
Started Feb 07 02:09:07 PM PST 24
Finished Feb 07 02:14:37 PM PST 24
Peak memory 202212 kb
Host smart-9db5382c-56bd-4ff3-9696-3128c4d803ef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602363931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.1602363931
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.1083122428
Short name T869
Test name
Test status
Simulation time 434238989 ps
CPU time 6.22 seconds
Started Feb 07 02:09:15 PM PST 24
Finished Feb 07 02:09:22 PM PST 24
Peak memory 202364 kb
Host smart-ca42b1cd-8d89-4493-bb00-902feeaa00b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083122428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1083122428
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.662298893
Short name T361
Test name
Test status
Simulation time 9631985541 ps
CPU time 556.54 seconds
Started Feb 07 02:09:12 PM PST 24
Finished Feb 07 02:18:29 PM PST 24
Peak memory 343224 kb
Host smart-822661dd-1a45-4a28-b342-5751542bf5d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662298893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.662298893
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.2683415154
Short name T677
Test name
Test status
Simulation time 7080158291 ps
CPU time 22.26 seconds
Started Feb 07 02:09:00 PM PST 24
Finished Feb 07 02:09:23 PM PST 24
Peak memory 210416 kb
Host smart-8db50d21-4b52-427d-9760-1b975aa4ab7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683415154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2683415154
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4020467709
Short name T554
Test name
Test status
Simulation time 789366173 ps
CPU time 2545.62 seconds
Started Feb 07 02:09:14 PM PST 24
Finished Feb 07 02:51:40 PM PST 24
Peak memory 431564 kb
Host smart-6c4289b6-a77a-44d7-8860-96186444c2aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4020467709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.4020467709
Directory /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2138569128
Short name T574
Test name
Test status
Simulation time 8485360637 ps
CPU time 302.52 seconds
Started Feb 07 02:09:02 PM PST 24
Finished Feb 07 02:14:06 PM PST 24
Peak memory 202296 kb
Host smart-e95af2f4-3a19-4752-9447-a481e1f87009
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138569128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.2138569128
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1791252519
Short name T654
Test name
Test status
Simulation time 2756190086 ps
CPU time 32.5 seconds
Started Feb 07 02:09:06 PM PST 24
Finished Feb 07 02:09:39 PM PST 24
Peak memory 234932 kb
Host smart-60c26e2a-cb74-4d2e-a4da-42b54758fd4f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791252519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.1791252519
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1070930931
Short name T435
Test name
Test status
Simulation time 7459718700 ps
CPU time 1086.12 seconds
Started Feb 07 02:09:18 PM PST 24
Finished Feb 07 02:27:25 PM PST 24
Peak memory 376052 kb
Host smart-7a8b53a3-503c-426a-89a8-5aa0fc4ea8e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070930931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.1070930931
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.3953593192
Short name T765
Test name
Test status
Simulation time 11744024 ps
CPU time 0.63 seconds
Started Feb 07 02:09:31 PM PST 24
Finished Feb 07 02:09:36 PM PST 24
Peak memory 201836 kb
Host smart-c4ea57b7-17b2-4b9a-8c63-ad7cea12c960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953593192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.3953593192
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3578298379
Short name T624
Test name
Test status
Simulation time 33800113472 ps
CPU time 713.51 seconds
Started Feb 07 02:09:12 PM PST 24
Finished Feb 07 02:21:06 PM PST 24
Peak memory 202360 kb
Host smart-d5834feb-4f6f-4040-828d-1134eb49eb00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578298379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3578298379
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.2124511569
Short name T804
Test name
Test status
Simulation time 20275077942 ps
CPU time 205.75 seconds
Started Feb 07 02:09:28 PM PST 24
Finished Feb 07 02:12:56 PM PST 24
Peak memory 210464 kb
Host smart-12bd0344-e7b8-4ee5-bb98-dc0635a5db8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124511569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.2124511569
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.339942759
Short name T270
Test name
Test status
Simulation time 1486759636 ps
CPU time 61.48 seconds
Started Feb 07 02:09:17 PM PST 24
Finished Feb 07 02:10:19 PM PST 24
Peak memory 301220 kb
Host smart-12b9b316-cad8-4655-a3d3-99cfc854872d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339942759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sram_ctrl_max_throughput.339942759
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.4077477848
Short name T81
Test name
Test status
Simulation time 9443463119 ps
CPU time 79.55 seconds
Started Feb 07 02:09:18 PM PST 24
Finished Feb 07 02:10:38 PM PST 24
Peak memory 211308 kb
Host smart-b5bf1f10-771c-4f65-824f-2682c7e1ef01
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077477848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.4077477848
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1553183691
Short name T650
Test name
Test status
Simulation time 15761567173 ps
CPU time 244.92 seconds
Started Feb 07 02:09:28 PM PST 24
Finished Feb 07 02:13:35 PM PST 24
Peak memory 202308 kb
Host smart-711f565a-5b1e-4af5-bf50-58dccbaeb254
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553183691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1553183691
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.3932075612
Short name T6
Test name
Test status
Simulation time 4610823231 ps
CPU time 210.95 seconds
Started Feb 07 02:09:13 PM PST 24
Finished Feb 07 02:12:45 PM PST 24
Peak memory 347984 kb
Host smart-b7a5a2b1-4fb8-4d8d-95db-da625d4f7463
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932075612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.3932075612
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.2010117693
Short name T408
Test name
Test status
Simulation time 2130694896 ps
CPU time 9.81 seconds
Started Feb 07 02:09:12 PM PST 24
Finished Feb 07 02:09:23 PM PST 24
Peak memory 202060 kb
Host smart-027439b7-9770-476c-bbb7-ec3c97223c18
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010117693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.2010117693
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2857589247
Short name T375
Test name
Test status
Simulation time 68027169517 ps
CPU time 435.45 seconds
Started Feb 07 02:09:21 PM PST 24
Finished Feb 07 02:16:37 PM PST 24
Peak memory 202140 kb
Host smart-5bde7713-e680-45b9-bb1f-5afae3d215f4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857589247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.2857589247
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.711923428
Short name T569
Test name
Test status
Simulation time 1540942910 ps
CPU time 6.78 seconds
Started Feb 07 02:09:23 PM PST 24
Finished Feb 07 02:09:30 PM PST 24
Peak memory 202408 kb
Host smart-bcbbe57e-3072-4448-b59d-9217dad7282f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711923428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.711923428
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.532491471
Short name T957
Test name
Test status
Simulation time 6151567317 ps
CPU time 398.58 seconds
Started Feb 07 02:09:21 PM PST 24
Finished Feb 07 02:16:01 PM PST 24
Peak memory 347364 kb
Host smart-450c797f-a884-4cdd-ab7d-06da1ca072d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532491471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.532491471
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.3613210017
Short name T226
Test name
Test status
Simulation time 1031683699 ps
CPU time 25.36 seconds
Started Feb 07 02:09:11 PM PST 24
Finished Feb 07 02:09:37 PM PST 24
Peak memory 202076 kb
Host smart-00d9bf9d-66b7-43ad-a112-914b1bd83110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613210017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3613210017
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.2932807420
Short name T733
Test name
Test status
Simulation time 105082005734 ps
CPU time 1100.87 seconds
Started Feb 07 02:09:23 PM PST 24
Finished Feb 07 02:27:45 PM PST 24
Peak memory 374920 kb
Host smart-011d3a39-ae5d-4205-a68c-7b2872767aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932807420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.2932807420
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2113889254
Short name T34
Test name
Test status
Simulation time 3323123982 ps
CPU time 2758.64 seconds
Started Feb 07 02:09:28 PM PST 24
Finished Feb 07 02:55:29 PM PST 24
Peak memory 619236 kb
Host smart-28e289ce-01ef-46d5-8dc6-98706b29cf5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2113889254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2113889254
Directory /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2210165501
Short name T520
Test name
Test status
Simulation time 18377765051 ps
CPU time 368.72 seconds
Started Feb 07 02:09:12 PM PST 24
Finished Feb 07 02:15:22 PM PST 24
Peak memory 202244 kb
Host smart-37d8e91d-08cd-449b-a3f2-d322c300df32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210165501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2210165501
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.335343999
Short name T928
Test name
Test status
Simulation time 1592155377 ps
CPU time 108.08 seconds
Started Feb 07 02:09:20 PM PST 24
Finished Feb 07 02:11:09 PM PST 24
Peak memory 342164 kb
Host smart-809330e4-d8b7-49cb-84e9-685728a47fcd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335343999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.335343999
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4070396415
Short name T562
Test name
Test status
Simulation time 7775637353 ps
CPU time 744.13 seconds
Started Feb 07 02:09:29 PM PST 24
Finished Feb 07 02:21:58 PM PST 24
Peak memory 375984 kb
Host smart-7d0a17a7-b403-4359-9939-a05421b0b70f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070396415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.4070396415
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.3098697736
Short name T731
Test name
Test status
Simulation time 47405047 ps
CPU time 0.63 seconds
Started Feb 07 02:09:30 PM PST 24
Finished Feb 07 02:09:36 PM PST 24
Peak memory 201840 kb
Host smart-7c1d5d8c-116c-43e9-a0f7-016660016cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098697736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.3098697736
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.1079461050
Short name T692
Test name
Test status
Simulation time 12181089683 ps
CPU time 836.12 seconds
Started Feb 07 02:09:29 PM PST 24
Finished Feb 07 02:23:26 PM PST 24
Peak memory 202144 kb
Host smart-beda80a4-a598-4a54-bee8-2396e9657d3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079461050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.1079461050
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.3867874678
Short name T9
Test name
Test status
Simulation time 11224639157 ps
CPU time 31.97 seconds
Started Feb 07 02:09:34 PM PST 24
Finished Feb 07 02:10:08 PM PST 24
Peak memory 210312 kb
Host smart-00c65e6d-1e50-41c5-9604-5f752fc467a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867874678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.3867874678
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.177600622
Short name T631
Test name
Test status
Simulation time 1586214306 ps
CPU time 104.81 seconds
Started Feb 07 02:09:28 PM PST 24
Finished Feb 07 02:11:15 PM PST 24
Peak memory 327172 kb
Host smart-da1ab582-521b-452b-b620-8e5fcf29c07a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177600622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.sram_ctrl_max_throughput.177600622
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3528177596
Short name T84
Test name
Test status
Simulation time 2707420075 ps
CPU time 71.25 seconds
Started Feb 07 02:09:34 PM PST 24
Finished Feb 07 02:10:47 PM PST 24
Peak memory 218480 kb
Host smart-b0d93578-3bde-4ffc-a9fc-eef94f338d92
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528177596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.3528177596
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.704549184
Short name T780
Test name
Test status
Simulation time 8047869455 ps
CPU time 247.37 seconds
Started Feb 07 02:09:29 PM PST 24
Finished Feb 07 02:13:38 PM PST 24
Peak memory 202668 kb
Host smart-b3747923-7083-4cce-9a9c-a03eed386b2d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704549184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl
_mem_walk.704549184
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.680556028
Short name T324
Test name
Test status
Simulation time 25351256013 ps
CPU time 1274.36 seconds
Started Feb 07 02:09:19 PM PST 24
Finished Feb 07 02:30:35 PM PST 24
Peak memory 371752 kb
Host smart-c3395d7e-a5d1-46ae-beac-89921bc580fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680556028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multip
le_keys.680556028
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.805377812
Short name T810
Test name
Test status
Simulation time 5161708595 ps
CPU time 25.88 seconds
Started Feb 07 02:09:18 PM PST 24
Finished Feb 07 02:09:45 PM PST 24
Peak memory 202156 kb
Host smart-14f5f4ae-693f-40dd-ba7a-1ede36291685
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805377812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s
ram_ctrl_partial_access.805377812
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1089764674
Short name T438
Test name
Test status
Simulation time 67136609255 ps
CPU time 429.22 seconds
Started Feb 07 02:09:30 PM PST 24
Finished Feb 07 02:16:45 PM PST 24
Peak memory 202172 kb
Host smart-484a6e58-9d08-4bdb-b521-9dab8f8f6bad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089764674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.1089764674
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.3293570612
Short name T215
Test name
Test status
Simulation time 1435733193 ps
CPU time 6.01 seconds
Started Feb 07 02:09:34 PM PST 24
Finished Feb 07 02:09:42 PM PST 24
Peak memory 202360 kb
Host smart-bd230909-f1d6-45ed-a099-9c02f6461fb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293570612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.3293570612
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.336267733
Short name T678
Test name
Test status
Simulation time 43713787747 ps
CPU time 612.24 seconds
Started Feb 07 02:09:34 PM PST 24
Finished Feb 07 02:19:49 PM PST 24
Peak memory 380024 kb
Host smart-47e8a0c2-4cf0-4a79-96b5-05bb7ac9a942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336267733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.336267733
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.3107165023
Short name T110
Test name
Test status
Simulation time 26745485395 ps
CPU time 32.96 seconds
Started Feb 07 02:09:31 PM PST 24
Finished Feb 07 02:10:09 PM PST 24
Peak memory 202112 kb
Host smart-77043151-0569-49d0-a06e-c2f9b468b235
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107165023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3107165023
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1985033809
Short name T221
Test name
Test status
Simulation time 1761259815 ps
CPU time 2406.28 seconds
Started Feb 07 02:09:33 PM PST 24
Finished Feb 07 02:49:42 PM PST 24
Peak memory 629872 kb
Host smart-151305e4-9680-4231-a91f-2d0688110a7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1985033809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1985033809
Directory /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.952733972
Short name T273
Test name
Test status
Simulation time 19316244011 ps
CPU time 365.18 seconds
Started Feb 07 02:09:19 PM PST 24
Finished Feb 07 02:15:25 PM PST 24
Peak memory 202244 kb
Host smart-a65c527b-4935-45d9-8180-b3aeb4eeae5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952733972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_stress_pipeline.952733972
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1609701457
Short name T391
Test name
Test status
Simulation time 2797605975 ps
CPU time 37.74 seconds
Started Feb 07 02:09:34 PM PST 24
Finished Feb 07 02:10:14 PM PST 24
Peak memory 251240 kb
Host smart-019e6eff-da38-4223-ada8-2c6578b67364
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609701457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1609701457
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3931877448
Short name T578
Test name
Test status
Simulation time 23568116448 ps
CPU time 792.72 seconds
Started Feb 07 02:09:47 PM PST 24
Finished Feb 07 02:23:05 PM PST 24
Peak memory 367820 kb
Host smart-629e78c5-8178-4c8d-bc63-fd786b32df71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931877448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.3931877448
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.3056968148
Short name T548
Test name
Test status
Simulation time 13902996 ps
CPU time 0.63 seconds
Started Feb 07 02:09:56 PM PST 24
Finished Feb 07 02:09:58 PM PST 24
Peak memory 201876 kb
Host smart-0040482a-252f-4fd9-8800-57f3e3a509dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056968148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.3056968148
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.3373416794
Short name T664
Test name
Test status
Simulation time 424866902665 ps
CPU time 2664.79 seconds
Started Feb 07 02:09:37 PM PST 24
Finished Feb 07 02:54:05 PM PST 24
Peak memory 202264 kb
Host smart-16bf7ce1-a162-4353-961c-c30bdb134b17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373416794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.3373416794
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.2883939588
Short name T526
Test name
Test status
Simulation time 75336242744 ps
CPU time 1301.28 seconds
Started Feb 07 02:09:46 PM PST 24
Finished Feb 07 02:31:29 PM PST 24
Peak memory 379028 kb
Host smart-cba11ff4-1d54-47fe-bd93-9116a6744f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883939588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.2883939588
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.3621882585
Short name T8
Test name
Test status
Simulation time 66843963103 ps
CPU time 384.05 seconds
Started Feb 07 02:09:46 PM PST 24
Finished Feb 07 02:16:12 PM PST 24
Peak memory 210420 kb
Host smart-984eb1a1-113b-4958-94f0-b84a9b2b2de7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621882585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.3621882585
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.3000012569
Short name T385
Test name
Test status
Simulation time 987162342 ps
CPU time 63.38 seconds
Started Feb 07 02:09:39 PM PST 24
Finished Feb 07 02:10:44 PM PST 24
Peak memory 285032 kb
Host smart-8ee1b63c-fbd8-448f-a753-49cb28de6da5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000012569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.3000012569
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2966720473
Short name T893
Test name
Test status
Simulation time 8706495519 ps
CPU time 147.84 seconds
Started Feb 07 02:09:51 PM PST 24
Finished Feb 07 02:12:22 PM PST 24
Peak memory 210344 kb
Host smart-443d41ae-a708-4bac-afb0-4da758c4f9cd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966720473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.2966720473
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.1613958895
Short name T487
Test name
Test status
Simulation time 43043275023 ps
CPU time 159.16 seconds
Started Feb 07 02:09:47 PM PST 24
Finished Feb 07 02:12:32 PM PST 24
Peak memory 202192 kb
Host smart-47aa1678-14ec-425c-8451-4cd9516e0dd8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613958895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.1613958895
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.1005274133
Short name T218
Test name
Test status
Simulation time 101844546335 ps
CPU time 1300.85 seconds
Started Feb 07 02:09:40 PM PST 24
Finished Feb 07 02:31:23 PM PST 24
Peak memory 378300 kb
Host smart-f2c4c4be-bb8c-48f5-9f81-d4fc9b408d1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005274133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.1005274133
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.3752784476
Short name T960
Test name
Test status
Simulation time 972413860 ps
CPU time 44.08 seconds
Started Feb 07 02:09:37 PM PST 24
Finished Feb 07 02:10:24 PM PST 24
Peak memory 202100 kb
Host smart-46eb09d0-3002-456a-9313-69b8dd6ee4fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752784476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.3752784476
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4041428886
Short name T133
Test name
Test status
Simulation time 82423616596 ps
CPU time 453.73 seconds
Started Feb 07 02:09:38 PM PST 24
Finished Feb 07 02:17:15 PM PST 24
Peak memory 202120 kb
Host smart-a254dd7a-e5f9-4348-9289-1ce3a3fdcf2a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041428886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.4041428886
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.2439166491
Short name T38
Test name
Test status
Simulation time 356182138 ps
CPU time 13.05 seconds
Started Feb 07 02:09:46 PM PST 24
Finished Feb 07 02:10:01 PM PST 24
Peak memory 202408 kb
Host smart-54b4a5c2-690e-44ac-96f9-9f5a93c15d8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439166491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2439166491
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.1904410263
Short name T947
Test name
Test status
Simulation time 29315650751 ps
CPU time 665.14 seconds
Started Feb 07 02:09:47 PM PST 24
Finished Feb 07 02:20:58 PM PST 24
Peak memory 362660 kb
Host smart-da6a3622-93f1-42d8-8d54-b3bf2c8dd811
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904410263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1904410263
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.2103440854
Short name T684
Test name
Test status
Simulation time 1050094156 ps
CPU time 53.25 seconds
Started Feb 07 02:09:40 PM PST 24
Finished Feb 07 02:10:35 PM PST 24
Peak memory 298392 kb
Host smart-1c00891e-c8b3-47a7-a4e1-0f5c6fe70689
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103440854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2103440854
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3942784170
Short name T359
Test name
Test status
Simulation time 1395347808 ps
CPU time 1383.73 seconds
Started Feb 07 02:09:46 PM PST 24
Finished Feb 07 02:32:52 PM PST 24
Peak memory 434628 kb
Host smart-6718b354-d16a-47c2-bda8-8552d8dd8b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3942784170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3942784170
Directory /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2628584320
Short name T945
Test name
Test status
Simulation time 5052093153 ps
CPU time 341.72 seconds
Started Feb 07 02:09:37 PM PST 24
Finished Feb 07 02:15:22 PM PST 24
Peak memory 202204 kb
Host smart-d0fd8174-d677-49e0-baf9-d9901a8be8bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628584320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.2628584320
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2815534375
Short name T815
Test name
Test status
Simulation time 771421994 ps
CPU time 76.4 seconds
Started Feb 07 02:09:40 PM PST 24
Finished Feb 07 02:10:58 PM PST 24
Peak memory 312464 kb
Host smart-88366489-437e-4ff4-acab-a845dba89c4b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815534375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2815534375
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.849820657
Short name T464
Test name
Test status
Simulation time 7124166601 ps
CPU time 888.17 seconds
Started Feb 07 02:00:57 PM PST 24
Finished Feb 07 02:15:46 PM PST 24
Peak memory 379132 kb
Host smart-3eec936c-8c5d-4dde-ad4b-4c84b483b207
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849820657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.sram_ctrl_access_during_key_req.849820657
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.2803601766
Short name T901
Test name
Test status
Simulation time 24018159 ps
CPU time 0.68 seconds
Started Feb 07 02:01:01 PM PST 24
Finished Feb 07 02:01:04 PM PST 24
Peak memory 201820 kb
Host smart-8d46ad6c-dfd7-4a24-baf7-bb899c26476a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803601766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.2803601766
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.3783250090
Short name T511
Test name
Test status
Simulation time 180191140001 ps
CPU time 1247.5 seconds
Started Feb 07 02:00:58 PM PST 24
Finished Feb 07 02:21:47 PM PST 24
Peak memory 202252 kb
Host smart-cf0e7475-db3f-46cd-8511-879913f4f29a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783250090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
3783250090
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.122994760
Short name T126
Test name
Test status
Simulation time 14117718706 ps
CPU time 144.97 seconds
Started Feb 07 02:00:59 PM PST 24
Finished Feb 07 02:03:25 PM PST 24
Peak memory 373968 kb
Host smart-36d422f1-5922-4935-b95c-1065c87933d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122994760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable
.122994760
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.3360792842
Short name T388
Test name
Test status
Simulation time 26931367355 ps
CPU time 142.1 seconds
Started Feb 07 02:00:57 PM PST 24
Finished Feb 07 02:03:20 PM PST 24
Peak memory 211920 kb
Host smart-3cd06fe5-308c-4f92-a66f-4fc9a7cb7a1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360792842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.3360792842
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2534267603
Short name T529
Test name
Test status
Simulation time 794057521 ps
CPU time 128.8 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:03:14 PM PST 24
Peak memory 355408 kb
Host smart-b36ebff9-872e-444e-a015-f3235f3e40e2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534267603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2534267603
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3816797551
Short name T463
Test name
Test status
Simulation time 50550367791 ps
CPU time 171.5 seconds
Started Feb 07 02:01:06 PM PST 24
Finished Feb 07 02:03:59 PM PST 24
Peak memory 211276 kb
Host smart-5dc25615-e9ff-416f-a474-4e9eaa614577
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816797551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.3816797551
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.4179312941
Short name T718
Test name
Test status
Simulation time 14068487569 ps
CPU time 146.62 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:03:32 PM PST 24
Peak memory 202264 kb
Host smart-8be0d5d4-794c-4268-86d9-4cdae4fc76e9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179312941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.4179312941
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.72982529
Short name T736
Test name
Test status
Simulation time 8661091817 ps
CPU time 157.17 seconds
Started Feb 07 02:01:00 PM PST 24
Finished Feb 07 02:03:38 PM PST 24
Peak memory 313748 kb
Host smart-fa52a6ca-dc02-4704-b6f4-9dbd42b6ea49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72982529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple
_keys.72982529
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.2284237517
Short name T401
Test name
Test status
Simulation time 2533515351 ps
CPU time 17.74 seconds
Started Feb 07 02:01:12 PM PST 24
Finished Feb 07 02:01:31 PM PST 24
Peak memory 240516 kb
Host smart-dc5a8b8e-8a67-47a6-995a-8362cc3fb38f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284237517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.2284237517
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1492873297
Short name T47
Test name
Test status
Simulation time 76389184982 ps
CPU time 501.42 seconds
Started Feb 07 02:00:58 PM PST 24
Finished Feb 07 02:09:20 PM PST 24
Peak memory 202164 kb
Host smart-ae83e360-d992-4ded-9b81-43a81def1da9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492873297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.1492873297
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.200159035
Short name T770
Test name
Test status
Simulation time 351566136 ps
CPU time 13.95 seconds
Started Feb 07 02:00:59 PM PST 24
Finished Feb 07 02:01:14 PM PST 24
Peak memory 202360 kb
Host smart-bb861b87-8a7a-4126-a181-b51678cbb706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200159035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.200159035
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.1785368720
Short name T508
Test name
Test status
Simulation time 24760613089 ps
CPU time 267.19 seconds
Started Feb 07 02:00:58 PM PST 24
Finished Feb 07 02:05:26 PM PST 24
Peak memory 347416 kb
Host smart-9198f7cd-3d8f-4da9-8008-bdc604ae7387
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785368720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1785368720
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.2623485010
Short name T648
Test name
Test status
Simulation time 9607033660 ps
CPU time 27.04 seconds
Started Feb 07 02:01:01 PM PST 24
Finished Feb 07 02:01:30 PM PST 24
Peak memory 202108 kb
Host smart-86d1ac86-3a4a-4b11-b46d-5505848cb044
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623485010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.2623485010
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.2051506518
Short name T802
Test name
Test status
Simulation time 209742047099 ps
CPU time 1918.88 seconds
Started Feb 07 02:00:55 PM PST 24
Finished Feb 07 02:32:56 PM PST 24
Peak memory 382188 kb
Host smart-a1e1e78d-d12e-469f-8479-a3350807b743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051506518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.sram_ctrl_stress_all.2051506518
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1687180715
Short name T341
Test name
Test status
Simulation time 2710879972 ps
CPU time 3525.77 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:59:52 PM PST 24
Peak memory 489604 kb
Host smart-599f056c-9b6a-46da-a9c9-2ac876b09b43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1687180715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1687180715
Directory /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3292421791
Short name T667
Test name
Test status
Simulation time 8852534899 ps
CPU time 292.3 seconds
Started Feb 07 02:01:02 PM PST 24
Finished Feb 07 02:05:56 PM PST 24
Peak memory 202196 kb
Host smart-a50ea0c1-449c-4681-a550-463fc65d140d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292421791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.3292421791
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.466601184
Short name T757
Test name
Test status
Simulation time 2814983663 ps
CPU time 28.1 seconds
Started Feb 07 02:00:59 PM PST 24
Finished Feb 07 02:01:27 PM PST 24
Peak memory 215012 kb
Host smart-c9985fff-7f69-4aba-834b-508e8468e4c7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466601184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_throughput_w_partial_write.466601184
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2068867540
Short name T807
Test name
Test status
Simulation time 12001988054 ps
CPU time 245.24 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:05:12 PM PST 24
Peak memory 373812 kb
Host smart-a3c50281-da80-4424-aec2-e96b73faa1c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068867540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.2068867540
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.3979496730
Short name T872
Test name
Test status
Simulation time 39774738 ps
CPU time 0.65 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:01:05 PM PST 24
Peak memory 201380 kb
Host smart-b6921d59-8a3f-42b7-b182-674ea1da16bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979496730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.3979496730
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.3735790273
Short name T930
Test name
Test status
Simulation time 15059850784 ps
CPU time 990.25 seconds
Started Feb 07 02:01:12 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 202248 kb
Host smart-556ebdbc-05c9-4716-8436-b95d1ff3e20a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735790273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
3735790273
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.3459186082
Short name T642
Test name
Test status
Simulation time 119775859890 ps
CPU time 1274.55 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:22:21 PM PST 24
Peak memory 372896 kb
Host smart-b64baac1-2a65-4948-8ba4-efa20a9437db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459186082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.3459186082
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.2445698347
Short name T465
Test name
Test status
Simulation time 2632184103 ps
CPU time 31 seconds
Started Feb 07 02:01:00 PM PST 24
Finished Feb 07 02:01:32 PM PST 24
Peak memory 235048 kb
Host smart-a2fb9993-a7f0-41fc-8599-cc04b22f2bc2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445698347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.2445698347
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4247123507
Short name T587
Test name
Test status
Simulation time 11842635283 ps
CPU time 79.9 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:02:26 PM PST 24
Peak memory 211228 kb
Host smart-67d68d69-4e45-4c8e-8e5b-ffff2747dbe1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247123507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.4247123507
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.2635435725
Short name T764
Test name
Test status
Simulation time 14049981524 ps
CPU time 150.92 seconds
Started Feb 07 02:00:58 PM PST 24
Finished Feb 07 02:03:30 PM PST 24
Peak memory 202280 kb
Host smart-0903d148-79b0-416e-8b93-4f5ac10c9b55
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635435725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.2635435725
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.2807572194
Short name T932
Test name
Test status
Simulation time 27707026533 ps
CPU time 452.87 seconds
Started Feb 07 02:01:06 PM PST 24
Finished Feb 07 02:08:40 PM PST 24
Peak memory 378072 kb
Host smart-943bc9e2-073a-4978-9b60-209fe2796050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807572194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.2807572194
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.3231239168
Short name T833
Test name
Test status
Simulation time 1513545159 ps
CPU time 13.74 seconds
Started Feb 07 02:01:07 PM PST 24
Finished Feb 07 02:01:21 PM PST 24
Peak memory 202104 kb
Host smart-da8519c7-05b2-47f7-abe0-6b4f728c7bda
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231239168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.3231239168
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.155381266
Short name T614
Test name
Test status
Simulation time 18153381645 ps
CPU time 366.3 seconds
Started Feb 07 02:00:59 PM PST 24
Finished Feb 07 02:07:06 PM PST 24
Peak memory 202176 kb
Host smart-bf1f7bb2-f072-4ced-8684-d2807068ef9c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155381266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.sram_ctrl_partial_access_b2b.155381266
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.1298706504
Short name T730
Test name
Test status
Simulation time 726904020 ps
CPU time 5.9 seconds
Started Feb 07 02:01:10 PM PST 24
Finished Feb 07 02:01:17 PM PST 24
Peak memory 202320 kb
Host smart-ce662e48-7f8e-423b-9bce-bb05cbd1fc4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298706504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1298706504
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3952019394
Short name T128
Test name
Test status
Simulation time 62687740441 ps
CPU time 594.22 seconds
Started Feb 07 02:01:12 PM PST 24
Finished Feb 07 02:11:07 PM PST 24
Peak memory 372948 kb
Host smart-2d907fed-9ef0-4f2f-af13-88e640578338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952019394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3952019394
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.1835954039
Short name T265
Test name
Test status
Simulation time 358596993 ps
CPU time 14.13 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:21 PM PST 24
Peak memory 202124 kb
Host smart-bcaff444-f460-4822-88db-6f11a1c579e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835954039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1835954039
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.888427874
Short name T482
Test name
Test status
Simulation time 813503893 ps
CPU time 6934.74 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 03:56:41 PM PST 24
Peak memory 733936 kb
Host smart-15fe3a4b-54dd-450f-b15e-4bbfc20c3147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=888427874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.888427874
Directory /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.4061643873
Short name T925
Test name
Test status
Simulation time 3262175384 ps
CPU time 260.66 seconds
Started Feb 07 02:01:09 PM PST 24
Finished Feb 07 02:05:30 PM PST 24
Peak memory 202220 kb
Host smart-87c98290-fbec-4964-a365-8142bd415056
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061643873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.4061643873
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1960217617
Short name T335
Test name
Test status
Simulation time 771178223 ps
CPU time 65.51 seconds
Started Feb 07 02:01:07 PM PST 24
Finished Feb 07 02:02:14 PM PST 24
Peak memory 311964 kb
Host smart-293e4101-4efc-4a15-bb74-b7bb3e746304
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960217617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1960217617
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.953738977
Short name T801
Test name
Test status
Simulation time 37421928176 ps
CPU time 1734.63 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:30:12 PM PST 24
Peak memory 380528 kb
Host smart-ab871ca1-830e-42fd-8112-ab07a62d4146
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953738977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 7.sram_ctrl_access_during_key_req.953738977
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.3854018224
Short name T941
Test name
Test status
Simulation time 37922147 ps
CPU time 0.66 seconds
Started Feb 07 02:01:02 PM PST 24
Finished Feb 07 02:01:04 PM PST 24
Peak memory 201836 kb
Host smart-a18f36bc-a34c-4c5c-85a9-5f9709e79ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854018224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.3854018224
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.2860362261
Short name T231
Test name
Test status
Simulation time 358968416115 ps
CPU time 3051.75 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:51:58 PM PST 24
Peak memory 202216 kb
Host smart-fdea8189-fbec-42e9-a095-596e9cb828f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860362261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
2860362261
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.615232361
Short name T646
Test name
Test status
Simulation time 763414470 ps
CPU time 65.7 seconds
Started Feb 07 02:01:03 PM PST 24
Finished Feb 07 02:02:10 PM PST 24
Peak memory 302344 kb
Host smart-1b0de23a-b3e3-400e-98c6-a203f689636e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615232361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.sram_ctrl_max_throughput.615232361
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2827309110
Short name T661
Test name
Test status
Simulation time 1648246592 ps
CPU time 127.59 seconds
Started Feb 07 02:01:11 PM PST 24
Finished Feb 07 02:03:20 PM PST 24
Peak memory 211316 kb
Host smart-ac97d0ff-c4f3-4370-83a9-03c9ebcfe532
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827309110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.2827309110
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.2003424485
Short name T540
Test name
Test status
Simulation time 28680516950 ps
CPU time 153 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:03:38 PM PST 24
Peak memory 202164 kb
Host smart-439df8d4-1adb-432c-9b74-9590e6bb00b8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003424485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.2003424485
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.3274657648
Short name T637
Test name
Test status
Simulation time 22983900013 ps
CPU time 1017.97 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:18:03 PM PST 24
Peak memory 377028 kb
Host smart-1b84cd6e-3d14-473e-8ae5-f0b8a46eb5a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274657648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.3274657648
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.3313655650
Short name T416
Test name
Test status
Simulation time 958104640 ps
CPU time 29.24 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:01:46 PM PST 24
Peak memory 258332 kb
Host smart-ee438b03-6b4a-4390-bd09-9c904bda2c33
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313655650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.3313655650
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1914641695
Short name T286
Test name
Test status
Simulation time 77564122125 ps
CPU time 310.12 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:06:15 PM PST 24
Peak memory 202152 kb
Host smart-3432b116-80ea-436a-ae79-5c1bfdb80bd7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914641695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.1914641695
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.1211550298
Short name T725
Test name
Test status
Simulation time 353494980 ps
CPU time 5.62 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:12 PM PST 24
Peak memory 202372 kb
Host smart-aaf48f73-f8c4-4adc-a4e8-dcdd304c445f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211550298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1211550298
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.2926683897
Short name T124
Test name
Test status
Simulation time 16079107601 ps
CPU time 1252.1 seconds
Started Feb 07 02:01:09 PM PST 24
Finished Feb 07 02:22:02 PM PST 24
Peak memory 372956 kb
Host smart-3b06deb1-5508-4587-9197-c7b95243c14f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926683897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2926683897
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.50045077
Short name T225
Test name
Test status
Simulation time 931198021 ps
CPU time 19.5 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:26 PM PST 24
Peak memory 202072 kb
Host smart-db5b0422-59f5-40c2-9189-d03dc7ea236e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50045077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.50045077
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3832341014
Short name T577
Test name
Test status
Simulation time 3577104327 ps
CPU time 1464.54 seconds
Started Feb 07 02:01:04 PM PST 24
Finished Feb 07 02:25:30 PM PST 24
Peak memory 506476 kb
Host smart-5578539b-e2d5-4916-82c7-a98f39c164f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3832341014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3832341014
Directory /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3612016264
Short name T547
Test name
Test status
Simulation time 10880027716 ps
CPU time 199.04 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:04:25 PM PST 24
Peak memory 202212 kb
Host smart-01ac0180-55c8-4f4d-9e5e-968d5161321d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612016264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.3612016264
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1342055617
Short name T793
Test name
Test status
Simulation time 2989137001 ps
CPU time 44.5 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:51 PM PST 24
Peak memory 271712 kb
Host smart-7a67825b-a826-4ab8-bcb5-7659362a9b44
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342055617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1342055617
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.93350266
Short name T615
Test name
Test status
Simulation time 9642797674 ps
CPU time 1197.72 seconds
Started Feb 07 02:01:08 PM PST 24
Finished Feb 07 02:21:07 PM PST 24
Peak memory 377484 kb
Host smart-67e31a1e-b60b-449e-8ae6-7e5c2d985e75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93350266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.sram_ctrl_access_during_key_req.93350266
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.2589717781
Short name T410
Test name
Test status
Simulation time 25147602 ps
CPU time 0.64 seconds
Started Feb 07 02:01:11 PM PST 24
Finished Feb 07 02:01:13 PM PST 24
Peak memory 201468 kb
Host smart-71fadf06-04e8-4322-8f77-0dd0fab61344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589717781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.2589717781
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.2084384802
Short name T11
Test name
Test status
Simulation time 148312824251 ps
CPU time 832.66 seconds
Started Feb 07 02:01:06 PM PST 24
Finished Feb 07 02:15:00 PM PST 24
Peak memory 202196 kb
Host smart-c0d47fff-52c6-42f6-b476-4c0b8457361c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084384802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
2084384802
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.2481472053
Short name T522
Test name
Test status
Simulation time 48056161434 ps
CPU time 1418.94 seconds
Started Feb 07 02:01:07 PM PST 24
Finished Feb 07 02:24:47 PM PST 24
Peak memory 375996 kb
Host smart-ba7e694e-ba19-4891-bc13-6c6494cf04ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481472053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.2481472053
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.1474155230
Short name T890
Test name
Test status
Simulation time 4312938053 ps
CPU time 69.84 seconds
Started Feb 07 02:01:00 PM PST 24
Finished Feb 07 02:02:10 PM PST 24
Peak memory 210520 kb
Host smart-656366db-65ae-48ca-973e-cbc057073e4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474155230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc
alation.1474155230
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.2357858911
Short name T296
Test name
Test status
Simulation time 2614586143 ps
CPU time 47.31 seconds
Started Feb 07 02:01:09 PM PST 24
Finished Feb 07 02:01:57 PM PST 24
Peak memory 268652 kb
Host smart-3a5f6176-cfe5-4554-81e7-d7d476502161
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357858911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.2357858911
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.719076550
Short name T402
Test name
Test status
Simulation time 3960425237 ps
CPU time 77.3 seconds
Started Feb 07 02:01:10 PM PST 24
Finished Feb 07 02:02:29 PM PST 24
Peak memory 211368 kb
Host smart-1f5a8528-e536-4910-8b7e-ce103fc9190d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719076550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
sram_ctrl_mem_partial_access.719076550
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.2149411416
Short name T737
Test name
Test status
Simulation time 9614366236 ps
CPU time 247.93 seconds
Started Feb 07 02:01:02 PM PST 24
Finished Feb 07 02:05:11 PM PST 24
Peak memory 202136 kb
Host smart-6ee1cf1a-7b0b-4785-80e3-e43cec35b875
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149411416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.2149411416
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.809977681
Short name T230
Test name
Test status
Simulation time 22335562665 ps
CPU time 1602.82 seconds
Started Feb 07 02:01:06 PM PST 24
Finished Feb 07 02:27:50 PM PST 24
Peak memory 377060 kb
Host smart-8643c1b7-9dab-4f00-a060-038788f42389
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809977681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl
e_keys.809977681
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.2462326071
Short name T333
Test name
Test status
Simulation time 1191624232 ps
CPU time 18.59 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:25 PM PST 24
Peak memory 210272 kb
Host smart-75bfbaa8-6959-46c2-86e5-178a1655d49e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462326071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.2462326071
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1699393088
Short name T282
Test name
Test status
Simulation time 4562674629 ps
CPU time 293.93 seconds
Started Feb 07 02:01:08 PM PST 24
Finished Feb 07 02:06:03 PM PST 24
Peak memory 202180 kb
Host smart-62cc7180-8d25-4a49-9fc0-ec762f067f8f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699393088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.1699393088
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.3970295870
Short name T512
Test name
Test status
Simulation time 358845253 ps
CPU time 5.33 seconds
Started Feb 07 02:01:08 PM PST 24
Finished Feb 07 02:01:14 PM PST 24
Peak memory 202396 kb
Host smart-f0e7bd6e-359f-4265-a807-4a1eda8e2e7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970295870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3970295870
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.2533799827
Short name T735
Test name
Test status
Simulation time 11763147815 ps
CPU time 486.94 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:09:22 PM PST 24
Peak memory 374872 kb
Host smart-eb76cb5a-bcc6-4470-8901-b72b2375a727
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533799827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2533799827
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.1793721238
Short name T392
Test name
Test status
Simulation time 580236510 ps
CPU time 20.22 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:26 PM PST 24
Peak memory 248024 kb
Host smart-436a5747-fd17-4197-a75d-55789d02af57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793721238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1793721238
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.2342035702
Short name T336
Test name
Test status
Simulation time 129614346048 ps
CPU time 4386.48 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 03:14:13 PM PST 24
Peak memory 386256 kb
Host smart-b827974f-0933-4ead-a7f1-0c719440b7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342035702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.2342035702
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.623848255
Short name T45
Test name
Test status
Simulation time 1190976829 ps
CPU time 2937.17 seconds
Started Feb 07 02:01:08 PM PST 24
Finished Feb 07 02:50:06 PM PST 24
Peak memory 453064 kb
Host smart-20061a51-6f80-4d92-b793-617f5a368941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=623848255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.623848255
Directory /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2757702503
Short name T896
Test name
Test status
Simulation time 17568237285 ps
CPU time 337.64 seconds
Started Feb 07 02:01:09 PM PST 24
Finished Feb 07 02:06:48 PM PST 24
Peak memory 202228 kb
Host smart-d074f347-f4fe-4e5d-9225-ab50b5aeacf8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757702503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2757702503
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.52351469
Short name T683
Test name
Test status
Simulation time 1917830129 ps
CPU time 130.23 seconds
Started Feb 07 02:01:07 PM PST 24
Finished Feb 07 02:03:18 PM PST 24
Peak memory 369748 kb
Host smart-eb62e97e-a2cc-4b9c-9921-059642080582
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52351469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.sram_ctrl_throughput_w_partial_write.52351469
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3444741060
Short name T87
Test name
Test status
Simulation time 5113783111 ps
CPU time 164.31 seconds
Started Feb 07 02:01:17 PM PST 24
Finished Feb 07 02:04:02 PM PST 24
Peak memory 284240 kb
Host smart-3170fbb5-04dc-4e68-b469-24f5a18a8566
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444741060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.3444741060
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1572492367
Short name T592
Test name
Test status
Simulation time 19207510 ps
CPU time 0.66 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:01:16 PM PST 24
Peak memory 201464 kb
Host smart-14c132cc-a874-4ad8-99b9-a4a1130516bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572492367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1572492367
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.4157753546
Short name T258
Test name
Test status
Simulation time 121568565964 ps
CPU time 2026.32 seconds
Started Feb 07 02:01:14 PM PST 24
Finished Feb 07 02:35:01 PM PST 24
Peak memory 202280 kb
Host smart-6a8b4c6e-b094-4e78-a20e-b726a8367ebf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157753546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
4157753546
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.633281544
Short name T518
Test name
Test status
Simulation time 51320112704 ps
CPU time 870.29 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:15:48 PM PST 24
Peak memory 376492 kb
Host smart-2adafcce-704a-41a2-babf-3b06f37f8284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633281544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable
.633281544
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.2081458295
Short name T281
Test name
Test status
Simulation time 7136984087 ps
CPU time 65.1 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:02:25 PM PST 24
Peak memory 210360 kb
Host smart-f29da9cf-5dd1-466b-897a-baeb9e45aab3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081458295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.2081458295
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.2632373651
Short name T711
Test name
Test status
Simulation time 1421292421 ps
CPU time 167.27 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:04:10 PM PST 24
Peak memory 364756 kb
Host smart-8a6a2215-9b74-4a38-85e2-39c00d65f5a1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632373651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.2632373651
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2755075632
Short name T892
Test name
Test status
Simulation time 4419099872 ps
CPU time 144.76 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:03:45 PM PST 24
Peak memory 214716 kb
Host smart-59ebce8e-95b9-4d02-bde0-93f30d0477c7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755075632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.2755075632
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.2739182090
Short name T632
Test name
Test status
Simulation time 137733116939 ps
CPU time 176.34 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:04:19 PM PST 24
Peak memory 202380 kb
Host smart-57534617-6999-45d2-b1e7-6d45b4aeb9b8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739182090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.2739182090
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.1807205752
Short name T374
Test name
Test status
Simulation time 11005535535 ps
CPU time 1594.54 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:27:54 PM PST 24
Peak memory 373972 kb
Host smart-39b71012-94b6-40ba-abc4-50356f7f11f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807205752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.1807205752
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.787192027
Short name T942
Test name
Test status
Simulation time 3854982845 ps
CPU time 30.88 seconds
Started Feb 07 02:01:21 PM PST 24
Finished Feb 07 02:01:52 PM PST 24
Peak memory 278688 kb
Host smart-d2eebbb8-c977-4c3b-9f39-4471544828bd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787192027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr
am_ctrl_partial_access.787192027
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2942023101
Short name T317
Test name
Test status
Simulation time 70197878492 ps
CPU time 404.26 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:08:05 PM PST 24
Peak memory 202136 kb
Host smart-c1f89291-03d5-46f9-9f24-933c9aae099a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942023101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2942023101
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.1445139522
Short name T766
Test name
Test status
Simulation time 1399754337 ps
CPU time 5.71 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:01:26 PM PST 24
Peak memory 202452 kb
Host smart-d5d232fc-6175-4bad-80f5-b491c8b5f72a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445139522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.1445139522
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.3650108693
Short name T915
Test name
Test status
Simulation time 10634114680 ps
CPU time 1003.18 seconds
Started Feb 07 02:01:15 PM PST 24
Finished Feb 07 02:18:00 PM PST 24
Peak memory 374984 kb
Host smart-96497413-c93a-4703-ae9c-3b9049af416b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650108693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3650108693
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.1379119182
Short name T585
Test name
Test status
Simulation time 1126353148 ps
CPU time 38.24 seconds
Started Feb 07 02:01:05 PM PST 24
Finished Feb 07 02:01:45 PM PST 24
Peak memory 285812 kb
Host smart-630d2c20-39b8-4635-9ef9-c5a6db875d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379119182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1379119182
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.3119022598
Short name T649
Test name
Test status
Simulation time 327746882258 ps
CPU time 2479.45 seconds
Started Feb 07 02:01:20 PM PST 24
Finished Feb 07 02:42:40 PM PST 24
Peak memory 372408 kb
Host smart-0cba222c-b393-46aa-9334-82e62ade0191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119022598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.3119022598
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1735371305
Short name T596
Test name
Test status
Simulation time 2830750000 ps
CPU time 3389.12 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:57:46 PM PST 24
Peak memory 432428 kb
Host smart-7a600764-9fff-4fa5-ade8-e2f93e0b06e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1735371305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1735371305
Directory /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3897229927
Short name T100
Test name
Test status
Simulation time 8458564247 ps
CPU time 291.09 seconds
Started Feb 07 02:01:19 PM PST 24
Finished Feb 07 02:06:11 PM PST 24
Peak memory 202224 kb
Host smart-145434ce-9a14-401b-9eda-da26fd470379
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897229927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.3897229927
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.4128760344
Short name T542
Test name
Test status
Simulation time 745586323 ps
CPU time 84.13 seconds
Started Feb 07 02:01:16 PM PST 24
Finished Feb 07 02:02:41 PM PST 24
Peak memory 307728 kb
Host smart-8846058f-bc16-46b5-80c7-1000dfb76b5e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128760344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.4128760344
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%