Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15033988

1

T1

135068

T2

58979

T4

105

full_word

126272657

1

T1

29855

T2

3026

T4

1045

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	141306355	1			T1	164923		T2	62005		T4	1150
auto[TlIntgErrCmd]	108	1			T31	8		T32	3		T33	1
auto[TlIntgErrData]	99	1			T31	5		T32	1		T33	6
auto[TlIntgErrBoth]	83	1			T31	7		T32	6		T33	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68427782

1

T1

82573

T2

30974

T4

553

auto[1]

72878863

1

T1

82350

T2

31031

T4

597

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7467685	1			T1	67675		T2	30722		T4	55
auto[TlIntgErrNone]	partial	auto[1]	7566040	1			T1	67393		T2	28257		T4	50
auto[TlIntgErrNone]	full_word	auto[0]	60959977	1			T1	14898		T2	252		T4	498
auto[TlIntgErrNone]	full_word	auto[1]	65312653	1			T1	14957		T2	2774		T4	547
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T31	4		T32	1		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T31	4		T32	2		T58	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T33	1		T107	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T53	1		T112	3		T111	2
auto[TlIntgErrData]	partial	auto[0]	40	1			T31	2		T32	1		T33	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T31	3		T33	4		T58	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T107	1		T111	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T109	1		T114	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T31	2		T32	1		T33	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T31	4		T32	4		T58	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T102	1		T110	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T31	1		T32	1		T53	1