Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	658262	1			T2	8638		T5	13864		T13	739
auto[1]	10318259	1			T1	8686		T2	8218		T4	486
auto[2]	516200	1			T2	6850		T5	12644		T13	333
auto[3]	10179659	1			T1	8908		T2	6122		T4	538

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12856493	1			T1	252		T2	7		T4	860
auto[1]	2045903	1			T1	1956		T2	904		T4	80
auto[2]	2088855	1			T1	2033		T2	786		T4	76
auto[3]	4681129	1			T1	13353		T2	28131		T4	8

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8527580

1

T2

29826

T4

1023

T8

45401

auto[1]

13144800

1

T1

17594

T2

2

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	286939	1			T5	11445		T13	617		T127	4070
auto[0]	auto[0]	auto[1]	30176	1			T2	63		T5	1123		T13	69
auto[0]	auto[0]	auto[2]	30139	1			T2	71		T5	1180		T13	49
auto[0]	auto[0]	auto[3]	59307	1			T2	8503		T5	116		T13	4
auto[0]	auto[1]	auto[0]	2688877	1			T4	397		T8	18880		T9	58942
auto[0]	auto[1]	auto[1]	292350	1			T2	69		T4	39		T8	1782
auto[0]	auto[1]	auto[2]	326407	1			T2	115		T4	45		T8	1851
auto[0]	auto[1]	auto[3]	640851	1			T2	8034		T4	4		T8	192
auto[0]	auto[2]	auto[0]	222675	1			T2	3		T5	10732		T13	274
auto[0]	auto[2]	auto[1]	27154	1			T2	721		T5	1054		T13	20
auto[0]	auto[2]	auto[2]	20831	1			T2	56		T5	776		T13	34
auto[0]	auto[2]	auto[3]	43528	1			T2	6069		T5	82		T13	5
auto[0]	auto[3]	auto[0]	2626619	1			T2	4		T4	463		T8	18855
auto[0]	auto[3]	auto[1]	312258	1			T2	51		T4	40		T8	1818
auto[0]	auto[3]	auto[2]	329739	1			T2	544		T4	31		T8	1817
auto[0]	auto[3]	auto[3]	589730	1			T2	5523		T4	4		T8	206
auto[1]	auto[0]	auto[0]	8298	1			T89	413		T91	925		T92	342
auto[1]	auto[0]	auto[1]	37117	1			T89	1747		T91	4224		T92	1467
auto[1]	auto[0]	auto[2]	37425	1			T89	1788		T91	4275		T92	1483
auto[1]	auto[0]	auto[3]	168861	1			T2	1		T89	7677		T91	19299
auto[1]	auto[1]	auto[0]	3509987	1			T1	114		T8	1		T9	1
auto[1]	auto[1]	auto[1]	667513	1			T1	1409		T4	1		T11	1440
auto[1]	auto[1]	auto[2]	654314	1			T1	548		T11	552		T89	288
auto[1]	auto[1]	auto[3]	1537960	1			T1	6615		T11	6690		T89	7840
auto[1]	auto[2]	auto[0]	6825	1			T89	347		T91	850		T92	296
auto[1]	auto[2]	auto[1]	30845	1			T89	1578		T91	3936		T92	1315
auto[1]	auto[2]	auto[2]	29846	1			T89	1185		T91	2861		T92	1040
auto[1]	auto[2]	auto[3]	134496	1			T2	1		T89	5344		T91	12998
auto[1]	auto[3]	auto[0]	3506273	1			T1	138		T9	2		T11	136
auto[1]	auto[3]	auto[1]	648490	1			T1	547		T11	553		T89	161
auto[1]	auto[3]	auto[2]	660154	1			T1	1485		T11	1449		T89	1266
auto[1]	auto[3]	auto[3]	1506396	1			T1	6738		T11	6910		T89	5421