Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	905953886	6035	0	0
ctrl_regwen_rd_A	905953886	1853	0	0
exec_rd_A	905953886	1841	0	0
exec_regwen_rd_A	905953886	1837	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905953886	6035	0	0
T31	12273	4	0	0
T33	10930	3	0	0
T34	3052	304	0	0
T35	9093	298	0	0
T49	8822	302	0	0
T50	3789	585	0	0
T51	6187	266	0	0
T52	6194	28	0	0
T53	8708	2	0	0
T58	6363	1	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905953886	1853	0	0
T35	9093	41	0	0
T52	6194	19	0	0
T55	7387	96	0	0
T56	16564	57	0	0
T62	1885	21	0	0
T67	1180	4	0	0
T85	1216	25	0	0
T98	933	5	0	0
T102	16528	87	0	0
T103	16890	408	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905953886	1841	0	0
T35	9093	45	0	0
T52	6194	15	0	0
T55	7387	25	0	0
T56	16564	81	0	0
T62	1885	37	0	0
T85	1216	6	0	0
T98	933	3	0	0
T102	16528	73	0	0
T103	16890	419	0	0
T104	1059	4	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905953886	1837	0	0
T35	9093	54	0	0
T52	6194	28	0	0
T55	7387	58	0	0
T56	16564	58	0	0
T62	1885	15	0	0
T67	1180	14	0	0
T85	1216	8	0	0
T102	16528	69	0	0
T103	16890	454	0	0
T104	1059	7	0	0