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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 100.00 97.62 100.00 100.00 99.15 99.70 98.52


Total test records in report: 894
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T805 /workspace/coverage/default/37.sram_ctrl_bijection.304485124 Feb 18 01:30:06 PM PST 24 Feb 18 02:02:01 PM PST 24 110636694178 ps
T806 /workspace/coverage/default/43.sram_ctrl_bijection.271638070 Feb 18 01:31:04 PM PST 24 Feb 18 01:42:03 PM PST 24 111406186189 ps
T807 /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2327125484 Feb 18 01:27:17 PM PST 24 Feb 18 01:33:08 PM PST 24 5293061267 ps
T808 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3320571638 Feb 18 01:30:14 PM PST 24 Feb 18 01:36:24 PM PST 24 23962412935 ps
T809 /workspace/coverage/default/49.sram_ctrl_stress_all.1257058110 Feb 18 01:32:13 PM PST 24 Feb 18 01:50:05 PM PST 24 51373510517 ps
T810 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1376732198 Feb 18 01:24:21 PM PST 24 Feb 18 01:25:29 PM PST 24 755067260 ps
T811 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3781223958 Feb 18 01:31:53 PM PST 24 Feb 18 01:33:12 PM PST 24 1047919449 ps
T812 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2718534649 Feb 18 01:25:00 PM PST 24 Feb 18 01:25:30 PM PST 24 2058144838 ps
T813 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.939124821 Feb 18 01:30:21 PM PST 24 Feb 18 01:32:54 PM PST 24 4713476601 ps
T814 /workspace/coverage/default/41.sram_ctrl_partial_access.3047903522 Feb 18 01:30:33 PM PST 24 Feb 18 01:30:52 PM PST 24 4112409123 ps
T815 /workspace/coverage/default/11.sram_ctrl_lc_escalation.2196671120 Feb 18 01:25:17 PM PST 24 Feb 18 01:26:53 PM PST 24 31433154638 ps
T816 /workspace/coverage/default/39.sram_ctrl_partial_access.137215742 Feb 18 01:30:14 PM PST 24 Feb 18 01:31:07 PM PST 24 7212778092 ps
T817 /workspace/coverage/default/45.sram_ctrl_smoke.2423247898 Feb 18 01:31:22 PM PST 24 Feb 18 01:31:38 PM PST 24 6934518473 ps
T818 /workspace/coverage/default/26.sram_ctrl_max_throughput.3687440027 Feb 18 01:28:11 PM PST 24 Feb 18 01:28:59 PM PST 24 1414490065 ps
T819 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1477384011 Feb 18 01:28:02 PM PST 24 Feb 18 01:28:38 PM PST 24 3540743436 ps
T820 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.813603706 Feb 18 01:24:39 PM PST 24 Feb 18 01:27:07 PM PST 24 4562519520 ps
T821 /workspace/coverage/default/28.sram_ctrl_partial_access.1342921222 Feb 18 01:28:30 PM PST 24 Feb 18 01:30:05 PM PST 24 1165795942 ps
T822 /workspace/coverage/default/33.sram_ctrl_executable.2519585789 Feb 18 01:29:22 PM PST 24 Feb 18 01:42:41 PM PST 24 13758958983 ps
T823 /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2653433138 Feb 18 01:23:57 PM PST 24 Feb 18 01:27:23 PM PST 24 10888115560 ps
T824 /workspace/coverage/default/44.sram_ctrl_multiple_keys.1480868554 Feb 18 01:31:09 PM PST 24 Feb 18 01:33:21 PM PST 24 6654109946 ps
T825 /workspace/coverage/default/34.sram_ctrl_max_throughput.3944230453 Feb 18 01:29:32 PM PST 24 Feb 18 01:30:27 PM PST 24 1460805115 ps
T826 /workspace/coverage/default/44.sram_ctrl_regwen.2840200729 Feb 18 01:31:19 PM PST 24 Feb 18 01:47:49 PM PST 24 18370681711 ps
T39 /workspace/coverage/default/1.sram_ctrl_sec_cm.295312494 Feb 18 01:24:06 PM PST 24 Feb 18 01:24:10 PM PST 24 249086195 ps
T827 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.4014281306 Feb 18 01:25:53 PM PST 24 Feb 18 01:31:26 PM PST 24 7958483211 ps
T828 /workspace/coverage/default/30.sram_ctrl_alert_test.4181000604 Feb 18 01:28:59 PM PST 24 Feb 18 01:29:03 PM PST 24 24829718 ps
T829 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1683812314 Feb 18 01:27:31 PM PST 24 Feb 18 01:29:33 PM PST 24 2905758848 ps
T830 /workspace/coverage/default/6.sram_ctrl_max_throughput.3307703419 Feb 18 01:24:40 PM PST 24 Feb 18 01:25:56 PM PST 24 4058020374 ps
T831 /workspace/coverage/default/7.sram_ctrl_alert_test.2660189072 Feb 18 01:24:54 PM PST 24 Feb 18 01:24:56 PM PST 24 12294282 ps
T832 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1477390396 Feb 18 01:31:05 PM PST 24 Feb 18 01:35:12 PM PST 24 3730000069 ps
T833 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1900956153 Feb 18 01:31:11 PM PST 24 Feb 18 01:35:53 PM PST 24 10116715269 ps
T834 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3565282918 Feb 18 01:26:43 PM PST 24 Feb 18 01:29:22 PM PST 24 22980828672 ps
T835 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1838926343 Feb 18 01:27:58 PM PST 24 Feb 18 01:33:33 PM PST 24 8741426274 ps
T836 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3974896432 Feb 18 01:29:32 PM PST 24 Feb 18 01:36:19 PM PST 24 10647308491 ps
T837 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2919884658 Feb 18 01:24:19 PM PST 24 Feb 18 01:28:36 PM PST 24 4310764618 ps
T838 /workspace/coverage/default/0.sram_ctrl_ram_cfg.1864280274 Feb 18 01:23:58 PM PST 24 Feb 18 01:24:06 PM PST 24 1465695769 ps
T839 /workspace/coverage/default/48.sram_ctrl_regwen.1237674102 Feb 18 01:32:01 PM PST 24 Feb 18 01:38:08 PM PST 24 5821250076 ps
T840 /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1269498888 Feb 18 01:31:52 PM PST 24 Feb 18 01:35:19 PM PST 24 3214093987 ps
T841 /workspace/coverage/default/32.sram_ctrl_smoke.3910996928 Feb 18 01:29:17 PM PST 24 Feb 18 01:29:37 PM PST 24 3190040395 ps
T842 /workspace/coverage/default/48.sram_ctrl_bijection.3284833539 Feb 18 01:31:51 PM PST 24 Feb 18 01:41:39 PM PST 24 51272268077 ps
T843 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3392838166 Feb 18 01:29:34 PM PST 24 Feb 18 01:51:08 PM PST 24 14736461337 ps
T844 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3289770741 Feb 18 01:24:01 PM PST 24 Feb 18 01:24:32 PM PST 24 4556919591 ps
T845 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3647283772 Feb 18 01:30:16 PM PST 24 Feb 18 01:38:46 PM PST 24 20574910310 ps
T846 /workspace/coverage/default/31.sram_ctrl_smoke.2962452139 Feb 18 01:29:08 PM PST 24 Feb 18 01:31:05 PM PST 24 11853818948 ps
T847 /workspace/coverage/default/22.sram_ctrl_ram_cfg.176311702 Feb 18 01:27:32 PM PST 24 Feb 18 01:27:40 PM PST 24 711569786 ps
T848 /workspace/coverage/default/32.sram_ctrl_partial_access.1668132487 Feb 18 01:29:13 PM PST 24 Feb 18 01:29:23 PM PST 24 1920553753 ps
T849 /workspace/coverage/default/40.sram_ctrl_ram_cfg.53804709 Feb 18 01:30:30 PM PST 24 Feb 18 01:30:46 PM PST 24 346254411 ps
T850 /workspace/coverage/default/28.sram_ctrl_lc_escalation.2086952363 Feb 18 01:28:31 PM PST 24 Feb 18 01:30:46 PM PST 24 114718452191 ps
T851 /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3150359962 Feb 18 01:30:22 PM PST 24 Feb 18 01:36:00 PM PST 24 5014473980 ps
T852 /workspace/coverage/default/45.sram_ctrl_max_throughput.1822757074 Feb 18 01:31:21 PM PST 24 Feb 18 01:32:57 PM PST 24 3648807008 ps
T31 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3707975949 Feb 18 12:47:50 PM PST 24 Feb 18 12:48:03 PM PST 24 191805676 ps
T96 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2183854303 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:04 PM PST 24 11663592 ps
T97 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.489662483 Feb 18 12:47:38 PM PST 24 Feb 18 12:47:47 PM PST 24 28301620 ps
T34 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4025333431 Feb 18 12:47:38 PM PST 24 Feb 18 12:47:50 PM PST 24 132761060 ps
T98 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3348566296 Feb 18 12:47:44 PM PST 24 Feb 18 12:47:54 PM PST 24 38953131 ps
T85 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1879396626 Feb 18 12:47:38 PM PST 24 Feb 18 12:47:45 PM PST 24 48714717 ps
T35 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3783245366 Feb 18 12:47:42 PM PST 24 Feb 18 12:47:54 PM PST 24 336794454 ps
T49 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3710273135 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:06 PM PST 24 180060278 ps
T60 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2314991965 Feb 18 12:47:41 PM PST 24 Feb 18 12:47:50 PM PST 24 49630888 ps
T50 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3753058885 Feb 18 12:47:47 PM PST 24 Feb 18 12:48:01 PM PST 24 46232572 ps
T51 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2692217550 Feb 18 12:47:52 PM PST 24 Feb 18 12:48:07 PM PST 24 309407223 ps
T32 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1052695469 Feb 18 12:47:50 PM PST 24 Feb 18 12:48:02 PM PST 24 357704767 ps
T99 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3226846593 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:55 PM PST 24 22017450 ps
T52 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1164462371 Feb 18 12:47:58 PM PST 24 Feb 18 12:48:12 PM PST 24 68844637 ps
T33 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3776533540 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:56 PM PST 24 223079215 ps
T58 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1999899204 Feb 18 12:47:55 PM PST 24 Feb 18 12:48:08 PM PST 24 176812776 ps
T86 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3211033465 Feb 18 12:47:47 PM PST 24 Feb 18 12:47:58 PM PST 24 23685790 ps
T87 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.958784747 Feb 18 12:47:48 PM PST 24 Feb 18 12:47:59 PM PST 24 177162510 ps
T53 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1094240901 Feb 18 12:47:48 PM PST 24 Feb 18 12:47:59 PM PST 24 189326906 ps
T54 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.880573047 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:05 PM PST 24 362353769 ps
T100 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1426758492 Feb 18 12:47:53 PM PST 24 Feb 18 12:48:05 PM PST 24 13996351 ps
T61 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3961235836 Feb 18 12:47:58 PM PST 24 Feb 18 12:48:11 PM PST 24 20226524 ps
T62 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3119763741 Feb 18 12:47:38 PM PST 24 Feb 18 12:47:47 PM PST 24 19448485 ps
T59 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.85425948 Feb 18 12:47:55 PM PST 24 Feb 18 12:48:08 PM PST 24 168847607 ps
T55 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2538855474 Feb 18 12:47:56 PM PST 24 Feb 18 12:48:10 PM PST 24 238298241 ps
T88 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1836936464 Feb 18 12:47:58 PM PST 24 Feb 18 12:48:11 PM PST 24 47090540 ps
T56 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2073848647 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:09 PM PST 24 169035489 ps
T63 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3765647940 Feb 18 12:47:50 PM PST 24 Feb 18 12:48:01 PM PST 24 22938299 ps
T102 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.817117225 Feb 18 12:47:48 PM PST 24 Feb 18 12:48:00 PM PST 24 165309886 ps
T853 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3487870969 Feb 18 12:47:39 PM PST 24 Feb 18 12:47:48 PM PST 24 50816534 ps
T64 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2399258948 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:55 PM PST 24 34804158 ps
T65 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.974780723 Feb 18 12:47:44 PM PST 24 Feb 18 12:47:55 PM PST 24 26477908 ps
T66 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2127764171 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:55 PM PST 24 18735133 ps
T103 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2006140342 Feb 18 12:47:43 PM PST 24 Feb 18 12:47:54 PM PST 24 675658002 ps
T104 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4069527497 Feb 18 12:47:44 PM PST 24 Feb 18 12:47:53 PM PST 24 21225567 ps
T67 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1135115450 Feb 18 12:47:47 PM PST 24 Feb 18 12:47:58 PM PST 24 49217218 ps
T854 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3718229794 Feb 18 12:47:48 PM PST 24 Feb 18 12:47:58 PM PST 24 21791762 ps
T855 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3768039316 Feb 18 12:47:48 PM PST 24 Feb 18 12:48:01 PM PST 24 262125873 ps
T57 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2639874535 Feb 18 12:47:59 PM PST 24 Feb 18 12:48:13 PM PST 24 61117106 ps
T110 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1691983836 Feb 18 12:47:41 PM PST 24 Feb 18 12:47:51 PM PST 24 221754257 ps
T107 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2766276292 Feb 18 12:47:37 PM PST 24 Feb 18 12:47:45 PM PST 24 1481801786 ps
T856 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2125110670 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:04 PM PST 24 47742058 ps
T857 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.314299215 Feb 18 12:47:44 PM PST 24 Feb 18 12:47:54 PM PST 24 31201225 ps
T68 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1268498565 Feb 18 12:47:40 PM PST 24 Feb 18 12:47:48 PM PST 24 18864396 ps
T858 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2759082245 Feb 18 12:47:49 PM PST 24 Feb 18 12:48:00 PM PST 24 57388792 ps
T69 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1147976414 Feb 18 12:47:42 PM PST 24 Feb 18 12:47:53 PM PST 24 976041968 ps
T859 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.251637282 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:06 PM PST 24 404355898 ps
T860 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2918100473 Feb 18 12:47:42 PM PST 24 Feb 18 12:47:51 PM PST 24 131556243 ps
T71 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2362468448 Feb 18 12:47:44 PM PST 24 Feb 18 12:47:54 PM PST 24 29601922 ps
T861 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.592829555 Feb 18 12:47:58 PM PST 24 Feb 18 12:48:11 PM PST 24 30184329 ps
T862 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.531122025 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:07 PM PST 24 142173911 ps
T863 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2260753766 Feb 18 12:47:44 PM PST 24 Feb 18 12:47:54 PM PST 24 20110349 ps
T864 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2479450020 Feb 18 12:47:41 PM PST 24 Feb 18 12:47:50 PM PST 24 11238471 ps
T112 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3334175068 Feb 18 12:47:39 PM PST 24 Feb 18 12:47:48 PM PST 24 113173264 ps
T865 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4058719559 Feb 18 12:47:55 PM PST 24 Feb 18 12:48:07 PM PST 24 63896222 ps
T108 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.597046938 Feb 18 12:47:50 PM PST 24 Feb 18 12:48:03 PM PST 24 146146768 ps
T866 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3937101090 Feb 18 12:47:47 PM PST 24 Feb 18 12:48:01 PM PST 24 91813912 ps
T867 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1820375890 Feb 18 12:47:40 PM PST 24 Feb 18 12:47:50 PM PST 24 353055468 ps
T868 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2487576678 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:05 PM PST 24 76137069 ps
T869 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1094200024 Feb 18 12:47:37 PM PST 24 Feb 18 12:47:43 PM PST 24 29414200 ps
T111 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2506345645 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:58 PM PST 24 1019108678 ps
T870 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3430249264 Feb 18 12:47:38 PM PST 24 Feb 18 12:47:46 PM PST 24 19151552 ps
T871 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.503172482 Feb 18 12:47:54 PM PST 24 Feb 18 12:48:06 PM PST 24 22003429 ps
T872 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1557951751 Feb 18 12:47:59 PM PST 24 Feb 18 12:48:12 PM PST 24 252229056 ps
T873 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2061764184 Feb 18 12:47:58 PM PST 24 Feb 18 12:48:11 PM PST 24 116899059 ps
T874 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1126905056 Feb 18 12:47:49 PM PST 24 Feb 18 12:48:00 PM PST 24 18991388 ps
T875 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2403987862 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:04 PM PST 24 15264719 ps
T876 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3969428404 Feb 18 12:47:49 PM PST 24 Feb 18 12:48:03 PM PST 24 704055682 ps
T877 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2459239296 Feb 18 12:47:49 PM PST 24 Feb 18 12:47:59 PM PST 24 16405489 ps
T878 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2519938755 Feb 18 12:47:59 PM PST 24 Feb 18 12:48:14 PM PST 24 132922378 ps
T879 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.249710958 Feb 18 12:47:42 PM PST 24 Feb 18 12:47:52 PM PST 24 12827894 ps
T880 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1778633682 Feb 18 12:47:52 PM PST 24 Feb 18 12:48:05 PM PST 24 60644671 ps
T881 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3053310059 Feb 18 12:47:49 PM PST 24 Feb 18 12:48:04 PM PST 24 389674375 ps
T882 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3491925075 Feb 18 12:47:55 PM PST 24 Feb 18 12:48:10 PM PST 24 80598708 ps
T72 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.342150635 Feb 18 12:47:57 PM PST 24 Feb 18 12:48:09 PM PST 24 41627934 ps
T84 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1881433661 Feb 18 12:47:41 PM PST 24 Feb 18 12:47:51 PM PST 24 82004319 ps
T883 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2748898076 Feb 18 12:47:42 PM PST 24 Feb 18 12:47:51 PM PST 24 20607958 ps
T884 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1525218176 Feb 18 12:47:52 PM PST 24 Feb 18 12:48:04 PM PST 24 14219700 ps
T73 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.756295379 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:56 PM PST 24 27465947 ps
T885 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2198720936 Feb 18 12:47:52 PM PST 24 Feb 18 12:48:07 PM PST 24 87830758 ps
T886 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.342163757 Feb 18 12:47:52 PM PST 24 Feb 18 12:48:04 PM PST 24 43936043 ps
T887 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1415794979 Feb 18 12:47:37 PM PST 24 Feb 18 12:47:44 PM PST 24 69243902 ps
T888 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1167798445 Feb 18 12:47:40 PM PST 24 Feb 18 12:47:49 PM PST 24 17298178 ps
T889 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2668733370 Feb 18 12:47:51 PM PST 24 Feb 18 12:48:04 PM PST 24 45773582 ps
T890 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3274624083 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:56 PM PST 24 21316291 ps
T109 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2264699254 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:58 PM PST 24 631821762 ps
T74 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.940793538 Feb 18 12:47:49 PM PST 24 Feb 18 12:48:00 PM PST 24 24039532 ps
T891 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2781703823 Feb 18 12:47:59 PM PST 24 Feb 18 12:48:13 PM PST 24 313690233 ps
T113 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2187846979 Feb 18 12:47:47 PM PST 24 Feb 18 12:47:59 PM PST 24 270476033 ps
T892 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1918265098 Feb 18 12:47:47 PM PST 24 Feb 18 12:48:00 PM PST 24 237342192 ps
T115 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2736788241 Feb 18 12:47:45 PM PST 24 Feb 18 12:47:58 PM PST 24 377270184 ps
T75 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.114517613 Feb 18 12:47:58 PM PST 24 Feb 18 12:48:10 PM PST 24 13189177 ps
T893 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1983588135 Feb 18 12:47:55 PM PST 24 Feb 18 12:48:07 PM PST 24 156195871 ps
T114 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.737207691 Feb 18 12:47:52 PM PST 24 Feb 18 12:48:06 PM PST 24 171499602 ps
T894 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.542421027 Feb 18 12:47:59 PM PST 24 Feb 18 12:48:12 PM PST 24 269643579 ps

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.1021314533
Short name T5
Test name
Test status
Simulation time 194621320975 ps
CPU time 3916.18 seconds
Started Feb 18 01:26:07 PM PST 24
Finished Feb 18 02:31:24 PM PST 24
Peak memory 379088 kb
Host smart-0a1aa6c4-5f75-472d-aa76-69ec8c023955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021314533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.1021314533
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.3800079828
Short name T119
Test name
Test status
Simulation time 173698815550 ps
CPU time 5413.98 seconds
Started Feb 18 01:28:31 PM PST 24
Finished Feb 18 02:58:46 PM PST 24
Peak memory 378152 kb
Host smart-407b028c-ef0e-4a80-a53e-78dfb0a585e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800079828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.sram_ctrl_stress_all.3800079828
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3783245366
Short name T35
Test name
Test status
Simulation time 336794454 ps
CPU time 3.31 seconds
Started Feb 18 12:47:42 PM PST 24
Finished Feb 18 12:47:54 PM PST 24
Peak memory 202208 kb
Host smart-e99fc108-d646-401c-9f75-7b612d05ca0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783245366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3783245366
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3707975949
Short name T31
Test name
Test status
Simulation time 191805676 ps
CPU time 2.1 seconds
Started Feb 18 12:47:50 PM PST 24
Finished Feb 18 12:48:03 PM PST 24
Peak memory 202196 kb
Host smart-55ee955c-5539-418e-9043-b695af466040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707975949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 11.sram_ctrl_tl_intg_err.3707975949
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3456643819
Short name T17
Test name
Test status
Simulation time 914099490 ps
CPU time 1.7 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:24:21 PM PST 24
Peak memory 223836 kb
Host smart-31b32cfb-8d0f-4410-8e60-92ef9a3583c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456643819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3456643819
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.251374710
Short name T11
Test name
Test status
Simulation time 105598040372 ps
CPU time 339.2 seconds
Started Feb 18 01:29:12 PM PST 24
Finished Feb 18 01:34:52 PM PST 24
Peak memory 202216 kb
Host smart-ac3921d0-423e-4c78-bbac-c268290f8f63
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251374710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.sram_ctrl_partial_access_b2b.251374710
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.1137739772
Short name T125
Test name
Test status
Simulation time 12857269449 ps
CPU time 1066.9 seconds
Started Feb 18 01:30:41 PM PST 24
Finished Feb 18 01:48:29 PM PST 24
Peak memory 378204 kb
Host smart-daf4d350-ee5f-4651-a525-65c3c7229014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137739772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1137739772
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.141107798
Short name T91
Test name
Test status
Simulation time 97307786554 ps
CPU time 510.06 seconds
Started Feb 18 01:31:25 PM PST 24
Finished Feb 18 01:39:55 PM PST 24
Peak memory 202204 kb
Host smart-9c76d89d-f129-441a-acbe-c00567e00fa2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141107798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.sram_ctrl_partial_access_b2b.141107798
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.1837300745
Short name T7
Test name
Test status
Simulation time 4124747548 ps
CPU time 43.8 seconds
Started Feb 18 01:30:15 PM PST 24
Finished Feb 18 01:30:59 PM PST 24
Peak memory 210424 kb
Host smart-72d8de64-352e-47f5-814e-1133f71d53ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837300745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.1837300745
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.258103131
Short name T15
Test name
Test status
Simulation time 48942200231 ps
CPU time 936.57 seconds
Started Feb 18 01:25:38 PM PST 24
Finished Feb 18 01:41:15 PM PST 24
Peak memory 371976 kb
Host smart-72f42836-508c-469e-9599-c819af5c982f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258103131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.sram_ctrl_access_during_key_req.258103131
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.701106115
Short name T26
Test name
Test status
Simulation time 46733062391 ps
CPU time 3569.5 seconds
Started Feb 18 01:26:41 PM PST 24
Finished Feb 18 02:26:11 PM PST 24
Peak memory 379184 kb
Host smart-ab928fcc-bdf4-4973-a809-458961e047d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701106115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_stress_all.701106115
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3961235836
Short name T61
Test name
Test status
Simulation time 20226524 ps
CPU time 0.66 seconds
Started Feb 18 12:47:58 PM PST 24
Finished Feb 18 12:48:11 PM PST 24
Peak memory 201860 kb
Host smart-49346b34-bac7-4cf9-bead-b0695eeab532
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961235836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3961235836
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2264699254
Short name T109
Test name
Test status
Simulation time 631821762 ps
CPU time 2.48 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:58 PM PST 24
Peak memory 202176 kb
Host smart-e2511803-0674-45d6-9c99-69b1f2662026
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264699254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.2264699254
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.2410935195
Short name T152
Test name
Test status
Simulation time 1247978902 ps
CPU time 14.63 seconds
Started Feb 18 01:25:46 PM PST 24
Finished Feb 18 01:26:01 PM PST 24
Peak memory 202460 kb
Host smart-023f01ef-8f2a-430d-92da-e01175e4f809
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410935195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2410935195
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.400340168
Short name T269
Test name
Test status
Simulation time 64267572 ps
CPU time 0.6 seconds
Started Feb 18 01:26:18 PM PST 24
Finished Feb 18 01:26:19 PM PST 24
Peak memory 201720 kb
Host smart-20e027a6-e127-4135-af93-d923d44d32af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400340168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.400340168
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.463195502
Short name T126
Test name
Test status
Simulation time 425166685249 ps
CPU time 8458.02 seconds
Started Feb 18 01:27:04 PM PST 24
Finished Feb 18 03:48:05 PM PST 24
Peak memory 388436 kb
Host smart-37cde94e-5723-4e58-82f6-59b323ae438e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463195502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_stress_all.463195502
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2766276292
Short name T107
Test name
Test status
Simulation time 1481801786 ps
CPU time 2.08 seconds
Started Feb 18 12:47:37 PM PST 24
Finished Feb 18 12:47:45 PM PST 24
Peak memory 202112 kb
Host smart-af573640-63b1-4362-b4b2-7ff07b008920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766276292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2766276292
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.2626528417
Short name T14
Test name
Test status
Simulation time 24809034410 ps
CPU time 139.37 seconds
Started Feb 18 01:25:45 PM PST 24
Finished Feb 18 01:28:05 PM PST 24
Peak memory 265736 kb
Host smart-752eae91-cbfb-4946-aea5-ad783cce83b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626528417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.2626528417
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1691983836
Short name T110
Test name
Test status
Simulation time 221754257 ps
CPU time 2.25 seconds
Started Feb 18 12:47:41 PM PST 24
Finished Feb 18 12:47:51 PM PST 24
Peak memory 202204 kb
Host smart-f35067f0-9892-4c04-9e06-03db1f159659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691983836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.1691983836
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.342150635
Short name T72
Test name
Test status
Simulation time 41627934 ps
CPU time 0.63 seconds
Started Feb 18 12:47:57 PM PST 24
Finished Feb 18 12:48:09 PM PST 24
Peak memory 201840 kb
Host smart-10a03daa-3e40-4614-b842-c4656f666a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342150635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 19.sram_ctrl_csr_rw.342150635
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.489662483
Short name T97
Test name
Test status
Simulation time 28301620 ps
CPU time 0.74 seconds
Started Feb 18 12:47:38 PM PST 24
Finished Feb 18 12:47:47 PM PST 24
Peak memory 201300 kb
Host smart-7af32615-c419-4445-ace9-81856b548614
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489662483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.sram_ctrl_csr_aliasing.489662483
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1820375890
Short name T867
Test name
Test status
Simulation time 353055468 ps
CPU time 2.35 seconds
Started Feb 18 12:47:40 PM PST 24
Finished Feb 18 12:47:50 PM PST 24
Peak memory 201976 kb
Host smart-755ed805-1cbb-4a89-9376-8532189b256b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820375890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.1820375890
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3226846593
Short name T99
Test name
Test status
Simulation time 22017450 ps
CPU time 0.65 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:55 PM PST 24
Peak memory 201596 kb
Host smart-dc0a633d-41de-41e5-989f-af16d663e28e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226846593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.3226846593
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1094200024
Short name T869
Test name
Test status
Simulation time 29414200 ps
CPU time 0.65 seconds
Started Feb 18 12:47:37 PM PST 24
Finished Feb 18 12:47:43 PM PST 24
Peak memory 201884 kb
Host smart-5eb4a5b7-ad66-4e5b-9ffd-fc2c94dd41ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094200024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.1094200024
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1879396626
Short name T85
Test name
Test status
Simulation time 48714717 ps
CPU time 0.76 seconds
Started Feb 18 12:47:38 PM PST 24
Finished Feb 18 12:47:45 PM PST 24
Peak memory 201884 kb
Host smart-d3f98db1-c948-4f4f-9779-5952a49c201e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879396626 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1879396626
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3776533540
Short name T33
Test name
Test status
Simulation time 223079215 ps
CPU time 1.58 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:56 PM PST 24
Peak memory 201956 kb
Host smart-21c8ada4-d3a6-4eb4-ab38-2dee6d10171c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776533540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.3776533540
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3119763741
Short name T62
Test name
Test status
Simulation time 19448485 ps
CPU time 0.7 seconds
Started Feb 18 12:47:38 PM PST 24
Finished Feb 18 12:47:47 PM PST 24
Peak memory 201896 kb
Host smart-d05bed3e-d640-4969-acec-5d8a883e2d72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119763741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.3119763741
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3487870969
Short name T853
Test name
Test status
Simulation time 50816534 ps
CPU time 1.31 seconds
Started Feb 18 12:47:39 PM PST 24
Finished Feb 18 12:47:48 PM PST 24
Peak memory 202096 kb
Host smart-3e536f7b-7d70-4d89-951c-f506905947e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487870969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.3487870969
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1415794979
Short name T887
Test name
Test status
Simulation time 69243902 ps
CPU time 0.67 seconds
Started Feb 18 12:47:37 PM PST 24
Finished Feb 18 12:47:44 PM PST 24
Peak memory 201920 kb
Host smart-324cf730-79e0-4ede-ae36-c422ae79eae9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415794979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_hw_reset.1415794979
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1167798445
Short name T888
Test name
Test status
Simulation time 17298178 ps
CPU time 0.69 seconds
Started Feb 18 12:47:40 PM PST 24
Finished Feb 18 12:47:49 PM PST 24
Peak memory 201520 kb
Host smart-cb8b3962-f80a-42fe-af57-7a2b19db6aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167798445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_csr_rw.1167798445
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2314991965
Short name T60
Test name
Test status
Simulation time 49630888 ps
CPU time 0.71 seconds
Started Feb 18 12:47:41 PM PST 24
Finished Feb 18 12:47:50 PM PST 24
Peak memory 202016 kb
Host smart-bc6da875-c1b0-4f8a-85e7-e64773649857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314991965 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.2314991965
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4025333431
Short name T34
Test name
Test status
Simulation time 132761060 ps
CPU time 3.56 seconds
Started Feb 18 12:47:38 PM PST 24
Finished Feb 18 12:47:50 PM PST 24
Peak memory 202260 kb
Host smart-6cf25e95-e922-44ae-bfe1-222760a4baef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025333431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.4025333431
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3334175068
Short name T112
Test name
Test status
Simulation time 113173264 ps
CPU time 1.58 seconds
Started Feb 18 12:47:39 PM PST 24
Finished Feb 18 12:47:48 PM PST 24
Peak memory 202144 kb
Host smart-912fcba9-1f5b-4e9d-933f-cf530de37a2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334175068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.3334175068
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.940793538
Short name T74
Test name
Test status
Simulation time 24039532 ps
CPU time 0.63 seconds
Started Feb 18 12:47:49 PM PST 24
Finished Feb 18 12:48:00 PM PST 24
Peak memory 201912 kb
Host smart-dfa4ba25-cae1-447e-9fe5-1b43afce6bbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940793538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 10.sram_ctrl_csr_rw.940793538
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2127764171
Short name T66
Test name
Test status
Simulation time 18735133 ps
CPU time 0.72 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:55 PM PST 24
Peak memory 201932 kb
Host smart-2c0034cf-e449-4272-acb6-ca64f1405536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127764171 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.2127764171
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2073848647
Short name T56
Test name
Test status
Simulation time 169035489 ps
CPU time 5.48 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:09 PM PST 24
Peak memory 202248 kb
Host smart-bed6249e-245f-4b39-87bb-068f5dce2e59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073848647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.2073848647
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1094240901
Short name T53
Test name
Test status
Simulation time 189326906 ps
CPU time 1.46 seconds
Started Feb 18 12:47:48 PM PST 24
Finished Feb 18 12:47:59 PM PST 24
Peak memory 202228 kb
Host smart-732f7a67-0b06-494e-b319-d84e0e302e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094240901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.1094240901
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2362468448
Short name T71
Test name
Test status
Simulation time 29601922 ps
CPU time 0.64 seconds
Started Feb 18 12:47:44 PM PST 24
Finished Feb 18 12:47:54 PM PST 24
Peak memory 201900 kb
Host smart-26e6089f-eb1a-4f20-b898-5cec93d7cbb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362468448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.2362468448
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1836936464
Short name T88
Test name
Test status
Simulation time 47090540 ps
CPU time 0.74 seconds
Started Feb 18 12:47:58 PM PST 24
Finished Feb 18 12:48:11 PM PST 24
Peak memory 201976 kb
Host smart-e58a33c1-b61a-4c9a-930d-95d3a89ae346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836936464 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1836936464
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3753058885
Short name T50
Test name
Test status
Simulation time 46232572 ps
CPU time 3.84 seconds
Started Feb 18 12:47:47 PM PST 24
Finished Feb 18 12:48:01 PM PST 24
Peak memory 201384 kb
Host smart-543fc3c2-2602-4e33-b293-bdc5101a2daf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753058885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.sram_ctrl_tl_errors.3753058885
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2403987862
Short name T875
Test name
Test status
Simulation time 15264719 ps
CPU time 0.68 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:04 PM PST 24
Peak memory 201680 kb
Host smart-b6f131fd-6d51-4b9e-9fa6-f1fdeb3b617d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403987862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2403987862
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.592829555
Short name T861
Test name
Test status
Simulation time 30184329 ps
CPU time 0.7 seconds
Started Feb 18 12:47:58 PM PST 24
Finished Feb 18 12:48:11 PM PST 24
Peak memory 201976 kb
Host smart-a9255949-0943-4ac8-8c2e-d86dba3c6556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592829555 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.592829555
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3053310059
Short name T881
Test name
Test status
Simulation time 389674375 ps
CPU time 4.67 seconds
Started Feb 18 12:47:49 PM PST 24
Finished Feb 18 12:48:04 PM PST 24
Peak memory 202224 kb
Host smart-23c011b5-9003-449a-ada0-d7513e3e9a92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053310059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.3053310059
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.880573047
Short name T54
Test name
Test status
Simulation time 362353769 ps
CPU time 1.51 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:05 PM PST 24
Peak memory 202232 kb
Host smart-8b979f8a-fb95-499b-9617-fed2330cc384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880573047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.sram_ctrl_tl_intg_err.880573047
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1983588135
Short name T893
Test name
Test status
Simulation time 156195871 ps
CPU time 0.68 seconds
Started Feb 18 12:47:55 PM PST 24
Finished Feb 18 12:48:07 PM PST 24
Peak memory 201864 kb
Host smart-51d6f285-ff66-4ef3-a234-bbd3ade32ec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983588135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1983588135
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3718229794
Short name T854
Test name
Test status
Simulation time 21791762 ps
CPU time 0.76 seconds
Started Feb 18 12:47:48 PM PST 24
Finished Feb 18 12:47:58 PM PST 24
Peak memory 201968 kb
Host smart-b6ef6609-6b13-404b-9194-21467d8ab4e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718229794 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3718229794
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2692217550
Short name T51
Test name
Test status
Simulation time 309407223 ps
CPU time 2.61 seconds
Started Feb 18 12:47:52 PM PST 24
Finished Feb 18 12:48:07 PM PST 24
Peak memory 202240 kb
Host smart-cd95f3ed-3982-4f98-8c83-1b01ac368b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692217550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.2692217550
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1052695469
Short name T32
Test name
Test status
Simulation time 357704767 ps
CPU time 1.51 seconds
Started Feb 18 12:47:50 PM PST 24
Finished Feb 18 12:48:02 PM PST 24
Peak memory 202232 kb
Host smart-f3d83cb0-39d2-4adc-9ff2-fd3e412bea58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052695469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.1052695469
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4058719559
Short name T865
Test name
Test status
Simulation time 63896222 ps
CPU time 0.7 seconds
Started Feb 18 12:47:55 PM PST 24
Finished Feb 18 12:48:07 PM PST 24
Peak memory 201024 kb
Host smart-b7f76728-355e-4b8b-a05a-511db0cd8bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058719559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_csr_rw.4058719559
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2668733370
Short name T889
Test name
Test status
Simulation time 45773582 ps
CPU time 0.75 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:04 PM PST 24
Peak memory 201724 kb
Host smart-a8796776-45d3-4541-bb18-afaec44b2a01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668733370 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.2668733370
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2781703823
Short name T891
Test name
Test status
Simulation time 313690233 ps
CPU time 2.59 seconds
Started Feb 18 12:47:59 PM PST 24
Finished Feb 18 12:48:13 PM PST 24
Peak memory 202316 kb
Host smart-1dbca719-3373-4410-b1a6-f072585b7cac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781703823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.sram_ctrl_tl_errors.2781703823
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3768039316
Short name T855
Test name
Test status
Simulation time 262125873 ps
CPU time 2.52 seconds
Started Feb 18 12:47:48 PM PST 24
Finished Feb 18 12:48:01 PM PST 24
Peak memory 202212 kb
Host smart-6198ae45-fb8a-41b7-8630-1c730de15c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768039316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3768039316
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1426758492
Short name T100
Test name
Test status
Simulation time 13996351 ps
CPU time 0.66 seconds
Started Feb 18 12:47:53 PM PST 24
Finished Feb 18 12:48:05 PM PST 24
Peak memory 201292 kb
Host smart-eec1ce68-879c-4b87-a1c6-5b3f3f628b49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426758492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_csr_rw.1426758492
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2125110670
Short name T856
Test name
Test status
Simulation time 47742058 ps
CPU time 0.76 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:04 PM PST 24
Peak memory 202008 kb
Host smart-3d2bf180-f7c0-4d4a-824b-03429b991a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125110670 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2125110670
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1164462371
Short name T52
Test name
Test status
Simulation time 68844637 ps
CPU time 2.11 seconds
Started Feb 18 12:47:58 PM PST 24
Finished Feb 18 12:48:12 PM PST 24
Peak memory 202204 kb
Host smart-7232f811-805b-4bae-aaec-33d2eb5a37dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164462371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1164462371
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.85425948
Short name T59
Test name
Test status
Simulation time 168847607 ps
CPU time 1.68 seconds
Started Feb 18 12:47:55 PM PST 24
Finished Feb 18 12:48:08 PM PST 24
Peak memory 201292 kb
Host smart-9b2b448c-54dc-46b4-ba15-2e6fb33d8f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85425948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te
st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.sram_ctrl_tl_intg_err.85425948
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1525218176
Short name T884
Test name
Test status
Simulation time 14219700 ps
CPU time 0.65 seconds
Started Feb 18 12:47:52 PM PST 24
Finished Feb 18 12:48:04 PM PST 24
Peak memory 201872 kb
Host smart-18abe829-6a0e-4304-8aa6-cf68521fa4a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525218176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.1525218176
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.342163757
Short name T886
Test name
Test status
Simulation time 43936043 ps
CPU time 0.79 seconds
Started Feb 18 12:47:52 PM PST 24
Finished Feb 18 12:48:04 PM PST 24
Peak memory 202000 kb
Host smart-fef27248-3b8e-4a29-8f27-14a24647e38b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342163757 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.342163757
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3710273135
Short name T49
Test name
Test status
Simulation time 180060278 ps
CPU time 3.13 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:06 PM PST 24
Peak memory 201924 kb
Host smart-2721eb5a-958a-4410-aed1-20e2cb5de7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710273135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.3710273135
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1999899204
Short name T58
Test name
Test status
Simulation time 176812776 ps
CPU time 1.48 seconds
Started Feb 18 12:47:55 PM PST 24
Finished Feb 18 12:48:08 PM PST 24
Peak memory 202180 kb
Host smart-6750757d-2d03-40fd-acb1-25c7e2688907
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999899204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.1999899204
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.503172482
Short name T871
Test name
Test status
Simulation time 22003429 ps
CPU time 0.71 seconds
Started Feb 18 12:47:54 PM PST 24
Finished Feb 18 12:48:06 PM PST 24
Peak memory 201908 kb
Host smart-948f2da6-864d-4642-9ecf-fa4695d014aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503172482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 17.sram_ctrl_csr_rw.503172482
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1778633682
Short name T880
Test name
Test status
Simulation time 60644671 ps
CPU time 0.79 seconds
Started Feb 18 12:47:52 PM PST 24
Finished Feb 18 12:48:05 PM PST 24
Peak memory 201868 kb
Host smart-ca179495-6430-4c1c-9e86-a94cc8dc103b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778633682 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1778633682
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3491925075
Short name T882
Test name
Test status
Simulation time 80598708 ps
CPU time 2.95 seconds
Started Feb 18 12:47:55 PM PST 24
Finished Feb 18 12:48:10 PM PST 24
Peak memory 202280 kb
Host smart-02b6a740-dac4-417e-b134-4c149131f7e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491925075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.sram_ctrl_tl_errors.3491925075
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.737207691
Short name T114
Test name
Test status
Simulation time 171499602 ps
CPU time 1.6 seconds
Started Feb 18 12:47:52 PM PST 24
Finished Feb 18 12:48:06 PM PST 24
Peak memory 202256 kb
Host smart-3a469b75-6a49-4fca-8424-339561057e45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737207691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.sram_ctrl_tl_intg_err.737207691
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3211033465
Short name T86
Test name
Test status
Simulation time 23685790 ps
CPU time 0.67 seconds
Started Feb 18 12:47:47 PM PST 24
Finished Feb 18 12:47:58 PM PST 24
Peak memory 201896 kb
Host smart-cd257f3f-5303-44f1-9c21-0e41337b735b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211033465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3211033465
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3765647940
Short name T63
Test name
Test status
Simulation time 22938299 ps
CPU time 0.67 seconds
Started Feb 18 12:47:50 PM PST 24
Finished Feb 18 12:48:01 PM PST 24
Peak memory 201980 kb
Host smart-4ae31dcc-5584-4c08-821c-917030490f0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765647940 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3765647940
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2538855474
Short name T55
Test name
Test status
Simulation time 238298241 ps
CPU time 2.91 seconds
Started Feb 18 12:47:56 PM PST 24
Finished Feb 18 12:48:10 PM PST 24
Peak memory 202140 kb
Host smart-5312e0ca-9d0d-4e3c-b2b9-f2fee3eecd26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538855474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.2538855474
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.542421027
Short name T894
Test name
Test status
Simulation time 269643579 ps
CPU time 1.42 seconds
Started Feb 18 12:47:59 PM PST 24
Finished Feb 18 12:48:12 PM PST 24
Peak memory 202212 kb
Host smart-7299763a-f585-4dec-8859-dcd1dd289d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542421027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.sram_ctrl_tl_intg_err.542421027
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2459239296
Short name T877
Test name
Test status
Simulation time 16405489 ps
CPU time 0.77 seconds
Started Feb 18 12:47:49 PM PST 24
Finished Feb 18 12:47:59 PM PST 24
Peak memory 201968 kb
Host smart-64fd23ca-95c7-4699-8feb-bc4a304c7b61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459239296 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.2459239296
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2198720936
Short name T885
Test name
Test status
Simulation time 87830758 ps
CPU time 2.9 seconds
Started Feb 18 12:47:52 PM PST 24
Finished Feb 18 12:48:07 PM PST 24
Peak memory 202232 kb
Host smart-a8a1e251-beb7-4010-ab9b-302b4a2f7c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198720936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.2198720936
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.597046938
Short name T108
Test name
Test status
Simulation time 146146768 ps
CPU time 2.18 seconds
Started Feb 18 12:47:50 PM PST 24
Finished Feb 18 12:48:03 PM PST 24
Peak memory 202196 kb
Host smart-e9423755-9da1-4a8e-9132-8dc4ab0d1e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597046938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.sram_ctrl_tl_intg_err.597046938
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1268498565
Short name T68
Test name
Test status
Simulation time 18864396 ps
CPU time 0.69 seconds
Started Feb 18 12:47:40 PM PST 24
Finished Feb 18 12:47:48 PM PST 24
Peak memory 201856 kb
Host smart-a287b0f8-8c4d-46ee-838b-1795e0ecc28a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268498565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.1268498565
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1881433661
Short name T84
Test name
Test status
Simulation time 82004319 ps
CPU time 1.82 seconds
Started Feb 18 12:47:41 PM PST 24
Finished Feb 18 12:47:51 PM PST 24
Peak memory 202016 kb
Host smart-f67b34c7-aa72-4d40-b8ab-797c7bef2f93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881433661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.1881433661
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3348566296
Short name T98
Test name
Test status
Simulation time 38953131 ps
CPU time 0.67 seconds
Started Feb 18 12:47:44 PM PST 24
Finished Feb 18 12:47:54 PM PST 24
Peak memory 201652 kb
Host smart-4c5e3404-7ce8-420d-a1bc-a88f21e11327
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348566296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.3348566296
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3430249264
Short name T870
Test name
Test status
Simulation time 19151552 ps
CPU time 0.75 seconds
Started Feb 18 12:47:38 PM PST 24
Finished Feb 18 12:47:46 PM PST 24
Peak memory 201876 kb
Host smart-9341dca4-6ea0-4319-bbcb-a76ccc7df5c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430249264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.3430249264
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.249710958
Short name T879
Test name
Test status
Simulation time 12827894 ps
CPU time 0.76 seconds
Started Feb 18 12:47:42 PM PST 24
Finished Feb 18 12:47:52 PM PST 24
Peak memory 201736 kb
Host smart-0f01a35d-3bb6-4ce5-b853-af5e2f3b74d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249710958 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.249710958
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1918265098
Short name T892
Test name
Test status
Simulation time 237342192 ps
CPU time 2.62 seconds
Started Feb 18 12:47:47 PM PST 24
Finished Feb 18 12:48:00 PM PST 24
Peak memory 202244 kb
Host smart-fb0d2688-3a19-401d-bb96-de7b9b1aef8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918265098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.1918265098
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.756295379
Short name T73
Test name
Test status
Simulation time 27465947 ps
CPU time 0.74 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:56 PM PST 24
Peak memory 201880 kb
Host smart-1789a1ce-2de8-4074-9035-c46731aeb8fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756295379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.sram_ctrl_csr_aliasing.756295379
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1147976414
Short name T69
Test name
Test status
Simulation time 976041968 ps
CPU time 2.49 seconds
Started Feb 18 12:47:42 PM PST 24
Finished Feb 18 12:47:53 PM PST 24
Peak memory 202156 kb
Host smart-a20c0b2b-db03-46bc-916f-a4e75867cdd1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147976414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1147976414
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2748898076
Short name T883
Test name
Test status
Simulation time 20607958 ps
CPU time 0.66 seconds
Started Feb 18 12:47:42 PM PST 24
Finished Feb 18 12:47:51 PM PST 24
Peak memory 201312 kb
Host smart-a44a4e2a-d6d3-41a2-9096-65df40ffd2c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748898076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2748898076
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2479450020
Short name T864
Test name
Test status
Simulation time 11238471 ps
CPU time 0.73 seconds
Started Feb 18 12:47:41 PM PST 24
Finished Feb 18 12:47:50 PM PST 24
Peak memory 201744 kb
Host smart-8b85ccee-e2e0-47fd-ac5f-a5cf18b88f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479450020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.2479450020
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2918100473
Short name T860
Test name
Test status
Simulation time 131556243 ps
CPU time 0.86 seconds
Started Feb 18 12:47:42 PM PST 24
Finished Feb 18 12:47:51 PM PST 24
Peak memory 201960 kb
Host smart-cc5497b2-2d03-477c-9f04-974c129db91e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918100473 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2918100473
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2487576678
Short name T868
Test name
Test status
Simulation time 76137069 ps
CPU time 2.61 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:05 PM PST 24
Peak memory 202272 kb
Host smart-27c90718-57cf-41e5-b908-7d2c12589c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487576678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.2487576678
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.114517613
Short name T75
Test name
Test status
Simulation time 13189177 ps
CPU time 0.73 seconds
Started Feb 18 12:47:58 PM PST 24
Finished Feb 18 12:48:10 PM PST 24
Peak memory 201860 kb
Host smart-dd363024-d761-407f-bf18-01b1174eee95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114517613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.sram_ctrl_csr_aliasing.114517613
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2006140342
Short name T103
Test name
Test status
Simulation time 675658002 ps
CPU time 2.43 seconds
Started Feb 18 12:47:43 PM PST 24
Finished Feb 18 12:47:54 PM PST 24
Peak memory 202156 kb
Host smart-c338646c-b35d-47b4-a4c9-63fa55e57b0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006140342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.2006140342
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2061764184
Short name T873
Test name
Test status
Simulation time 116899059 ps
CPU time 0.65 seconds
Started Feb 18 12:47:58 PM PST 24
Finished Feb 18 12:48:11 PM PST 24
Peak memory 201652 kb
Host smart-66cfb43c-6843-4182-81ff-8803e62b57fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061764184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.2061764184
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2260753766
Short name T863
Test name
Test status
Simulation time 20110349 ps
CPU time 0.76 seconds
Started Feb 18 12:47:44 PM PST 24
Finished Feb 18 12:47:54 PM PST 24
Peak memory 201976 kb
Host smart-f4079087-eef9-4c96-b92c-1ad365971e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260753766 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.2260753766
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2519938755
Short name T878
Test name
Test status
Simulation time 132922378 ps
CPU time 2.83 seconds
Started Feb 18 12:47:59 PM PST 24
Finished Feb 18 12:48:14 PM PST 24
Peak memory 210448 kb
Host smart-81468e73-fe4d-4039-bef3-3623b75dc14e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519938755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2519938755
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1557951751
Short name T872
Test name
Test status
Simulation time 252229056 ps
CPU time 1.43 seconds
Started Feb 18 12:47:59 PM PST 24
Finished Feb 18 12:48:12 PM PST 24
Peak memory 202192 kb
Host smart-f0b61d92-32de-4d9a-9025-9401efca06d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557951751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.1557951751
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1135115450
Short name T67
Test name
Test status
Simulation time 49217218 ps
CPU time 0.69 seconds
Started Feb 18 12:47:47 PM PST 24
Finished Feb 18 12:47:58 PM PST 24
Peak memory 201388 kb
Host smart-01dbb40c-9024-493c-b4ca-0bb12072fe0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135115450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.1135115450
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.314299215
Short name T857
Test name
Test status
Simulation time 31201225 ps
CPU time 0.68 seconds
Started Feb 18 12:47:44 PM PST 24
Finished Feb 18 12:47:54 PM PST 24
Peak memory 201976 kb
Host smart-ebde3ed2-604d-43d8-9cf8-df66393a0b97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314299215 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.314299215
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2639874535
Short name T57
Test name
Test status
Simulation time 61117106 ps
CPU time 2.26 seconds
Started Feb 18 12:47:59 PM PST 24
Finished Feb 18 12:48:13 PM PST 24
Peak memory 202208 kb
Host smart-930d8aff-2881-4b20-885d-9259bfb709f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639874535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.sram_ctrl_tl_errors.2639874535
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2187846979
Short name T113
Test name
Test status
Simulation time 270476033 ps
CPU time 1.52 seconds
Started Feb 18 12:47:47 PM PST 24
Finished Feb 18 12:47:59 PM PST 24
Peak memory 202232 kb
Host smart-96918283-6b71-4265-a0f5-3f708abbef35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187846979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.sram_ctrl_tl_intg_err.2187846979
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3274624083
Short name T890
Test name
Test status
Simulation time 21316291 ps
CPU time 0.68 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:56 PM PST 24
Peak memory 201896 kb
Host smart-d3ad0b3d-e746-4432-ab89-f2937d53b97a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274624083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.3274624083
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2399258948
Short name T64
Test name
Test status
Simulation time 34804158 ps
CPU time 0.74 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:55 PM PST 24
Peak memory 202016 kb
Host smart-8be2c525-f449-4642-9910-a5299dd9cc1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399258948 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.2399258948
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.531122025
Short name T862
Test name
Test status
Simulation time 142173911 ps
CPU time 4.57 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:07 PM PST 24
Peak memory 202188 kb
Host smart-37a99640-42a2-4f59-936f-cc1a96073331
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531122025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_tl_errors.531122025
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4069527497
Short name T104
Test name
Test status
Simulation time 21225567 ps
CPU time 0.66 seconds
Started Feb 18 12:47:44 PM PST 24
Finished Feb 18 12:47:53 PM PST 24
Peak memory 201804 kb
Host smart-d9e89906-d1e3-429f-adf5-8ea52c087f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069527497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.4069527497
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.974780723
Short name T65
Test name
Test status
Simulation time 26477908 ps
CPU time 0.71 seconds
Started Feb 18 12:47:44 PM PST 24
Finished Feb 18 12:47:55 PM PST 24
Peak memory 202040 kb
Host smart-b85c7109-e013-43f8-ba8c-d335e9746f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974780723 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.974780723
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3937101090
Short name T866
Test name
Test status
Simulation time 91813912 ps
CPU time 3.76 seconds
Started Feb 18 12:47:47 PM PST 24
Finished Feb 18 12:48:01 PM PST 24
Peak memory 202036 kb
Host smart-3ff23a79-e2e9-42bf-9555-c1ec06b0e948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937101090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.3937101090
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2506345645
Short name T111
Test name
Test status
Simulation time 1019108678 ps
CPU time 2.7 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:58 PM PST 24
Peak memory 202188 kb
Host smart-38087121-c400-4a5a-b37c-6644f317c076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506345645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.2506345645
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2759082245
Short name T858
Test name
Test status
Simulation time 57388792 ps
CPU time 0.66 seconds
Started Feb 18 12:47:49 PM PST 24
Finished Feb 18 12:48:00 PM PST 24
Peak memory 201348 kb
Host smart-60f3b722-2c64-4692-ab58-ae520556e73d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759082245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.2759082245
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.958784747
Short name T87
Test name
Test status
Simulation time 177162510 ps
CPU time 0.68 seconds
Started Feb 18 12:47:48 PM PST 24
Finished Feb 18 12:47:59 PM PST 24
Peak memory 201948 kb
Host smart-977d9e0b-711a-4d8e-9bcb-1f93de43ee13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958784747 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.958784747
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.251637282
Short name T859
Test name
Test status
Simulation time 404355898 ps
CPU time 2.59 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:06 PM PST 24
Peak memory 202276 kb
Host smart-3cf71e20-01e0-413e-92d5-0a7b2531e745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251637282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_tl_errors.251637282
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2736788241
Short name T115
Test name
Test status
Simulation time 377270184 ps
CPU time 2.8 seconds
Started Feb 18 12:47:45 PM PST 24
Finished Feb 18 12:47:58 PM PST 24
Peak memory 202196 kb
Host smart-aa0ab2b8-1059-4442-98c5-00fa6cc25a39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736788241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.2736788241
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2183854303
Short name T96
Test name
Test status
Simulation time 11663592 ps
CPU time 0.67 seconds
Started Feb 18 12:47:51 PM PST 24
Finished Feb 18 12:48:04 PM PST 24
Peak memory 201832 kb
Host smart-d079416e-9219-456c-9fa4-cff1e80faa99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183854303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.2183854303
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1126905056
Short name T874
Test name
Test status
Simulation time 18991388 ps
CPU time 0.73 seconds
Started Feb 18 12:47:49 PM PST 24
Finished Feb 18 12:48:00 PM PST 24
Peak memory 201936 kb
Host smart-aa1dae10-6e59-4dd6-b618-3449fe459196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126905056 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.1126905056
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3969428404
Short name T876
Test name
Test status
Simulation time 704055682 ps
CPU time 3.97 seconds
Started Feb 18 12:47:49 PM PST 24
Finished Feb 18 12:48:03 PM PST 24
Peak memory 202244 kb
Host smart-6e6b347e-643f-4a39-90d7-458583807830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969428404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.3969428404
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.817117225
Short name T102
Test name
Test status
Simulation time 165309886 ps
CPU time 2.22 seconds
Started Feb 18 12:47:48 PM PST 24
Finished Feb 18 12:48:00 PM PST 24
Peak memory 202192 kb
Host smart-21965d21-7f5f-4601-9112-b0d9b9b2961f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817117225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.sram_ctrl_tl_intg_err.817117225
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3005541853
Short name T338
Test name
Test status
Simulation time 85960514097 ps
CPU time 2327.48 seconds
Started Feb 18 01:23:58 PM PST 24
Finished Feb 18 02:02:46 PM PST 24
Peak memory 378184 kb
Host smart-0a9391b3-eb47-46ed-96dc-38321f327d7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005541853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.3005541853
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.3674622097
Short name T520
Test name
Test status
Simulation time 15364412 ps
CPU time 0.65 seconds
Started Feb 18 01:24:06 PM PST 24
Finished Feb 18 01:24:07 PM PST 24
Peak memory 201740 kb
Host smart-8838eae6-48b3-45b4-8fcc-d34298568e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674622097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.3674622097
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.4251256983
Short name T513
Test name
Test status
Simulation time 59082593617 ps
CPU time 1044.93 seconds
Started Feb 18 01:23:58 PM PST 24
Finished Feb 18 01:41:24 PM PST 24
Peak memory 202340 kb
Host smart-40da8bff-1efa-4145-a76b-08ab4e8e0f7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251256983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
4251256983
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.2255293195
Short name T710
Test name
Test status
Simulation time 15578213966 ps
CPU time 784.7 seconds
Started Feb 18 01:24:07 PM PST 24
Finished Feb 18 01:37:14 PM PST 24
Peak memory 377032 kb
Host smart-9bf33725-23a1-40c3-adad-47f66229d1e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255293195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.2255293195
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.2145143001
Short name T753
Test name
Test status
Simulation time 2706604991 ps
CPU time 29.65 seconds
Started Feb 18 01:24:00 PM PST 24
Finished Feb 18 01:24:31 PM PST 24
Peak memory 225056 kb
Host smart-040829ab-de00-4b99-8775-054ae6bd0edc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145143001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.2145143001
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.392132967
Short name T2
Test name
Test status
Simulation time 40558924887 ps
CPU time 163 seconds
Started Feb 18 01:24:05 PM PST 24
Finished Feb 18 01:26:49 PM PST 24
Peak memory 211580 kb
Host smart-881a7465-7b0d-447d-ba90-b78ca0b9b850
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392132967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
sram_ctrl_mem_partial_access.392132967
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.2330510124
Short name T795
Test name
Test status
Simulation time 10536632541 ps
CPU time 155.35 seconds
Started Feb 18 01:24:03 PM PST 24
Finished Feb 18 01:26:39 PM PST 24
Peak memory 202504 kb
Host smart-db53b44d-1ae0-4ef4-860b-8744084c6174
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330510124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl
_mem_walk.2330510124
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.2917209420
Short name T40
Test name
Test status
Simulation time 45200284526 ps
CPU time 627.87 seconds
Started Feb 18 01:23:59 PM PST 24
Finished Feb 18 01:34:27 PM PST 24
Peak memory 375076 kb
Host smart-f897fc8f-81c2-4a60-829b-f8bb10bfbff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917209420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.2917209420
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.2424197039
Short name T526
Test name
Test status
Simulation time 925656569 ps
CPU time 13.6 seconds
Started Feb 18 01:24:01 PM PST 24
Finished Feb 18 01:24:15 PM PST 24
Peak memory 202112 kb
Host smart-a20eb2cf-28a0-458d-82d9-4ccdc2ec6083
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424197039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.2424197039
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2189977378
Short name T41
Test name
Test status
Simulation time 20065704631 ps
CPU time 365.92 seconds
Started Feb 18 01:24:00 PM PST 24
Finished Feb 18 01:30:07 PM PST 24
Peak memory 202316 kb
Host smart-4697d3d4-d904-4607-a13e-128bdbcb8fb5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189977378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.sram_ctrl_partial_access_b2b.2189977378
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.1864280274
Short name T838
Test name
Test status
Simulation time 1465695769 ps
CPU time 7.31 seconds
Started Feb 18 01:23:58 PM PST 24
Finished Feb 18 01:24:06 PM PST 24
Peak memory 202472 kb
Host smart-46170f44-91de-4f7b-9026-37c62783fe13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864280274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1864280274
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.3254246219
Short name T470
Test name
Test status
Simulation time 89837815236 ps
CPU time 1308.1 seconds
Started Feb 18 01:24:00 PM PST 24
Finished Feb 18 01:45:49 PM PST 24
Peak memory 377124 kb
Host smart-0199697d-d696-405e-aa73-0632f6e04564
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254246219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3254246219
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.1904233141
Short name T38
Test name
Test status
Simulation time 1567788088 ps
CPU time 2.38 seconds
Started Feb 18 01:24:02 PM PST 24
Finished Feb 18 01:24:04 PM PST 24
Peak memory 223840 kb
Host smart-2e993bae-e5b1-4d57-b60e-14e15d7b2c10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904233141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.1904233141
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.4221599852
Short name T580
Test name
Test status
Simulation time 1901445785 ps
CPU time 112.48 seconds
Started Feb 18 01:24:07 PM PST 24
Finished Feb 18 01:26:01 PM PST 24
Peak memory 372868 kb
Host smart-8ba0ceaf-05aa-4194-9bc0-eecb52757598
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221599852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.4221599852
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2653433138
Short name T823
Test name
Test status
Simulation time 10888115560 ps
CPU time 205.19 seconds
Started Feb 18 01:23:57 PM PST 24
Finished Feb 18 01:27:23 PM PST 24
Peak memory 202300 kb
Host smart-141ae94b-80e0-498f-9f02-fcb274a99e4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653433138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.2653433138
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1235916423
Short name T457
Test name
Test status
Simulation time 729584231 ps
CPU time 45.77 seconds
Started Feb 18 01:24:00 PM PST 24
Finished Feb 18 01:24:47 PM PST 24
Peak memory 269684 kb
Host smart-a34706e4-0e20-4b4b-9f80-5db8d6dfd5cd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235916423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1235916423
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2047752329
Short name T198
Test name
Test status
Simulation time 10472264542 ps
CPU time 1588.13 seconds
Started Feb 18 01:24:04 PM PST 24
Finished Feb 18 01:50:33 PM PST 24
Peak memory 378124 kb
Host smart-feef8a29-d4cc-4d36-82d7-33a700908b98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047752329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.sram_ctrl_access_during_key_req.2047752329
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.3870745048
Short name T312
Test name
Test status
Simulation time 19714585 ps
CPU time 0.65 seconds
Started Feb 18 01:24:03 PM PST 24
Finished Feb 18 01:24:04 PM PST 24
Peak memory 202080 kb
Host smart-9adff206-f046-462f-bc33-a69025a12718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870745048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.3870745048
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.165280751
Short name T495
Test name
Test status
Simulation time 32788791266 ps
CPU time 2154.08 seconds
Started Feb 18 01:24:05 PM PST 24
Finished Feb 18 02:00:01 PM PST 24
Peak memory 202336 kb
Host smart-70e0d44c-b674-4809-ae5e-c55a57449cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165280751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.165280751
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.3417673336
Short name T6
Test name
Test status
Simulation time 12426029941 ps
CPU time 90.22 seconds
Started Feb 18 01:24:01 PM PST 24
Finished Feb 18 01:25:32 PM PST 24
Peak memory 210500 kb
Host smart-4d5fed95-7f3a-4461-b705-2005aa868fba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417673336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.3417673336
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1255622313
Short name T395
Test name
Test status
Simulation time 2969413570 ps
CPU time 79.85 seconds
Started Feb 18 01:24:07 PM PST 24
Finished Feb 18 01:25:29 PM PST 24
Peak memory 325996 kb
Host smart-ba81df3f-61a4-4497-b235-c0786d6876c7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255622313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1255622313
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1844279702
Short name T48
Test name
Test status
Simulation time 9403970954 ps
CPU time 80.52 seconds
Started Feb 18 01:24:07 PM PST 24
Finished Feb 18 01:25:29 PM PST 24
Peak memory 211328 kb
Host smart-0be22852-c77a-4c23-a075-d893e9b05f42
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844279702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.1844279702
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.1678869781
Short name T162
Test name
Test status
Simulation time 55055582431 ps
CPU time 277.15 seconds
Started Feb 18 01:24:05 PM PST 24
Finished Feb 18 01:28:43 PM PST 24
Peak memory 202272 kb
Host smart-a3fb4d8a-9017-4a01-a471-6a56b4ca1962
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678869781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.1678869781
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.2657506077
Short name T192
Test name
Test status
Simulation time 44826943710 ps
CPU time 721.94 seconds
Started Feb 18 01:24:02 PM PST 24
Finished Feb 18 01:36:04 PM PST 24
Peak memory 369136 kb
Host smart-5d594133-2c5b-4440-8974-0c82cc55918c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657506077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.2657506077
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2621959261
Short name T289
Test name
Test status
Simulation time 558436494 ps
CPU time 15.86 seconds
Started Feb 18 01:24:04 PM PST 24
Finished Feb 18 01:24:20 PM PST 24
Peak memory 241628 kb
Host smart-e4e92b12-d725-48bc-99d4-c50f97590e67
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621959261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2621959261
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.372132916
Short name T95
Test name
Test status
Simulation time 11709119878 ps
CPU time 206.56 seconds
Started Feb 18 01:24:08 PM PST 24
Finished Feb 18 01:27:36 PM PST 24
Peak memory 202304 kb
Host smart-425ea861-4951-4b0d-b034-31122c707b94
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372132916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.sram_ctrl_partial_access_b2b.372132916
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.3464542507
Short name T253
Test name
Test status
Simulation time 357433743 ps
CPU time 6.55 seconds
Started Feb 18 01:24:05 PM PST 24
Finished Feb 18 01:24:12 PM PST 24
Peak memory 202444 kb
Host smart-e45ded26-3737-4334-a8d4-5618d6b37815
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464542507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.3464542507
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.2575223681
Short name T20
Test name
Test status
Simulation time 11944382657 ps
CPU time 244.46 seconds
Started Feb 18 01:24:05 PM PST 24
Finished Feb 18 01:28:10 PM PST 24
Peak memory 351564 kb
Host smart-b3dd6ad6-0bef-49c2-ba60-c0638c0e98d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575223681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2575223681
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.295312494
Short name T39
Test name
Test status
Simulation time 249086195 ps
CPU time 1.98 seconds
Started Feb 18 01:24:06 PM PST 24
Finished Feb 18 01:24:10 PM PST 24
Peak memory 221084 kb
Host smart-bddd6ae9-c48b-4129-9f34-03d924487211
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295312494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_sec_cm.295312494
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.2165695833
Short name T750
Test name
Test status
Simulation time 519954624 ps
CPU time 25.34 seconds
Started Feb 18 01:24:02 PM PST 24
Finished Feb 18 01:24:28 PM PST 24
Peak memory 210356 kb
Host smart-37cd2b36-3ff0-49dd-aafa-a812d8c4705f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165695833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2165695833
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1181475474
Short name T502
Test name
Test status
Simulation time 203958224397 ps
CPU time 1237.83 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 01:44:57 PM PST 24
Peak memory 375076 kb
Host smart-d49c380c-0041-4a28-afc6-58eec9f6ef44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181475474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1181475474
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.199303919
Short name T424
Test name
Test status
Simulation time 6100668175 ps
CPU time 287.74 seconds
Started Feb 18 01:24:07 PM PST 24
Finished Feb 18 01:28:56 PM PST 24
Peak memory 202300 kb
Host smart-235650d3-c6b1-438a-bc37-a81d7559d69a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199303919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
sram_ctrl_stress_pipeline.199303919
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3289770741
Short name T844
Test name
Test status
Simulation time 4556919591 ps
CPU time 30.63 seconds
Started Feb 18 01:24:01 PM PST 24
Finished Feb 18 01:24:32 PM PST 24
Peak memory 222840 kb
Host smart-f52aa7e0-3288-4ccd-a9f3-cbeacff2d2f7
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289770741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.3289770741
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.911745782
Short name T725
Test name
Test status
Simulation time 61546778796 ps
CPU time 1348.63 seconds
Started Feb 18 01:25:12 PM PST 24
Finished Feb 18 01:47:41 PM PST 24
Peak memory 379140 kb
Host smart-9c9eb7a4-eb2d-4b07-9874-a1adcaba02b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911745782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 10.sram_ctrl_access_during_key_req.911745782
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.2287924447
Short name T644
Test name
Test status
Simulation time 128589904 ps
CPU time 0.65 seconds
Started Feb 18 01:25:17 PM PST 24
Finished Feb 18 01:25:18 PM PST 24
Peak memory 202072 kb
Host smart-7b53e24d-111c-4e78-9f52-6a224550e5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287924447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.sram_ctrl_alert_test.2287924447
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.1102095358
Short name T327
Test name
Test status
Simulation time 51476766047 ps
CPU time 1820.65 seconds
Started Feb 18 01:25:11 PM PST 24
Finished Feb 18 01:55:33 PM PST 24
Peak memory 202412 kb
Host smart-e86ed533-5aa1-42f4-8559-76012920ddf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102095358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.1102095358
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.2758879463
Short name T541
Test name
Test status
Simulation time 22210814031 ps
CPU time 70.82 seconds
Started Feb 18 01:25:08 PM PST 24
Finished Feb 18 01:26:20 PM PST 24
Peak memory 210476 kb
Host smart-b7271dc9-ced6-4b70-8e93-89c01f13791c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758879463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.2758879463
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3117625740
Short name T414
Test name
Test status
Simulation time 1591945271 ps
CPU time 174.06 seconds
Started Feb 18 01:25:10 PM PST 24
Finished Feb 18 01:28:05 PM PST 24
Peak memory 363792 kb
Host smart-a90f29c2-7bb5-4779-ae70-6d9280ff1ca1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117625740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3117625740
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2279059956
Short name T530
Test name
Test status
Simulation time 1618368585 ps
CPU time 139.61 seconds
Started Feb 18 01:25:10 PM PST 24
Finished Feb 18 01:27:30 PM PST 24
Peak memory 211264 kb
Host smart-69940f40-27dd-4d5f-bd8a-3a3605eb2782
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279059956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.2279059956
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.3724325410
Short name T696
Test name
Test status
Simulation time 2063698402 ps
CPU time 117.24 seconds
Started Feb 18 01:25:13 PM PST 24
Finished Feb 18 01:27:11 PM PST 24
Peak memory 202176 kb
Host smart-a9ec1158-5388-4bd3-8755-5eb3eb5bec45
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724325410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.3724325410
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.781491914
Short name T792
Test name
Test status
Simulation time 41057067983 ps
CPU time 965.05 seconds
Started Feb 18 01:25:10 PM PST 24
Finished Feb 18 01:41:16 PM PST 24
Peak memory 378084 kb
Host smart-46dc2639-f1b3-4f5b-9167-bb92a1465f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781491914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multip
le_keys.781491914
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.3689298378
Short name T379
Test name
Test status
Simulation time 28885517699 ps
CPU time 36.52 seconds
Started Feb 18 01:25:10 PM PST 24
Finished Feb 18 01:25:48 PM PST 24
Peak memory 202248 kb
Host smart-58ec88ed-7d98-4dc5-8969-67a51c099aff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689298378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.3689298378
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2078935696
Short name T778
Test name
Test status
Simulation time 12023618053 ps
CPU time 311.21 seconds
Started Feb 18 01:25:09 PM PST 24
Finished Feb 18 01:30:21 PM PST 24
Peak memory 202284 kb
Host smart-d63aab95-fcce-4732-bb2f-d3069d2a9770
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078935696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_partial_access_b2b.2078935696
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.489613177
Short name T293
Test name
Test status
Simulation time 363354792 ps
CPU time 13.44 seconds
Started Feb 18 01:25:11 PM PST 24
Finished Feb 18 01:25:26 PM PST 24
Peak memory 202476 kb
Host smart-a0f8aa17-8c82-4163-973b-3f6e141a150f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489613177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.489613177
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.2050709753
Short name T303
Test name
Test status
Simulation time 2855068624 ps
CPU time 164.32 seconds
Started Feb 18 01:25:12 PM PST 24
Finished Feb 18 01:27:58 PM PST 24
Peak memory 369856 kb
Host smart-79fce3e7-577e-4a2d-85ca-c206941b3089
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050709753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2050709753
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.4032226842
Short name T555
Test name
Test status
Simulation time 3449618380 ps
CPU time 8.6 seconds
Started Feb 18 01:25:12 PM PST 24
Finished Feb 18 01:25:21 PM PST 24
Peak memory 202284 kb
Host smart-8dfc1815-5cb5-4cb0-9aef-533afe41dc96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032226842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.4032226842
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1122171085
Short name T204
Test name
Test status
Simulation time 4965517011 ps
CPU time 231.15 seconds
Started Feb 18 01:25:08 PM PST 24
Finished Feb 18 01:29:00 PM PST 24
Peak memory 202296 kb
Host smart-13a6d276-58be-4af4-b027-a33f411d9247
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122171085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.1122171085
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3536212149
Short name T487
Test name
Test status
Simulation time 3077602019 ps
CPU time 75.67 seconds
Started Feb 18 01:25:11 PM PST 24
Finished Feb 18 01:26:28 PM PST 24
Peak memory 306604 kb
Host smart-bc292405-cae9-46bd-8bea-68e32338a493
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536212149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.3536212149
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2527734526
Short name T554
Test name
Test status
Simulation time 9077226452 ps
CPU time 1142.63 seconds
Started Feb 18 01:25:25 PM PST 24
Finished Feb 18 01:44:29 PM PST 24
Peak memory 378236 kb
Host smart-d5a142f8-d73f-4707-8bcf-db2d5760b5d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527734526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.2527734526
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.2879016271
Short name T176
Test name
Test status
Simulation time 12321582 ps
CPU time 0.64 seconds
Started Feb 18 01:25:35 PM PST 24
Finished Feb 18 01:25:37 PM PST 24
Peak memory 201860 kb
Host smart-3bb0a345-9199-4fdb-91b1-ba850d250ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879016271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.2879016271
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.3141671246
Short name T709
Test name
Test status
Simulation time 50815197760 ps
CPU time 1177.32 seconds
Started Feb 18 01:25:16 PM PST 24
Finished Feb 18 01:44:55 PM PST 24
Peak memory 202360 kb
Host smart-a0dd8960-d04a-4b41-8ac1-f8b90218396a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141671246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection
.3141671246
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.3558313759
Short name T484
Test name
Test status
Simulation time 65493145493 ps
CPU time 1033.92 seconds
Started Feb 18 01:25:26 PM PST 24
Finished Feb 18 01:42:42 PM PST 24
Peak memory 376124 kb
Host smart-03495e3d-d38d-4a36-85f9-16258dd6ba6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558313759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.3558313759
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.2196671120
Short name T815
Test name
Test status
Simulation time 31433154638 ps
CPU time 95.54 seconds
Started Feb 18 01:25:17 PM PST 24
Finished Feb 18 01:26:53 PM PST 24
Peak memory 214320 kb
Host smart-a0adb2dc-6449-4304-9ab3-c1d2c3ca1ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196671120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.2196671120
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.3745600788
Short name T780
Test name
Test status
Simulation time 2891130611 ps
CPU time 57.43 seconds
Started Feb 18 01:25:27 PM PST 24
Finished Feb 18 01:26:26 PM PST 24
Peak memory 296584 kb
Host smart-984447b4-02fa-41aa-b7cd-4835826dba99
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745600788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.3745600788
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3147218170
Short name T383
Test name
Test status
Simulation time 4603114164 ps
CPU time 149.81 seconds
Started Feb 18 01:25:31 PM PST 24
Finished Feb 18 01:28:02 PM PST 24
Peak memory 214580 kb
Host smart-363b3406-496f-4e50-a826-24557d23a15e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147218170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_mem_partial_access.3147218170
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.4088865873
Short name T552
Test name
Test status
Simulation time 4029695736 ps
CPU time 129.03 seconds
Started Feb 18 01:25:27 PM PST 24
Finished Feb 18 01:27:37 PM PST 24
Peak memory 202232 kb
Host smart-40b29cbd-db53-4804-87d4-488f017ba370
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088865873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.4088865873
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.1239122801
Short name T291
Test name
Test status
Simulation time 39791983835 ps
CPU time 1389.01 seconds
Started Feb 18 01:25:14 PM PST 24
Finished Feb 18 01:48:24 PM PST 24
Peak memory 378236 kb
Host smart-123c4f72-7a17-4950-b7be-4578c9a5a7ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239122801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.1239122801
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.4183329709
Short name T692
Test name
Test status
Simulation time 844262912 ps
CPU time 34.61 seconds
Started Feb 18 01:25:16 PM PST 24
Finished Feb 18 01:25:51 PM PST 24
Peak memory 267572 kb
Host smart-5b3b4fad-94a4-4aa4-9d46-1210eb987f60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183329709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.4183329709
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.490956128
Short name T170
Test name
Test status
Simulation time 28169910219 ps
CPU time 469.02 seconds
Started Feb 18 01:25:16 PM PST 24
Finished Feb 18 01:33:06 PM PST 24
Peak memory 202316 kb
Host smart-754bfc5c-f1d1-4f55-81d7-5a48265590f5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490956128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.490956128
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.965397971
Short name T299
Test name
Test status
Simulation time 369219741 ps
CPU time 13.17 seconds
Started Feb 18 01:25:31 PM PST 24
Finished Feb 18 01:25:45 PM PST 24
Peak memory 202480 kb
Host smart-3ee5cf7e-fbaf-4ce8-bcf8-813f4b8b95b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965397971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.965397971
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.2790171831
Short name T562
Test name
Test status
Simulation time 7330576118 ps
CPU time 626.55 seconds
Started Feb 18 01:25:30 PM PST 24
Finished Feb 18 01:35:58 PM PST 24
Peak memory 366904 kb
Host smart-92cd4cc3-9fa9-48fe-9f35-67b769b20eb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790171831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2790171831
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.2146183517
Short name T267
Test name
Test status
Simulation time 1198804182 ps
CPU time 27.45 seconds
Started Feb 18 01:25:16 PM PST 24
Finished Feb 18 01:25:44 PM PST 24
Peak memory 202096 kb
Host smart-130b98e2-5ec9-4a51-b35a-52b06b495e3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146183517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2146183517
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_all.4183008690
Short name T468
Test name
Test status
Simulation time 73264497886 ps
CPU time 4060.77 seconds
Started Feb 18 01:25:35 PM PST 24
Finished Feb 18 02:33:17 PM PST 24
Peak memory 373008 kb
Host smart-142f9f7f-519f-4705-8399-c773c653b919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183008690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.sram_ctrl_stress_all.4183008690
Directory /workspace/11.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1968619897
Short name T94
Test name
Test status
Simulation time 19856771859 ps
CPU time 337.78 seconds
Started Feb 18 01:25:16 PM PST 24
Finished Feb 18 01:30:55 PM PST 24
Peak memory 202272 kb
Host smart-fa48f93b-2beb-4317-98a8-8556216c1dec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968619897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.sram_ctrl_stress_pipeline.1968619897
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.768722668
Short name T297
Test name
Test status
Simulation time 1035041305 ps
CPU time 159.23 seconds
Started Feb 18 01:25:15 PM PST 24
Finished Feb 18 01:27:55 PM PST 24
Peak memory 368812 kb
Host smart-c8388499-d48c-4172-8835-dc844e327a5c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768722668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.768722668
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3237866820
Short name T294
Test name
Test status
Simulation time 46981502 ps
CPU time 0.63 seconds
Started Feb 18 01:25:43 PM PST 24
Finished Feb 18 01:25:45 PM PST 24
Peak memory 201972 kb
Host smart-f91609c6-8f50-47c4-a873-1389b9b4626f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237866820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3237866820
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.2347290538
Short name T749
Test name
Test status
Simulation time 595917231386 ps
CPU time 2291.28 seconds
Started Feb 18 01:25:33 PM PST 24
Finished Feb 18 02:03:46 PM PST 24
Peak memory 202304 kb
Host smart-d0e58816-7a8d-402e-bb1b-a9e815bcd608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347290538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.2347290538
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.2049576916
Short name T591
Test name
Test status
Simulation time 10555510496 ps
CPU time 88.31 seconds
Started Feb 18 01:25:43 PM PST 24
Finished Feb 18 01:27:12 PM PST 24
Peak memory 210468 kb
Host smart-6e466087-8b8b-4792-b280-588e5523f8d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049576916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es
calation.2049576916
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.1119653045
Short name T329
Test name
Test status
Simulation time 2943407181 ps
CPU time 45.7 seconds
Started Feb 18 01:25:41 PM PST 24
Finished Feb 18 01:26:28 PM PST 24
Peak memory 270852 kb
Host smart-06f05b62-6950-4a3b-baa1-8f88ce94e832
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119653045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.1119653045
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3448325711
Short name T287
Test name
Test status
Simulation time 18212256849 ps
CPU time 163 seconds
Started Feb 18 01:25:43 PM PST 24
Finished Feb 18 01:28:26 PM PST 24
Peak memory 214764 kb
Host smart-074e6b8e-3b3d-4e21-90b3-0994a2ba38b2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448325711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.3448325711
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.1145445567
Short name T399
Test name
Test status
Simulation time 43023853163 ps
CPU time 297.42 seconds
Started Feb 18 01:25:42 PM PST 24
Finished Feb 18 01:30:40 PM PST 24
Peak memory 202276 kb
Host smart-15bd4cb3-5e5a-437b-9e6a-12a9ad69014b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145445567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr
l_mem_walk.1145445567
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.856213237
Short name T667
Test name
Test status
Simulation time 6898196949 ps
CPU time 217.14 seconds
Started Feb 18 01:25:35 PM PST 24
Finished Feb 18 01:29:13 PM PST 24
Peak memory 359892 kb
Host smart-65eaf711-414f-4a0b-9c65-4ec2f804c4e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856213237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multip
le_keys.856213237
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.2995251259
Short name T178
Test name
Test status
Simulation time 3182279645 ps
CPU time 33.93 seconds
Started Feb 18 01:25:34 PM PST 24
Finished Feb 18 01:26:09 PM PST 24
Peak memory 202284 kb
Host smart-b45e1401-dd45-49a6-bd0e-0e4435ba1308
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995251259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.2995251259
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2831613009
Short name T570
Test name
Test status
Simulation time 5966299282 ps
CPU time 355.23 seconds
Started Feb 18 01:25:32 PM PST 24
Finished Feb 18 01:31:29 PM PST 24
Peak memory 202336 kb
Host smart-91a052f2-34df-4012-bdd5-397f8c38a70c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831613009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.sram_ctrl_partial_access_b2b.2831613009
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.3183560438
Short name T623
Test name
Test status
Simulation time 54307199606 ps
CPU time 822.08 seconds
Started Feb 18 01:25:41 PM PST 24
Finished Feb 18 01:39:24 PM PST 24
Peak memory 380196 kb
Host smart-25f8d3db-84ad-40c7-bd21-2c549a1d9f55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183560438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3183560438
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.3368563207
Short name T220
Test name
Test status
Simulation time 1481390304 ps
CPU time 48.56 seconds
Started Feb 18 01:25:35 PM PST 24
Finished Feb 18 01:26:25 PM PST 24
Peak memory 264428 kb
Host smart-941ddb71-d7c5-4612-88f1-420681f672bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368563207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3368563207
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.1922124087
Short name T496
Test name
Test status
Simulation time 268280770742 ps
CPU time 2284.03 seconds
Started Feb 18 01:25:42 PM PST 24
Finished Feb 18 02:03:47 PM PST 24
Peak memory 380192 kb
Host smart-3e3c5424-7c82-4f88-b31e-93bb923a672e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922124087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.1922124087
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3821090242
Short name T505
Test name
Test status
Simulation time 25491595060 ps
CPU time 506.49 seconds
Started Feb 18 01:25:34 PM PST 24
Finished Feb 18 01:34:02 PM PST 24
Peak memory 202312 kb
Host smart-543be674-1175-47f2-b6e7-a09b63deb4f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821090242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.3821090242
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.136092381
Short name T244
Test name
Test status
Simulation time 1595055351 ps
CPU time 110.22 seconds
Started Feb 18 01:25:41 PM PST 24
Finished Feb 18 01:27:32 PM PST 24
Peak memory 365928 kb
Host smart-90b29eb2-7cb7-403f-84fd-a80baabc3060
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136092381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_throughput_w_partial_write.136092381
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.974828359
Short name T280
Test name
Test status
Simulation time 7935201756 ps
CPU time 901.2 seconds
Started Feb 18 01:25:43 PM PST 24
Finished Feb 18 01:40:45 PM PST 24
Peak memory 376032 kb
Host smart-10cdceff-f1d6-4e76-bb07-ad56c5e64a9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974828359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 13.sram_ctrl_access_during_key_req.974828359
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.2414759771
Short name T529
Test name
Test status
Simulation time 15709713 ps
CPU time 0.64 seconds
Started Feb 18 01:25:52 PM PST 24
Finished Feb 18 01:25:54 PM PST 24
Peak memory 202068 kb
Host smart-9e4c6f6c-8065-48b7-9ceb-03374fc412df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414759771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.2414759771
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.77152710
Short name T349
Test name
Test status
Simulation time 158182605949 ps
CPU time 1755.92 seconds
Started Feb 18 01:25:45 PM PST 24
Finished Feb 18 01:55:01 PM PST 24
Peak memory 202388 kb
Host smart-b608f893-d936-4fb3-b678-11c393a5fc0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77152710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.77152710
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_lc_escalation.2538304932
Short name T633
Test name
Test status
Simulation time 106159361080 ps
CPU time 111.14 seconds
Started Feb 18 01:25:44 PM PST 24
Finished Feb 18 01:27:35 PM PST 24
Peak memory 210492 kb
Host smart-6d79c4eb-acbd-413a-aff4-e6cb4d5fa868
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538304932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es
calation.2538304932
Directory /workspace/13.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.1378422752
Short name T182
Test name
Test status
Simulation time 1560304646 ps
CPU time 180.09 seconds
Started Feb 18 01:25:46 PM PST 24
Finished Feb 18 01:28:47 PM PST 24
Peak memory 363832 kb
Host smart-6f7149ee-4cb6-422a-9efd-b12792a1e8e6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378422752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sram_ctrl_max_throughput.1378422752
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2636705678
Short name T77
Test name
Test status
Simulation time 1007573700 ps
CPU time 74.61 seconds
Started Feb 18 01:25:46 PM PST 24
Finished Feb 18 01:27:02 PM PST 24
Peak memory 211068 kb
Host smart-f24b84fb-30f9-4eba-b846-3fae92827408
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636705678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.2636705678
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.1641694587
Short name T571
Test name
Test status
Simulation time 7186136894 ps
CPU time 140.94 seconds
Started Feb 18 01:25:48 PM PST 24
Finished Feb 18 01:28:09 PM PST 24
Peak memory 202180 kb
Host smart-bb5c75d7-f284-4937-b298-39228fdd1d41
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641694587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr
l_mem_walk.1641694587
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.449513465
Short name T160
Test name
Test status
Simulation time 16519108911 ps
CPU time 690.69 seconds
Started Feb 18 01:25:46 PM PST 24
Finished Feb 18 01:37:18 PM PST 24
Peak memory 378184 kb
Host smart-1d85b276-47a5-46f4-b237-1fd00c287ff5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449513465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip
le_keys.449513465
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.1430721045
Short name T641
Test name
Test status
Simulation time 6653047420 ps
CPU time 32.8 seconds
Started Feb 18 01:25:44 PM PST 24
Finished Feb 18 01:26:18 PM PST 24
Peak memory 202144 kb
Host smart-2a7158b2-24bc-4c50-92c0-3654719b9637
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430721045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
sram_ctrl_partial_access.1430721045
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3713906466
Short name T1
Test name
Test status
Simulation time 122697162234 ps
CPU time 305.85 seconds
Started Feb 18 01:25:43 PM PST 24
Finished Feb 18 01:30:50 PM PST 24
Peak memory 202232 kb
Host smart-86f114f6-a402-4fec-b0ec-c06e398cd115
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713906466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.3713906466
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.1916647230
Short name T381
Test name
Test status
Simulation time 889631935 ps
CPU time 6.64 seconds
Started Feb 18 01:25:45 PM PST 24
Finished Feb 18 01:25:52 PM PST 24
Peak memory 202424 kb
Host smart-cd97c6d2-4387-4333-a2e4-9d8dab3ef9a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916647230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.1916647230
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.747890613
Short name T437
Test name
Test status
Simulation time 3370961238 ps
CPU time 820.66 seconds
Started Feb 18 01:25:45 PM PST 24
Finished Feb 18 01:39:26 PM PST 24
Peak memory 371060 kb
Host smart-ce7764a1-0e7d-427d-82ee-291ce7f5c831
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747890613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.747890613
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.3260254986
Short name T441
Test name
Test status
Simulation time 5083247724 ps
CPU time 130.43 seconds
Started Feb 18 01:25:42 PM PST 24
Finished Feb 18 01:27:53 PM PST 24
Peak memory 364820 kb
Host smart-a11c306e-057f-412f-aac7-06b33f584441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260254986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3260254986
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1176524372
Short name T385
Test name
Test status
Simulation time 6196621198 ps
CPU time 234.55 seconds
Started Feb 18 01:25:45 PM PST 24
Finished Feb 18 01:29:40 PM PST 24
Peak memory 202304 kb
Host smart-ba4f62ca-b0c7-4b71-b8d5-62bed5163db1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176524372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.1176524372
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.2652406514
Short name T161
Test name
Test status
Simulation time 2898313116 ps
CPU time 47.67 seconds
Started Feb 18 01:25:45 PM PST 24
Finished Feb 18 01:26:34 PM PST 24
Peak memory 284112 kb
Host smart-da679d02-b72b-4836-8234-869093667e00
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652406514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.2652406514
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1990831971
Short name T16
Test name
Test status
Simulation time 20968668533 ps
CPU time 1281.96 seconds
Started Feb 18 01:25:59 PM PST 24
Finished Feb 18 01:47:21 PM PST 24
Peak memory 379192 kb
Host smart-ab486b8b-e835-403c-9e47-b8f5d0a6c5cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990831971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1990831971
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.1093052922
Short name T321
Test name
Test status
Simulation time 67607573 ps
CPU time 0.62 seconds
Started Feb 18 01:26:07 PM PST 24
Finished Feb 18 01:26:08 PM PST 24
Peak memory 201728 kb
Host smart-a7e93827-d016-44e1-8ccf-fa6fcc61d577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093052922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.1093052922
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.3470208542
Short name T322
Test name
Test status
Simulation time 20022432797 ps
CPU time 1431.56 seconds
Started Feb 18 01:25:56 PM PST 24
Finished Feb 18 01:49:48 PM PST 24
Peak memory 202368 kb
Host smart-91bf9e5b-2862-4dcb-bcb6-693ebe429deb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470208542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.3470208542
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.400189085
Short name T547
Test name
Test status
Simulation time 33740078798 ps
CPU time 204.73 seconds
Started Feb 18 01:26:01 PM PST 24
Finished Feb 18 01:29:27 PM PST 24
Peak memory 210524 kb
Host smart-0db47ba3-bbf4-4027-baeb-74fa8aea99fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400189085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_esc
alation.400189085
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.1671488451
Short name T137
Test name
Test status
Simulation time 771226021 ps
CPU time 119.16 seconds
Started Feb 18 01:25:52 PM PST 24
Finished Feb 18 01:27:53 PM PST 24
Peak memory 357576 kb
Host smart-e6aa179b-4d35-4c18-b5ec-46d4d248c6f9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671488451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sram_ctrl_max_throughput.1671488451
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2980787207
Short name T538
Test name
Test status
Simulation time 1358647262 ps
CPU time 74.79 seconds
Started Feb 18 01:26:08 PM PST 24
Finished Feb 18 01:27:23 PM PST 24
Peak memory 210652 kb
Host smart-f62662bd-95f9-41eb-8305-4d997a69d1d9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980787207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.2980787207
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.1803416831
Short name T765
Test name
Test status
Simulation time 40694888668 ps
CPU time 159.74 seconds
Started Feb 18 01:26:00 PM PST 24
Finished Feb 18 01:28:40 PM PST 24
Peak memory 202360 kb
Host smart-48c4d3e2-97eb-44f4-b6e0-217db078520e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803416831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.1803416831
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.83945682
Short name T70
Test name
Test status
Simulation time 7903867434 ps
CPU time 502.1 seconds
Started Feb 18 01:25:54 PM PST 24
Finished Feb 18 01:34:17 PM PST 24
Peak memory 375096 kb
Host smart-432e3e98-d6d9-4a5b-a60f-273d25974511
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83945682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multipl
e_keys.83945682
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.736984224
Short name T456
Test name
Test status
Simulation time 511316594 ps
CPU time 22.24 seconds
Started Feb 18 01:25:53 PM PST 24
Finished Feb 18 01:26:16 PM PST 24
Peak memory 202212 kb
Host smart-8071fa29-4f6a-48ca-8f17-d4ec3443220e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736984224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_partial_access.736984224
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3395577150
Short name T674
Test name
Test status
Simulation time 63136653461 ps
CPU time 386.86 seconds
Started Feb 18 01:25:54 PM PST 24
Finished Feb 18 01:32:22 PM PST 24
Peak memory 202284 kb
Host smart-1c215dcd-c387-4c9d-8025-35a54c7eb6bd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395577150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.3395577150
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.3638706925
Short name T415
Test name
Test status
Simulation time 1880896114 ps
CPU time 6.63 seconds
Started Feb 18 01:26:02 PM PST 24
Finished Feb 18 01:26:09 PM PST 24
Peak memory 202440 kb
Host smart-0cb83c86-15d4-4a46-9e00-06b9d97dc7ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638706925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3638706925
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.2363078812
Short name T446
Test name
Test status
Simulation time 48442864596 ps
CPU time 1081.18 seconds
Started Feb 18 01:26:00 PM PST 24
Finished Feb 18 01:44:02 PM PST 24
Peak memory 380164 kb
Host smart-16f422d3-e5ff-473d-96bb-9ee3a9e9b415
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363078812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2363078812
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.2241813294
Short name T172
Test name
Test status
Simulation time 1886477617 ps
CPU time 22.9 seconds
Started Feb 18 01:25:59 PM PST 24
Finished Feb 18 01:26:22 PM PST 24
Peak memory 202208 kb
Host smart-d3ffc51e-b81f-4a82-9f3f-9a7c91a5e7a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241813294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2241813294
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.4014281306
Short name T827
Test name
Test status
Simulation time 7958483211 ps
CPU time 332.75 seconds
Started Feb 18 01:25:53 PM PST 24
Finished Feb 18 01:31:26 PM PST 24
Peak memory 202304 kb
Host smart-1ce2bc95-2c62-4a43-8957-4e0af498fa32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014281306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.4014281306
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3238171183
Short name T452
Test name
Test status
Simulation time 710631954 ps
CPU time 30.33 seconds
Started Feb 18 01:25:55 PM PST 24
Finished Feb 18 01:26:26 PM PST 24
Peak memory 222356 kb
Host smart-5aa80c87-b5b1-42e5-a760-79b62b144fc2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238171183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3238171183
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3282644953
Short name T288
Test name
Test status
Simulation time 5940790112 ps
CPU time 885.44 seconds
Started Feb 18 01:26:08 PM PST 24
Finished Feb 18 01:40:54 PM PST 24
Peak memory 373256 kb
Host smart-e06bfa0e-62d8-4f39-8313-3b64b293d8cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282644953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.sram_ctrl_access_during_key_req.3282644953
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.3241074717
Short name T339
Test name
Test status
Simulation time 172376663669 ps
CPU time 2933.47 seconds
Started Feb 18 01:26:08 PM PST 24
Finished Feb 18 02:15:03 PM PST 24
Peak memory 202288 kb
Host smart-006ebc06-9a7f-448f-a377-ee2868a7ef86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241074717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.3241074717
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.2959912979
Short name T255
Test name
Test status
Simulation time 28137458416 ps
CPU time 1812.5 seconds
Started Feb 18 01:26:17 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 378156 kb
Host smart-262b475c-d05a-46a3-aa35-1f21337c463e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959912979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.2959912979
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.239198425
Short name T242
Test name
Test status
Simulation time 1330992749 ps
CPU time 28.25 seconds
Started Feb 18 01:26:08 PM PST 24
Finished Feb 18 01:26:37 PM PST 24
Peak memory 210444 kb
Host smart-bd8dede9-86c8-4e44-a274-649ff45deb0b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239198425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.sram_ctrl_max_throughput.239198425
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.3352148626
Short name T260
Test name
Test status
Simulation time 4525908865 ps
CPU time 137.4 seconds
Started Feb 18 01:26:17 PM PST 24
Finished Feb 18 01:28:35 PM PST 24
Peak memory 218608 kb
Host smart-d3eb6038-6a29-4a35-acb8-abc16e4c5fc3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352148626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_mem_partial_access.3352148626
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.686059945
Short name T593
Test name
Test status
Simulation time 4699682728 ps
CPU time 126.77 seconds
Started Feb 18 01:26:20 PM PST 24
Finished Feb 18 01:28:27 PM PST 24
Peak memory 202724 kb
Host smart-7fa54d0a-8eb2-442f-bb79-9c6a1b10e471
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686059945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_mem_walk.686059945
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.3263434786
Short name T691
Test name
Test status
Simulation time 70878932630 ps
CPU time 1459.2 seconds
Started Feb 18 01:26:07 PM PST 24
Finished Feb 18 01:50:27 PM PST 24
Peak memory 374972 kb
Host smart-d5d5e0f1-3436-47e3-9de6-876a23308640
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263434786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi
ple_keys.3263434786
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.424050166
Short name T682
Test name
Test status
Simulation time 4652251014 ps
CPU time 65.38 seconds
Started Feb 18 01:26:09 PM PST 24
Finished Feb 18 01:27:15 PM PST 24
Peak memory 312728 kb
Host smart-39778afc-65b0-4c70-b358-57596da55f59
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424050166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.s
ram_ctrl_partial_access.424050166
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3525247090
Short name T154
Test name
Test status
Simulation time 18311822164 ps
CPU time 292.17 seconds
Started Feb 18 01:26:06 PM PST 24
Finished Feb 18 01:30:59 PM PST 24
Peak memory 202312 kb
Host smart-39782ae0-31b9-4d8c-82b4-ac973f314c85
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525247090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.3525247090
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.621472210
Short name T453
Test name
Test status
Simulation time 357027714 ps
CPU time 13.92 seconds
Started Feb 18 01:26:17 PM PST 24
Finished Feb 18 01:26:32 PM PST 24
Peak memory 202480 kb
Host smart-a921def0-057e-47cf-a9ac-21fb5d173e17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621472210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.621472210
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.869262576
Short name T436
Test name
Test status
Simulation time 19658134802 ps
CPU time 824.65 seconds
Started Feb 18 01:26:17 PM PST 24
Finished Feb 18 01:40:03 PM PST 24
Peak memory 372960 kb
Host smart-26375fa3-35c7-4a1b-9647-02106dc1d207
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869262576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.869262576
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.1599368111
Short name T746
Test name
Test status
Simulation time 584362941 ps
CPU time 7.47 seconds
Started Feb 18 01:26:10 PM PST 24
Finished Feb 18 01:26:18 PM PST 24
Peak memory 202464 kb
Host smart-1191a85a-4580-49e5-932d-d287bbccda1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599368111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1599368111
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.3487532569
Short name T461
Test name
Test status
Simulation time 319719197250 ps
CPU time 2936.53 seconds
Started Feb 18 01:26:18 PM PST 24
Finished Feb 18 02:15:16 PM PST 24
Peak memory 370928 kb
Host smart-7ba8e2c4-edc7-4226-915c-80e4b5962b92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487532569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.3487532569
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.3502197104
Short name T158
Test name
Test status
Simulation time 13649356719 ps
CPU time 155.62 seconds
Started Feb 18 01:26:08 PM PST 24
Finished Feb 18 01:28:45 PM PST 24
Peak memory 202316 kb
Host smart-db0a430e-9ff9-421b-a1f0-ad9415dc5e10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502197104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.3502197104
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2104941753
Short name T132
Test name
Test status
Simulation time 1435550807 ps
CPU time 42.72 seconds
Started Feb 18 01:26:08 PM PST 24
Finished Feb 18 01:26:51 PM PST 24
Peak memory 267648 kb
Host smart-cee6ea72-daaf-4765-b828-45f32cd7121e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104941753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2104941753
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.740385166
Short name T175
Test name
Test status
Simulation time 31471830292 ps
CPU time 806.22 seconds
Started Feb 18 01:26:24 PM PST 24
Finished Feb 18 01:39:51 PM PST 24
Peak memory 358760 kb
Host smart-4b4d1245-c2e2-4128-aaba-2cfe3635a5f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740385166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 16.sram_ctrl_access_during_key_req.740385166
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.3452389826
Short name T754
Test name
Test status
Simulation time 30104433 ps
CPU time 0.6 seconds
Started Feb 18 01:26:20 PM PST 24
Finished Feb 18 01:26:21 PM PST 24
Peak memory 202032 kb
Host smart-d6ffcb1a-8fd0-428d-aad0-7a3c9038de68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452389826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.3452389826
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.3624909677
Short name T798
Test name
Test status
Simulation time 16655577714 ps
CPU time 408.76 seconds
Started Feb 18 01:26:29 PM PST 24
Finished Feb 18 01:33:19 PM PST 24
Peak memory 369108 kb
Host smart-8bf9b842-a4c9-4a1e-9b94-0b29542c9ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624909677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab
le.3624909677
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.502636254
Short name T564
Test name
Test status
Simulation time 11078126408 ps
CPU time 267.42 seconds
Started Feb 18 01:26:25 PM PST 24
Finished Feb 18 01:30:53 PM PST 24
Peak memory 214760 kb
Host smart-2a412923-f9ee-4e36-b3d7-15477702e736
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502636254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_esc
alation.502636254
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.2613843168
Short name T721
Test name
Test status
Simulation time 3098375372 ps
CPU time 91.36 seconds
Started Feb 18 01:26:21 PM PST 24
Finished Feb 18 01:27:53 PM PST 24
Peak memory 335400 kb
Host smart-5d447985-4ba5-4703-91d3-21b4c4b6875b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613843168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.2613843168
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.77051426
Short name T78
Test name
Test status
Simulation time 2490915332 ps
CPU time 74.27 seconds
Started Feb 18 01:26:21 PM PST 24
Finished Feb 18 01:27:36 PM PST 24
Peak memory 210392 kb
Host smart-0c432e39-a44e-48c8-b511-c7cdf68d95d7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77051426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_mem_partial_access.77051426
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.362951015
Short name T751
Test name
Test status
Simulation time 10341757577 ps
CPU time 150.32 seconds
Started Feb 18 01:26:20 PM PST 24
Finished Feb 18 01:28:51 PM PST 24
Peak memory 202252 kb
Host smart-43e5d5ba-6b36-4a73-b9f3-739362bae923
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362951015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_mem_walk.362951015
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.3046519279
Short name T551
Test name
Test status
Simulation time 16953836072 ps
CPU time 826.28 seconds
Started Feb 18 01:26:16 PM PST 24
Finished Feb 18 01:40:03 PM PST 24
Peak memory 377156 kb
Host smart-fd9e048e-e485-45cc-8d02-b55795776bcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046519279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.3046519279
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2955476664
Short name T355
Test name
Test status
Simulation time 5779719514 ps
CPU time 30.16 seconds
Started Feb 18 01:26:16 PM PST 24
Finished Feb 18 01:26:47 PM PST 24
Peak memory 202216 kb
Host smart-ba3f52ea-73d6-438c-8705-18af360caa44
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955476664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2955476664
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3678470241
Short name T268
Test name
Test status
Simulation time 27163799897 ps
CPU time 446.26 seconds
Started Feb 18 01:26:17 PM PST 24
Finished Feb 18 01:33:44 PM PST 24
Peak memory 202244 kb
Host smart-47c90133-62a6-458b-937d-16461c3da4dd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678470241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 16.sram_ctrl_partial_access_b2b.3678470241
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.1438102287
Short name T669
Test name
Test status
Simulation time 362630972 ps
CPU time 6.43 seconds
Started Feb 18 01:26:26 PM PST 24
Finished Feb 18 01:26:33 PM PST 24
Peak memory 202348 kb
Host smart-39e0dce1-e5a1-4b04-9e7b-4c3bcbc37c08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438102287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1438102287
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.53994712
Short name T351
Test name
Test status
Simulation time 10756109522 ps
CPU time 772.77 seconds
Started Feb 18 01:26:20 PM PST 24
Finished Feb 18 01:39:13 PM PST 24
Peak memory 375136 kb
Host smart-ed9e5b6a-4492-49e5-80e0-d045868a7e8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53994712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.53994712
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.1620725376
Short name T724
Test name
Test status
Simulation time 3036026298 ps
CPU time 73.37 seconds
Started Feb 18 01:26:20 PM PST 24
Finished Feb 18 01:27:34 PM PST 24
Peak memory 299264 kb
Host smart-b3f2c1b4-8a54-4d79-a8c5-ca878edbf6c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620725376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1620725376
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.2572548732
Short name T506
Test name
Test status
Simulation time 353211418685 ps
CPU time 5144.53 seconds
Started Feb 18 01:26:24 PM PST 24
Finished Feb 18 02:52:09 PM PST 24
Peak memory 387308 kb
Host smart-1b5584f5-5a92-4bbf-8ea5-eaf6cf46636f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572548732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.2572548732
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.3918250864
Short name T656
Test name
Test status
Simulation time 17413892592 ps
CPU time 312.19 seconds
Started Feb 18 01:26:17 PM PST 24
Finished Feb 18 01:31:30 PM PST 24
Peak memory 202300 kb
Host smart-a56700c5-46da-486d-9f2d-069b04481fae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918250864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.3918250864
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.282415915
Short name T491
Test name
Test status
Simulation time 789896172 ps
CPU time 156.54 seconds
Started Feb 18 01:26:22 PM PST 24
Finished Feb 18 01:28:59 PM PST 24
Peak memory 372940 kb
Host smart-dbecb8a1-c7f6-4a24-a9ca-63e0bc7ffad5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282415915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.282415915
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2137268612
Short name T305
Test name
Test status
Simulation time 23869377453 ps
CPU time 994.38 seconds
Started Feb 18 01:26:31 PM PST 24
Finished Feb 18 01:43:06 PM PST 24
Peak memory 378416 kb
Host smart-b5c881d2-8a5b-424b-b192-330842f64943
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137268612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.2137268612
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.4032267192
Short name T352
Test name
Test status
Simulation time 33082809 ps
CPU time 0.67 seconds
Started Feb 18 01:26:39 PM PST 24
Finished Feb 18 01:26:40 PM PST 24
Peak memory 201936 kb
Host smart-f341577d-7672-4756-a316-9264d412bacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032267192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.4032267192
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.1488419636
Short name T755
Test name
Test status
Simulation time 197296082781 ps
CPU time 2298.09 seconds
Started Feb 18 01:26:29 PM PST 24
Finished Feb 18 02:04:48 PM PST 24
Peak memory 202296 kb
Host smart-2f06517b-6978-4f19-92e2-7b203fea64e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488419636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.1488419636
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.2574024983
Short name T328
Test name
Test status
Simulation time 9846353323 ps
CPU time 567.02 seconds
Started Feb 18 01:26:37 PM PST 24
Finished Feb 18 01:36:05 PM PST 24
Peak memory 377848 kb
Host smart-baff49d4-0d73-4fde-8a6e-465fad287b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574024983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.2574024983
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_lc_escalation.3960092581
Short name T245
Test name
Test status
Simulation time 26221321029 ps
CPU time 89.68 seconds
Started Feb 18 01:26:31 PM PST 24
Finished Feb 18 01:28:01 PM PST 24
Peak memory 210508 kb
Host smart-90b9858e-9e29-4689-b7ee-63b98152be9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960092581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es
calation.3960092581
Directory /workspace/17.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.1524049742
Short name T535
Test name
Test status
Simulation time 874347397 ps
CPU time 57.17 seconds
Started Feb 18 01:26:32 PM PST 24
Finished Feb 18 01:27:30 PM PST 24
Peak memory 294180 kb
Host smart-ec91791d-ca5e-4cea-b19d-09555361e001
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524049742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.1524049742
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3565282918
Short name T834
Test name
Test status
Simulation time 22980828672 ps
CPU time 157.47 seconds
Started Feb 18 01:26:43 PM PST 24
Finished Feb 18 01:29:22 PM PST 24
Peak memory 211256 kb
Host smart-f43b76ed-2985-4ee3-b19b-fbc5d5acaa47
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565282918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.3565282918
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.2775604348
Short name T285
Test name
Test status
Simulation time 4023922126 ps
CPU time 248.25 seconds
Started Feb 18 01:26:38 PM PST 24
Finished Feb 18 01:30:47 PM PST 24
Peak memory 202240 kb
Host smart-291792b0-9052-440a-8516-9d823dd084a1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775604348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr
l_mem_walk.2775604348
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.3026636381
Short name T372
Test name
Test status
Simulation time 24397280079 ps
CPU time 1662.31 seconds
Started Feb 18 01:26:26 PM PST 24
Finished Feb 18 01:54:09 PM PST 24
Peak memory 378044 kb
Host smart-99e9a5ff-3ebf-4176-a819-6f73bff061c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026636381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi
ple_keys.3026636381
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.3217688036
Short name T396
Test name
Test status
Simulation time 795205162 ps
CPU time 32.29 seconds
Started Feb 18 01:26:33 PM PST 24
Finished Feb 18 01:27:05 PM PST 24
Peak memory 202152 kb
Host smart-33887fe2-9745-42d2-9bba-8f34c6ab829b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217688036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
sram_ctrl_partial_access.3217688036
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2597084333
Short name T683
Test name
Test status
Simulation time 15007308532 ps
CPU time 380.85 seconds
Started Feb 18 01:26:31 PM PST 24
Finished Feb 18 01:32:52 PM PST 24
Peak memory 202228 kb
Host smart-3cf98879-2f59-4a89-802a-22b8a9be3b85
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597084333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.sram_ctrl_partial_access_b2b.2597084333
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.532877431
Short name T504
Test name
Test status
Simulation time 738707971 ps
CPU time 6.34 seconds
Started Feb 18 01:26:36 PM PST 24
Finished Feb 18 01:26:42 PM PST 24
Peak memory 202384 kb
Host smart-537d2bd3-3f3f-44ce-82a7-d9b73ec2ae97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532877431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.532877431
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.1389175546
Short name T423
Test name
Test status
Simulation time 3693137749 ps
CPU time 1336.84 seconds
Started Feb 18 01:26:39 PM PST 24
Finished Feb 18 01:48:56 PM PST 24
Peak memory 379240 kb
Host smart-65c7e119-a664-4362-8be3-2ff94b3c1f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389175546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1389175546
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.948431080
Short name T655
Test name
Test status
Simulation time 3156429706 ps
CPU time 134.15 seconds
Started Feb 18 01:26:29 PM PST 24
Finished Feb 18 01:28:44 PM PST 24
Peak memory 339320 kb
Host smart-de07c3a3-bd5e-4b07-ade2-c1c2c0becb0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948431080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.948431080
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3151880732
Short name T716
Test name
Test status
Simulation time 5351358376 ps
CPU time 164.46 seconds
Started Feb 18 01:26:25 PM PST 24
Finished Feb 18 01:29:10 PM PST 24
Peak memory 202328 kb
Host smart-8ac6680f-1a68-4986-98f1-ae5834e27423
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151880732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.3151880732
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.30798527
Short name T266
Test name
Test status
Simulation time 803216982 ps
CPU time 129.26 seconds
Started Feb 18 01:26:37 PM PST 24
Finished Feb 18 01:28:47 PM PST 24
Peak memory 340196 kb
Host smart-569f12d3-136d-4f8f-b3b2-9f6b46ec123d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30798527 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.sram_ctrl_throughput_w_partial_write.30798527
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2058665444
Short name T180
Test name
Test status
Simulation time 18322391482 ps
CPU time 1123.02 seconds
Started Feb 18 01:26:50 PM PST 24
Finished Feb 18 01:45:34 PM PST 24
Peak memory 376128 kb
Host smart-ce5211ad-4324-49ed-9f50-de659920b259
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058665444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.2058665444
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.2345054590
Short name T794
Test name
Test status
Simulation time 44996048 ps
CPU time 0.68 seconds
Started Feb 18 01:26:53 PM PST 24
Finished Feb 18 01:26:55 PM PST 24
Peak memory 202040 kb
Host smart-f997451b-0da2-4aec-b0a2-37e019f91843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345054590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.2345054590
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.67338809
Short name T317
Test name
Test status
Simulation time 43243805724 ps
CPU time 665.33 seconds
Started Feb 18 01:26:36 PM PST 24
Finished Feb 18 01:37:42 PM PST 24
Peak memory 202400 kb
Host smart-1c45d47c-1532-41a1-a207-5ae2d5166e87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67338809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.67338809
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_lc_escalation.4190950236
Short name T609
Test name
Test status
Simulation time 4168908696 ps
CPU time 13.82 seconds
Started Feb 18 01:26:51 PM PST 24
Finished Feb 18 01:27:06 PM PST 24
Peak memory 202276 kb
Host smart-964a5cba-3544-4407-ab4e-cbcb7767a972
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190950236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_es
calation.4190950236
Directory /workspace/18.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.263488446
Short name T465
Test name
Test status
Simulation time 2963783872 ps
CPU time 48.47 seconds
Started Feb 18 01:26:50 PM PST 24
Finished Feb 18 01:27:39 PM PST 24
Peak memory 276672 kb
Host smart-4be47232-1182-4725-b7e7-bd035cc1b71f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263488446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.sram_ctrl_max_throughput.263488446
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.4254546359
Short name T770
Test name
Test status
Simulation time 3626298315 ps
CPU time 75.46 seconds
Started Feb 18 01:26:59 PM PST 24
Finished Feb 18 01:28:15 PM PST 24
Peak memory 211336 kb
Host smart-ee6192e3-f2c3-4ada-9575-b593ce144bdc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254546359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.4254546359
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.2118497467
Short name T796
Test name
Test status
Simulation time 2994731229 ps
CPU time 119.83 seconds
Started Feb 18 01:26:53 PM PST 24
Finished Feb 18 01:28:53 PM PST 24
Peak memory 202188 kb
Host smart-84c2901b-689a-4672-91e7-06c0900bda44
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118497467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.2118497467
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.3122430023
Short name T347
Test name
Test status
Simulation time 4824668000 ps
CPU time 317.09 seconds
Started Feb 18 01:26:37 PM PST 24
Finished Feb 18 01:31:55 PM PST 24
Peak memory 330116 kb
Host smart-0f46d1b0-9162-4545-bed9-e133a2736b0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122430023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.3122430023
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.2041553112
Short name T139
Test name
Test status
Simulation time 4453454874 ps
CPU time 179.74 seconds
Started Feb 18 01:26:40 PM PST 24
Finished Feb 18 01:29:40 PM PST 24
Peak memory 373848 kb
Host smart-60ac1adb-b5b4-4ccb-8e74-517605a60084
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041553112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
sram_ctrl_partial_access.2041553112
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1430039045
Short name T455
Test name
Test status
Simulation time 23655895474 ps
CPU time 552.97 seconds
Started Feb 18 01:26:44 PM PST 24
Finished Feb 18 01:35:58 PM PST 24
Peak memory 202144 kb
Host smart-02307ab0-9833-461a-b70f-c3b65e1f2496
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430039045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.1430039045
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.996680782
Short name T221
Test name
Test status
Simulation time 355430374 ps
CPU time 14.65 seconds
Started Feb 18 01:26:51 PM PST 24
Finished Feb 18 01:27:06 PM PST 24
Peak memory 202504 kb
Host smart-ba64b414-2b8a-4ea9-aa36-f63ed47b7377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996680782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.996680782
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.502035867
Short name T323
Test name
Test status
Simulation time 1481895900 ps
CPU time 292.87 seconds
Started Feb 18 01:26:53 PM PST 24
Finished Feb 18 01:31:47 PM PST 24
Peak memory 372012 kb
Host smart-c618060d-3342-4184-9236-1245a09791b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502035867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.502035867
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.3560803502
Short name T356
Test name
Test status
Simulation time 2159858794 ps
CPU time 19.91 seconds
Started Feb 18 01:26:37 PM PST 24
Finished Feb 18 01:26:57 PM PST 24
Peak memory 253664 kb
Host smart-ea9dd08d-2716-4718-a032-3c963dde7c8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560803502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3560803502
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.439214470
Short name T375
Test name
Test status
Simulation time 3674337716 ps
CPU time 231.78 seconds
Started Feb 18 01:26:37 PM PST 24
Finished Feb 18 01:30:30 PM PST 24
Peak memory 202392 kb
Host smart-2fc60498-7dad-462e-8389-2a7a943c8133
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439214470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.sram_ctrl_stress_pipeline.439214470
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2609520844
Short name T159
Test name
Test status
Simulation time 779498150 ps
CPU time 62.28 seconds
Started Feb 18 01:26:51 PM PST 24
Finished Feb 18 01:27:54 PM PST 24
Peak memory 314636 kb
Host smart-af430f02-9a34-405d-ac88-8b7b5eaf7414
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609520844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.2609520844
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3553648011
Short name T236
Test name
Test status
Simulation time 9047267260 ps
CPU time 1141.2 seconds
Started Feb 18 01:27:05 PM PST 24
Finished Feb 18 01:46:07 PM PST 24
Peak memory 378152 kb
Host smart-ba6811e1-4cc6-4f31-bdd6-7b496a76fdc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553648011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.3553648011
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.4245373986
Short name T417
Test name
Test status
Simulation time 11827353 ps
CPU time 0.62 seconds
Started Feb 18 01:27:11 PM PST 24
Finished Feb 18 01:27:13 PM PST 24
Peak memory 201996 kb
Host smart-3350c6a5-d8a6-4c03-a4fa-4fe6ab99ea3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245373986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.4245373986
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.3955785176
Short name T687
Test name
Test status
Simulation time 268928760230 ps
CPU time 1510.78 seconds
Started Feb 18 01:27:00 PM PST 24
Finished Feb 18 01:52:12 PM PST 24
Peak memory 202252 kb
Host smart-64fe08f6-7018-4330-a37d-a5cec8d2134b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955785176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.3955785176
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.2161334697
Short name T250
Test name
Test status
Simulation time 23140665463 ps
CPU time 70.99 seconds
Started Feb 18 01:27:06 PM PST 24
Finished Feb 18 01:28:17 PM PST 24
Peak memory 213860 kb
Host smart-1cf88cf2-6df5-4fa4-8361-24d5ceda7910
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161334697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.2161334697
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.2898198657
Short name T715
Test name
Test status
Simulation time 799258784 ps
CPU time 125.12 seconds
Started Feb 18 01:26:53 PM PST 24
Finished Feb 18 01:28:59 PM PST 24
Peak memory 360452 kb
Host smart-82be47e9-a096-4118-a4fd-e8c8820d9a8b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898198657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sram_ctrl_max_throughput.2898198657
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.3934781986
Short name T76
Test name
Test status
Simulation time 18252699633 ps
CPU time 155.6 seconds
Started Feb 18 01:27:08 PM PST 24
Finished Feb 18 01:29:44 PM PST 24
Peak memory 214584 kb
Host smart-ef30fc67-f70e-4be0-a520-005548b692bb
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934781986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_mem_partial_access.3934781986
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.1374924310
Short name T390
Test name
Test status
Simulation time 15766640116 ps
CPU time 240.72 seconds
Started Feb 18 01:27:05 PM PST 24
Finished Feb 18 01:31:06 PM PST 24
Peak memory 202708 kb
Host smart-030c98a8-e48b-4c2c-af41-abff59405ee6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374924310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr
l_mem_walk.1374924310
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.263315456
Short name T127
Test name
Test status
Simulation time 28912326019 ps
CPU time 332.49 seconds
Started Feb 18 01:26:54 PM PST 24
Finished Feb 18 01:32:28 PM PST 24
Peak memory 373052 kb
Host smart-6b87d343-2888-41ea-9819-9b85fd0f7cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263315456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip
le_keys.263315456
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.1945084583
Short name T224
Test name
Test status
Simulation time 3368276582 ps
CPU time 89.34 seconds
Started Feb 18 01:26:54 PM PST 24
Finished Feb 18 01:28:25 PM PST 24
Peak memory 336076 kb
Host smart-6561659d-4e40-41f1-8312-a9b72449349a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945084583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.1945084583
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.2025790023
Short name T148
Test name
Test status
Simulation time 70723414617 ps
CPU time 458.14 seconds
Started Feb 18 01:26:58 PM PST 24
Finished Feb 18 01:34:37 PM PST 24
Peak memory 202220 kb
Host smart-4f760123-b577-43c5-9131-70609ee4af3c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025790023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.2025790023
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.935960281
Short name T324
Test name
Test status
Simulation time 643821993 ps
CPU time 6.09 seconds
Started Feb 18 01:27:06 PM PST 24
Finished Feb 18 01:27:13 PM PST 24
Peak memory 202464 kb
Host smart-f7cf0e1f-f6af-49c9-b709-0326eb39ccda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935960281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.935960281
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.692252192
Short name T124
Test name
Test status
Simulation time 5448394473 ps
CPU time 708.23 seconds
Started Feb 18 01:27:13 PM PST 24
Finished Feb 18 01:39:02 PM PST 24
Peak memory 378184 kb
Host smart-8c2804ff-7824-44a8-8dc9-c803dbfb698a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692252192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.692252192
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.916642577
Short name T249
Test name
Test status
Simulation time 915615115 ps
CPU time 20.94 seconds
Started Feb 18 01:26:58 PM PST 24
Finished Feb 18 01:27:20 PM PST 24
Peak memory 202100 kb
Host smart-34c37ba0-a513-4002-8d62-91bf3565aff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916642577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.916642577
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.1412699348
Short name T270
Test name
Test status
Simulation time 8251684305 ps
CPU time 304.94 seconds
Started Feb 18 01:26:51 PM PST 24
Finished Feb 18 01:31:57 PM PST 24
Peak memory 202300 kb
Host smart-d585f106-99bc-4b65-990b-4d86aa356a4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412699348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.1412699348
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1937643384
Short name T394
Test name
Test status
Simulation time 3097647999 ps
CPU time 31.02 seconds
Started Feb 18 01:27:12 PM PST 24
Finished Feb 18 01:27:45 PM PST 24
Peak memory 224352 kb
Host smart-2ed1116e-8c08-4d0e-bfc8-ffb189e65fe4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937643384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1937643384
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.811405532
Short name T272
Test name
Test status
Simulation time 10357300507 ps
CPU time 1178.9 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:44:00 PM PST 24
Peak memory 380160 kb
Host smart-7ce80a73-7bd8-4ee6-abd4-1d027abfa662
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811405532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.sram_ctrl_access_during_key_req.811405532
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.3633686904
Short name T283
Test name
Test status
Simulation time 40850626 ps
CPU time 0.65 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:24:22 PM PST 24
Peak memory 201736 kb
Host smart-4f72ae91-90cf-4b3e-b766-c536b96ef49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633686904 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.3633686904
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.2033421137
Short name T432
Test name
Test status
Simulation time 313277019446 ps
CPU time 1785.53 seconds
Started Feb 18 01:24:02 PM PST 24
Finished Feb 18 01:53:48 PM PST 24
Peak memory 202272 kb
Host smart-52443e69-15fa-4a1e-a1e2-4883ca5b1f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033421137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
2033421137
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.122886594
Short name T748
Test name
Test status
Simulation time 25281241823 ps
CPU time 930.77 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:39:50 PM PST 24
Peak memory 378200 kb
Host smart-08325ead-4a3d-48a3-bb47-ed7c5fcaf25c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122886594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable
.122886594
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.1453999049
Short name T276
Test name
Test status
Simulation time 732978079 ps
CPU time 42.77 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:25:03 PM PST 24
Peak memory 252680 kb
Host smart-6d5950f2-d6fd-4e80-897d-d25549ecbcae
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453999049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.1453999049
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.988274950
Short name T83
Test name
Test status
Simulation time 11634827341 ps
CPU time 147.46 seconds
Started Feb 18 01:24:16 PM PST 24
Finished Feb 18 01:26:45 PM PST 24
Peak memory 211256 kb
Host smart-0e683a41-16db-4059-9e2e-27af0be87af9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988274950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
sram_ctrl_mem_partial_access.988274950
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.2208674589
Short name T747
Test name
Test status
Simulation time 10899037197 ps
CPU time 150.92 seconds
Started Feb 18 01:24:17 PM PST 24
Finished Feb 18 01:26:49 PM PST 24
Peak memory 202356 kb
Host smart-865f8abf-fbb5-4a32-ba7e-46c1359792ce
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208674589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.2208674589
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.3078868242
Short name T700
Test name
Test status
Simulation time 72003322010 ps
CPU time 1125.68 seconds
Started Feb 18 01:24:07 PM PST 24
Finished Feb 18 01:42:55 PM PST 24
Peak memory 378132 kb
Host smart-0b715061-c065-4ebe-b0e5-3304c6f5de2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078868242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.3078868242
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.1230151183
Short name T365
Test name
Test status
Simulation time 902124642 ps
CPU time 17.14 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:24:37 PM PST 24
Peak memory 221368 kb
Host smart-7f4216e8-0058-454b-a61c-446e7dc6187e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230151183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.1230151183
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3668739075
Short name T241
Test name
Test status
Simulation time 100972221405 ps
CPU time 592.08 seconds
Started Feb 18 01:24:17 PM PST 24
Finished Feb 18 01:34:10 PM PST 24
Peak memory 202232 kb
Host smart-26e981be-994c-423f-a8ed-d07463d8efaf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668739075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.3668739075
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.2927496996
Short name T336
Test name
Test status
Simulation time 1983317635 ps
CPU time 13.52 seconds
Started Feb 18 01:24:26 PM PST 24
Finished Feb 18 01:24:40 PM PST 24
Peak memory 202240 kb
Host smart-886d1926-ae4b-45e6-9017-146ce849bd88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927496996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2927496996
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.3157246954
Short name T391
Test name
Test status
Simulation time 20758614615 ps
CPU time 655.63 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:35:15 PM PST 24
Peak memory 364972 kb
Host smart-122ece25-4737-44f7-a063-8f6b73554630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157246954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3157246954
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.3650431468
Short name T730
Test name
Test status
Simulation time 1869517669 ps
CPU time 16.37 seconds
Started Feb 18 01:24:04 PM PST 24
Finished Feb 18 01:24:21 PM PST 24
Peak memory 213100 kb
Host smart-efc91665-aeb3-4e52-a33b-18b0f9fd47be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650431468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.3650431468
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.795380625
Short name T450
Test name
Test status
Simulation time 163805841436 ps
CPU time 7314.47 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 03:26:18 PM PST 24
Peak memory 386328 kb
Host smart-fff6c907-2aba-41bc-aa9b-4ec44ac4fcd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795380625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_stress_all.795380625
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1250903454
Short name T566
Test name
Test status
Simulation time 34320992415 ps
CPU time 508.52 seconds
Started Feb 18 01:24:03 PM PST 24
Finished Feb 18 01:32:32 PM PST 24
Peak memory 202328 kb
Host smart-4f0d6f04-efb8-4340-afa4-e8e1ce6d02b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250903454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.1250903454
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3179729728
Short name T779
Test name
Test status
Simulation time 3096559245 ps
CPU time 83.53 seconds
Started Feb 18 01:24:17 PM PST 24
Finished Feb 18 01:25:41 PM PST 24
Peak memory 354612 kb
Host smart-b90ab2a3-fe72-4cb2-b06f-536d18532e42
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179729728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.3179729728
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3951017272
Short name T719
Test name
Test status
Simulation time 7402637432 ps
CPU time 912.56 seconds
Started Feb 18 01:27:20 PM PST 24
Finished Feb 18 01:42:34 PM PST 24
Peak memory 368344 kb
Host smart-fa633f59-5d67-4999-931d-04ba764327ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951017272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.3951017272
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1557593280
Short name T588
Test name
Test status
Simulation time 113518306 ps
CPU time 0.64 seconds
Started Feb 18 01:27:23 PM PST 24
Finished Feb 18 01:27:25 PM PST 24
Peak memory 201728 kb
Host smart-e883588c-489f-4ab3-b6b0-e5486eb31bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557593280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1557593280
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.3692656252
Short name T804
Test name
Test status
Simulation time 93898406666 ps
CPU time 2185.53 seconds
Started Feb 18 01:27:15 PM PST 24
Finished Feb 18 02:03:41 PM PST 24
Peak memory 202324 kb
Host smart-14aefb6e-f184-4de3-9fb5-44dd1be48e59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692656252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.3692656252
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.1916784684
Short name T252
Test name
Test status
Simulation time 737166120 ps
CPU time 28.13 seconds
Started Feb 18 01:27:19 PM PST 24
Finished Feb 18 01:27:48 PM PST 24
Peak memory 211036 kb
Host smart-a39241fa-d54e-472d-8030-42ce2f7a4e20
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916784684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.1916784684
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2371894464
Short name T787
Test name
Test status
Simulation time 1558024799 ps
CPU time 147.13 seconds
Started Feb 18 01:27:19 PM PST 24
Finished Feb 18 01:29:47 PM PST 24
Peak memory 210800 kb
Host smart-a1449a75-a383-4240-bede-f7a157194fbf
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371894464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2371894464
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.2137677795
Short name T742
Test name
Test status
Simulation time 85985782719 ps
CPU time 309.35 seconds
Started Feb 18 01:27:15 PM PST 24
Finished Feb 18 01:32:25 PM PST 24
Peak memory 202248 kb
Host smart-9ec23e5d-0a32-4c8e-8ab7-fd1b602be400
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137677795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.2137677795
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.3720679481
Short name T663
Test name
Test status
Simulation time 22878177455 ps
CPU time 378.01 seconds
Started Feb 18 01:27:13 PM PST 24
Finished Feb 18 01:33:33 PM PST 24
Peak memory 353580 kb
Host smart-ee391310-6902-4119-8026-3771bcca8578
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720679481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.3720679481
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.2867749596
Short name T451
Test name
Test status
Simulation time 3221817199 ps
CPU time 40.65 seconds
Started Feb 18 01:27:15 PM PST 24
Finished Feb 18 01:27:56 PM PST 24
Peak memory 270952 kb
Host smart-876f4de9-d15c-40cf-ac4b-9646d2f910ea
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867749596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.2867749596
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2660039141
Short name T607
Test name
Test status
Simulation time 13723994191 ps
CPU time 450.48 seconds
Started Feb 18 01:27:12 PM PST 24
Finished Feb 18 01:34:44 PM PST 24
Peak memory 216628 kb
Host smart-71d10db0-204c-45ba-bd3a-04314f75140a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660039141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.sram_ctrl_partial_access_b2b.2660039141
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.3425497980
Short name T146
Test name
Test status
Simulation time 1350649931 ps
CPU time 13.99 seconds
Started Feb 18 01:27:13 PM PST 24
Finished Feb 18 01:27:29 PM PST 24
Peak memory 202480 kb
Host smart-5f25b3bb-5aa6-4869-b918-732373e8b620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425497980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3425497980
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.107723257
Short name T392
Test name
Test status
Simulation time 2495093462 ps
CPU time 834.05 seconds
Started Feb 18 01:27:13 PM PST 24
Finished Feb 18 01:41:09 PM PST 24
Peak memory 375268 kb
Host smart-9bd56018-c14b-4050-9678-bcb2bd5c64ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107723257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.107723257
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.4028142890
Short name T213
Test name
Test status
Simulation time 3951268398 ps
CPU time 19.79 seconds
Started Feb 18 01:27:16 PM PST 24
Finished Feb 18 01:27:37 PM PST 24
Peak memory 202276 kb
Host smart-8dd3fb2e-1e72-4294-a0df-8ca8e701e8b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028142890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4028142890
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.1941716329
Short name T232
Test name
Test status
Simulation time 20959517688 ps
CPU time 400.32 seconds
Started Feb 18 01:27:18 PM PST 24
Finished Feb 18 01:33:59 PM PST 24
Peak memory 202312 kb
Host smart-ea5752bd-45e0-42f4-a8c2-bf7a502a5605
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941716329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_stress_pipeline.1941716329
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1439379897
Short name T387
Test name
Test status
Simulation time 677656953 ps
CPU time 27.38 seconds
Started Feb 18 01:27:19 PM PST 24
Finished Feb 18 01:27:47 PM PST 24
Peak memory 216200 kb
Host smart-2da9538c-828f-4de5-89d2-f0e3bfdb3127
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439379897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.1439379897
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1152132065
Short name T626
Test name
Test status
Simulation time 10984962279 ps
CPU time 1718.11 seconds
Started Feb 18 01:27:23 PM PST 24
Finished Feb 18 01:56:02 PM PST 24
Peak memory 381248 kb
Host smart-8b30e0c6-1619-4f18-a425-ddee646c009d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152132065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.1152132065
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.847527059
Short name T22
Test name
Test status
Simulation time 51762457 ps
CPU time 0.62 seconds
Started Feb 18 01:27:24 PM PST 24
Finished Feb 18 01:27:25 PM PST 24
Peak memory 201652 kb
Host smart-f8223c86-3089-4e42-bd6f-8c64c0a1a6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847527059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.847527059
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.2323778714
Short name T483
Test name
Test status
Simulation time 71174060895 ps
CPU time 2070.49 seconds
Started Feb 18 01:27:21 PM PST 24
Finished Feb 18 02:01:52 PM PST 24
Peak memory 202444 kb
Host smart-37e9c475-5858-419e-8d4b-d064112e3fab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323778714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection
.2323778714
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.1250794146
Short name T517
Test name
Test status
Simulation time 8037263653 ps
CPU time 188.74 seconds
Started Feb 18 01:27:25 PM PST 24
Finished Feb 18 01:30:35 PM PST 24
Peak memory 210460 kb
Host smart-a9fa35f6-4a43-4514-b02f-112183e1eb1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250794146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.1250794146
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.239689163
Short name T157
Test name
Test status
Simulation time 1481879374 ps
CPU time 68.47 seconds
Started Feb 18 01:27:25 PM PST 24
Finished Feb 18 01:28:34 PM PST 24
Peak memory 300208 kb
Host smart-380dc8d5-76c8-4a46-9012-c539abe75b6d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239689163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.sram_ctrl_max_throughput.239689163
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.786279879
Short name T191
Test name
Test status
Simulation time 3137547692 ps
CPU time 139.99 seconds
Started Feb 18 01:27:22 PM PST 24
Finished Feb 18 01:29:43 PM PST 24
Peak memory 210872 kb
Host smart-b4f57e24-b41c-4146-87fb-55688dabaf04
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786279879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.sram_ctrl_mem_partial_access.786279879
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.3996516185
Short name T416
Test name
Test status
Simulation time 2058413832 ps
CPU time 125.65 seconds
Started Feb 18 01:27:24 PM PST 24
Finished Feb 18 01:29:31 PM PST 24
Peak memory 202152 kb
Host smart-98a5abb9-9f1a-45a1-8722-11fb5b3c907b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996516185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr
l_mem_walk.3996516185
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.87381490
Short name T528
Test name
Test status
Simulation time 13174852095 ps
CPU time 319.3 seconds
Started Feb 18 01:27:18 PM PST 24
Finished Feb 18 01:32:38 PM PST 24
Peak memory 354452 kb
Host smart-c3dccd51-91d1-46df-bcf4-f5627fbef80b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87381490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multipl
e_keys.87381490
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.3281200406
Short name T595
Test name
Test status
Simulation time 3507286136 ps
CPU time 25.89 seconds
Started Feb 18 01:27:22 PM PST 24
Finished Feb 18 01:27:48 PM PST 24
Peak memory 250700 kb
Host smart-c8d0cfbc-5e9a-42d9-b7f5-9011b032bfb6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281200406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
sram_ctrl_partial_access.3281200406
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2747578189
Short name T464
Test name
Test status
Simulation time 6350186626 ps
CPU time 418.58 seconds
Started Feb 18 01:27:24 PM PST 24
Finished Feb 18 01:34:23 PM PST 24
Peak memory 202308 kb
Host smart-aa865d6c-5b11-4880-a57b-caa392b26476
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747578189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2747578189
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.3595932789
Short name T679
Test name
Test status
Simulation time 359190213 ps
CPU time 5.65 seconds
Started Feb 18 01:27:25 PM PST 24
Finished Feb 18 01:27:32 PM PST 24
Peak memory 202352 kb
Host smart-6f3c360e-99e4-4f78-9166-7ab627fa7d41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595932789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3595932789
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.775024228
Short name T215
Test name
Test status
Simulation time 1889597413 ps
CPU time 222.95 seconds
Started Feb 18 01:27:23 PM PST 24
Finished Feb 18 01:31:07 PM PST 24
Peak memory 338136 kb
Host smart-412cfa7e-973e-4917-a449-90174ba74de0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775024228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.775024228
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.110537807
Short name T675
Test name
Test status
Simulation time 6404138041 ps
CPU time 142.16 seconds
Started Feb 18 01:27:19 PM PST 24
Finished Feb 18 01:29:42 PM PST 24
Peak memory 360788 kb
Host smart-69c063d9-19ad-4f74-8774-4c4e4729c2da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110537807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.110537807
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2327125484
Short name T807
Test name
Test status
Simulation time 5293061267 ps
CPU time 350.05 seconds
Started Feb 18 01:27:17 PM PST 24
Finished Feb 18 01:33:08 PM PST 24
Peak memory 202284 kb
Host smart-9285641f-adbe-486f-a2c2-86337ce1d17d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327125484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_stress_pipeline.2327125484
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.619129142
Short name T617
Test name
Test status
Simulation time 768560797 ps
CPU time 107.97 seconds
Started Feb 18 01:27:28 PM PST 24
Finished Feb 18 01:29:17 PM PST 24
Peak memory 342396 kb
Host smart-d621122a-f53f-4b49-9ede-8c398036eedd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619129142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.619129142
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2755433299
Short name T374
Test name
Test status
Simulation time 38056401494 ps
CPU time 1364.63 seconds
Started Feb 18 01:27:32 PM PST 24
Finished Feb 18 01:50:19 PM PST 24
Peak memory 375008 kb
Host smart-0dc0a39c-4824-4683-8a4a-7a6ebbac0289
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755433299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.2755433299
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.3450300721
Short name T422
Test name
Test status
Simulation time 15517759 ps
CPU time 0.63 seconds
Started Feb 18 01:27:38 PM PST 24
Finished Feb 18 01:27:41 PM PST 24
Peak memory 202012 kb
Host smart-69b4befc-6438-4a57-8e4e-28a8d909bc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450300721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.3450300721
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.1132219472
Short name T594
Test name
Test status
Simulation time 152433930671 ps
CPU time 2153.13 seconds
Started Feb 18 01:27:30 PM PST 24
Finished Feb 18 02:03:24 PM PST 24
Peak memory 202308 kb
Host smart-2e9eea5b-2d3a-46f3-ad38-a48731a7e143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132219472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.1132219472
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.731248221
Short name T616
Test name
Test status
Simulation time 27064456638 ps
CPU time 126.82 seconds
Started Feb 18 01:27:30 PM PST 24
Finished Feb 18 01:29:39 PM PST 24
Peak memory 210432 kb
Host smart-bb3843f4-db99-4f29-978b-33701e7749ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731248221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc
alation.731248221
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.541337404
Short name T625
Test name
Test status
Simulation time 2844146077 ps
CPU time 54.56 seconds
Started Feb 18 01:27:32 PM PST 24
Finished Feb 18 01:28:29 PM PST 24
Peak memory 284116 kb
Host smart-6ef73357-5f54-4aab-ab8c-6e506b653bd0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541337404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.sram_ctrl_max_throughput.541337404
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.772701273
Short name T557
Test name
Test status
Simulation time 5316391522 ps
CPU time 78.73 seconds
Started Feb 18 01:27:37 PM PST 24
Finished Feb 18 01:28:58 PM PST 24
Peak memory 211340 kb
Host smart-d9773fa6-89e2-4d5a-a7cb-5646696c250e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772701273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.sram_ctrl_mem_partial_access.772701273
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.184730065
Short name T651
Test name
Test status
Simulation time 21071510679 ps
CPU time 303.04 seconds
Started Feb 18 01:27:32 PM PST 24
Finished Feb 18 01:32:38 PM PST 24
Peak memory 202364 kb
Host smart-da9a1dd0-b451-479c-8f08-410e355d778d
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184730065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl
_mem_walk.184730065
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.2266303585
Short name T206
Test name
Test status
Simulation time 29490451702 ps
CPU time 1665.6 seconds
Started Feb 18 01:27:33 PM PST 24
Finished Feb 18 01:55:22 PM PST 24
Peak memory 378212 kb
Host smart-8f50fdee-67d8-4c0a-ad3b-5681d1721423
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266303585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.2266303585
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.959301646
Short name T318
Test name
Test status
Simulation time 3289930666 ps
CPU time 76.45 seconds
Started Feb 18 01:27:31 PM PST 24
Finished Feb 18 01:28:50 PM PST 24
Peak memory 343092 kb
Host smart-00202eae-e95e-4758-ad5e-0c68ad6f3213
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959301646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.s
ram_ctrl_partial_access.959301646
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.4061404560
Short name T93
Test name
Test status
Simulation time 32489512634 ps
CPU time 512.61 seconds
Started Feb 18 01:27:32 PM PST 24
Finished Feb 18 01:36:07 PM PST 24
Peak memory 202316 kb
Host smart-d806e30a-dcda-4e47-a5b8-f62ea42f9d7c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061404560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.4061404560
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.176311702
Short name T847
Test name
Test status
Simulation time 711569786 ps
CPU time 5.53 seconds
Started Feb 18 01:27:32 PM PST 24
Finished Feb 18 01:27:40 PM PST 24
Peak memory 202440 kb
Host smart-4262429e-0fcf-4d0f-bbe5-96c57ba9f1b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176311702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.176311702
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.2528325930
Short name T389
Test name
Test status
Simulation time 17871365558 ps
CPU time 496.34 seconds
Started Feb 18 01:27:30 PM PST 24
Finished Feb 18 01:35:48 PM PST 24
Peak memory 355620 kb
Host smart-bcb5ac1b-2ed7-4ae7-b80b-9d38774d797b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528325930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2528325930
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.2610533908
Short name T271
Test name
Test status
Simulation time 2458659299 ps
CPU time 11.76 seconds
Started Feb 18 01:27:30 PM PST 24
Finished Feb 18 01:27:43 PM PST 24
Peak memory 202204 kb
Host smart-d483189f-8fed-49b1-b2e6-270dd2d8278c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610533908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2610533908
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.2036935820
Short name T762
Test name
Test status
Simulation time 508818203734 ps
CPU time 4222.27 seconds
Started Feb 18 01:27:38 PM PST 24
Finished Feb 18 02:38:03 PM PST 24
Peak memory 380172 kb
Host smart-c85bf5f5-453a-477d-a699-bbcaa026dd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036935820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.sram_ctrl_stress_all.2036935820
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2726392599
Short name T187
Test name
Test status
Simulation time 8827698559 ps
CPU time 306.61 seconds
Started Feb 18 01:27:33 PM PST 24
Finished Feb 18 01:32:43 PM PST 24
Peak memory 202348 kb
Host smart-78fed281-1aef-4b57-9b8f-782e9614d0d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726392599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.2726392599
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1683812314
Short name T829
Test name
Test status
Simulation time 2905758848 ps
CPU time 118.96 seconds
Started Feb 18 01:27:31 PM PST 24
Finished Feb 18 01:29:33 PM PST 24
Peak memory 334140 kb
Host smart-29a026a7-b761-4257-9d5a-bce6c83ff11b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683812314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1683812314
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.4211323090
Short name T332
Test name
Test status
Simulation time 53347139255 ps
CPU time 2459.73 seconds
Started Feb 18 01:27:47 PM PST 24
Finished Feb 18 02:08:47 PM PST 24
Peak memory 374044 kb
Host smart-aa1bedf4-c53d-4875-a511-36ed5c70264c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211323090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.4211323090
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.999068223
Short name T447
Test name
Test status
Simulation time 59956424 ps
CPU time 0.66 seconds
Started Feb 18 01:27:55 PM PST 24
Finished Feb 18 01:27:59 PM PST 24
Peak memory 201884 kb
Host smart-058612e4-1ef5-4337-984a-71075b94deae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999068223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.999068223
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.4111144668
Short name T686
Test name
Test status
Simulation time 59290241009 ps
CPU time 1920.11 seconds
Started Feb 18 01:27:38 PM PST 24
Finished Feb 18 01:59:41 PM PST 24
Peak memory 202328 kb
Host smart-8e179f05-72b4-4dc5-9f8b-400d1dc2a458
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111144668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection
.4111144668
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.1044213866
Short name T106
Test name
Test status
Simulation time 6360357827 ps
CPU time 70.05 seconds
Started Feb 18 01:27:49 PM PST 24
Finished Feb 18 01:28:59 PM PST 24
Peak memory 210492 kb
Host smart-aa801a67-a20d-46d2-83b0-fa7aeacfe85e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044213866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es
calation.1044213866
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.2527155251
Short name T405
Test name
Test status
Simulation time 733848831 ps
CPU time 64.64 seconds
Started Feb 18 01:27:46 PM PST 24
Finished Feb 18 01:28:51 PM PST 24
Peak memory 306492 kb
Host smart-566a3224-1c33-40b9-a622-0b66ffbb6209
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527155251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_max_throughput.2527155251
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2804466621
Short name T629
Test name
Test status
Simulation time 8397938946 ps
CPU time 75.75 seconds
Started Feb 18 01:27:54 PM PST 24
Finished Feb 18 01:29:14 PM PST 24
Peak memory 212192 kb
Host smart-d77f3af7-74fd-47de-803d-117cfccc343f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804466621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_mem_partial_access.2804466621
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.2975459659
Short name T540
Test name
Test status
Simulation time 3945998301 ps
CPU time 247.51 seconds
Started Feb 18 01:27:48 PM PST 24
Finished Feb 18 01:31:56 PM PST 24
Peak memory 202208 kb
Host smart-fd0b1b7b-0438-42c2-adfe-a34c9f71ece8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975459659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr
l_mem_walk.2975459659
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.4188445847
Short name T666
Test name
Test status
Simulation time 10322026147 ps
CPU time 386.65 seconds
Started Feb 18 01:27:45 PM PST 24
Finished Feb 18 01:34:12 PM PST 24
Peak memory 373720 kb
Host smart-01f6d52d-6fab-4919-b163-8615b13b338f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188445847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.4188445847
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.1277438817
Short name T739
Test name
Test status
Simulation time 3643059121 ps
CPU time 76.14 seconds
Started Feb 18 01:27:48 PM PST 24
Finished Feb 18 01:29:05 PM PST 24
Peak memory 319052 kb
Host smart-eac7dca7-f79c-4f89-bd59-52a97a01cf0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277438817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.1277438817
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.2396731597
Short name T209
Test name
Test status
Simulation time 131979222773 ps
CPU time 252.72 seconds
Started Feb 18 01:27:46 PM PST 24
Finished Feb 18 01:32:00 PM PST 24
Peak memory 202220 kb
Host smart-4057c497-b1ec-4610-953f-178d184e9e20
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396731597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.2396731597
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.3640685812
Short name T445
Test name
Test status
Simulation time 709891668 ps
CPU time 6.76 seconds
Started Feb 18 01:27:47 PM PST 24
Finished Feb 18 01:27:55 PM PST 24
Peak memory 202424 kb
Host smart-f95cbb43-c503-41cb-811d-0391589ac85b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640685812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3640685812
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.431564997
Short name T576
Test name
Test status
Simulation time 12968951465 ps
CPU time 907.74 seconds
Started Feb 18 01:27:49 PM PST 24
Finished Feb 18 01:42:58 PM PST 24
Peak memory 376192 kb
Host smart-bb883233-3c41-489f-9fc8-2f6a5cc4904e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431564997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.431564997
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.2296344748
Short name T361
Test name
Test status
Simulation time 346032976 ps
CPU time 13.38 seconds
Started Feb 18 01:27:37 PM PST 24
Finished Feb 18 01:27:53 PM PST 24
Peak memory 202160 kb
Host smart-fe555b2a-3cb4-4a5f-b03c-5d45faab51f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296344748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2296344748
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_all.1137501798
Short name T803
Test name
Test status
Simulation time 167647912908 ps
CPU time 6431.83 seconds
Started Feb 18 01:27:56 PM PST 24
Finished Feb 18 03:15:14 PM PST 24
Peak memory 382232 kb
Host smart-8c5dcf78-3609-4706-ba1b-27d52e2e5d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137501798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.sram_ctrl_stress_all.1137501798
Directory /workspace/23.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2974153737
Short name T639
Test name
Test status
Simulation time 27319332717 ps
CPU time 363.21 seconds
Started Feb 18 01:27:48 PM PST 24
Finished Feb 18 01:33:52 PM PST 24
Peak memory 202276 kb
Host smart-dfe4dd5a-0668-43b0-b40d-fc96ddcb8ff0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974153737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.2974153737
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3091681935
Short name T713
Test name
Test status
Simulation time 3166787286 ps
CPU time 127.33 seconds
Started Feb 18 01:27:47 PM PST 24
Finished Feb 18 01:29:55 PM PST 24
Peak memory 341352 kb
Host smart-0c5b6637-5438-4dfb-8cc5-e96a783ede7a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091681935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3091681935
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2232817086
Short name T497
Test name
Test status
Simulation time 6074638841 ps
CPU time 993.36 seconds
Started Feb 18 01:27:56 PM PST 24
Finished Feb 18 01:44:34 PM PST 24
Peak memory 376116 kb
Host smart-99c6b945-cc77-44d7-9c2e-74a49caa601f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232817086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.sram_ctrl_access_during_key_req.2232817086
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.4121913453
Short name T186
Test name
Test status
Simulation time 48004742 ps
CPU time 0.63 seconds
Started Feb 18 01:28:01 PM PST 24
Finished Feb 18 01:28:05 PM PST 24
Peak memory 201708 kb
Host smart-8b7c61a9-5e95-46af-912d-b9265cfc95dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121913453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.4121913453
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.3871499893
Short name T430
Test name
Test status
Simulation time 83328783358 ps
CPU time 1420.81 seconds
Started Feb 18 01:27:55 PM PST 24
Finished Feb 18 01:51:39 PM PST 24
Peak memory 202296 kb
Host smart-30d4d42d-b9f0-46a9-be18-76600827a5e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871499893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.3871499893
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.4143793510
Short name T264
Test name
Test status
Simulation time 9442583469 ps
CPU time 107.29 seconds
Started Feb 18 01:27:55 PM PST 24
Finished Feb 18 01:29:46 PM PST 24
Peak memory 210476 kb
Host smart-567d4439-25d0-4e8e-9e8f-0257b30b2a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143793510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.4143793510
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.235997490
Short name T706
Test name
Test status
Simulation time 6224003274 ps
CPU time 35.56 seconds
Started Feb 18 01:27:54 PM PST 24
Finished Feb 18 01:28:34 PM PST 24
Peak memory 235084 kb
Host smart-3be90d08-31d6-4372-a313-1b0bec4210ec
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235997490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.sram_ctrl_max_throughput.235997490
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.54018036
Short name T610
Test name
Test status
Simulation time 968759426 ps
CPU time 73.84 seconds
Started Feb 18 01:28:03 PM PST 24
Finished Feb 18 01:29:20 PM PST 24
Peak memory 211256 kb
Host smart-55265c48-b74e-49f9-aea3-363254e19a4d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54018036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_mem_partial_access.54018036
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.820716298
Short name T199
Test name
Test status
Simulation time 91889095537 ps
CPU time 284.38 seconds
Started Feb 18 01:28:02 PM PST 24
Finished Feb 18 01:32:48 PM PST 24
Peak memory 202752 kb
Host smart-ecfbd381-e405-4e89-a8ad-211a02c9e987
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820716298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_mem_walk.820716298
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.4246616875
Short name T326
Test name
Test status
Simulation time 36499360602 ps
CPU time 721.92 seconds
Started Feb 18 01:27:57 PM PST 24
Finished Feb 18 01:40:03 PM PST 24
Peak memory 373208 kb
Host smart-c78d4c2f-cf55-4631-b5be-e9ef254042f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246616875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.4246616875
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.2044792970
Short name T774
Test name
Test status
Simulation time 1305110762 ps
CPU time 74.42 seconds
Started Feb 18 01:27:54 PM PST 24
Finished Feb 18 01:29:13 PM PST 24
Peak memory 319700 kb
Host smart-309cc381-c5cb-41fe-96e3-9b922dd3362a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044792970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.2044792970
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2389623821
Short name T611
Test name
Test status
Simulation time 8470397773 ps
CPU time 223.6 seconds
Started Feb 18 01:27:55 PM PST 24
Finished Feb 18 01:31:42 PM PST 24
Peak memory 202248 kb
Host smart-bed8e7a0-7d7b-4cc7-a115-14db7eb210ed
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389623821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.2389623821
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.2085339968
Short name T359
Test name
Test status
Simulation time 357092545 ps
CPU time 6.48 seconds
Started Feb 18 01:28:01 PM PST 24
Finished Feb 18 01:28:10 PM PST 24
Peak memory 202444 kb
Host smart-82926f34-dd09-4089-9292-8a7322421a36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085339968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2085339968
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.2814016735
Short name T123
Test name
Test status
Simulation time 13943162266 ps
CPU time 1196.45 seconds
Started Feb 18 01:28:01 PM PST 24
Finished Feb 18 01:48:01 PM PST 24
Peak memory 379256 kb
Host smart-bc8d528b-5c24-4ed3-a9b3-f89dfafc75ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814016735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2814016735
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.2883988158
Short name T469
Test name
Test status
Simulation time 917433284 ps
CPU time 153.82 seconds
Started Feb 18 01:27:55 PM PST 24
Finished Feb 18 01:30:32 PM PST 24
Peak memory 365608 kb
Host smart-c951b9d8-244d-4d00-9580-299135f8fa73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883988158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2883988158
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.1838926343
Short name T835
Test name
Test status
Simulation time 8741426274 ps
CPU time 331.82 seconds
Started Feb 18 01:27:58 PM PST 24
Finished Feb 18 01:33:33 PM PST 24
Peak memory 202316 kb
Host smart-eb53c3ba-72c6-48d4-90ef-fea0a18c9dc0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838926343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.1838926343
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1224124843
Short name T500
Test name
Test status
Simulation time 5762260319 ps
CPU time 33.7 seconds
Started Feb 18 01:27:54 PM PST 24
Finished Feb 18 01:28:32 PM PST 24
Peak memory 237992 kb
Host smart-5091ce2e-98e9-4e87-88f8-b34052f7b93d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224124843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1224124843
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.1507343826
Short name T316
Test name
Test status
Simulation time 6366943175 ps
CPU time 801.33 seconds
Started Feb 18 01:28:07 PM PST 24
Finished Feb 18 01:41:32 PM PST 24
Peak memory 377108 kb
Host smart-8a277a54-ed04-4ea7-ae3a-d8f7dd96ed4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507343826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.1507343826
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.4176201259
Short name T624
Test name
Test status
Simulation time 40202745 ps
CPU time 0.64 seconds
Started Feb 18 01:28:12 PM PST 24
Finished Feb 18 01:28:16 PM PST 24
Peak memory 201716 kb
Host smart-e1d49b46-66bb-4715-843a-3a89f42cf4bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176201259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.4176201259
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.1785051038
Short name T704
Test name
Test status
Simulation time 150442574284 ps
CPU time 844.66 seconds
Started Feb 18 01:27:57 PM PST 24
Finished Feb 18 01:42:06 PM PST 24
Peak memory 202384 kb
Host smart-ffae4178-8374-49f1-8d49-fdda3d061be7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785051038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.1785051038
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.1719403764
Short name T212
Test name
Test status
Simulation time 6667837350 ps
CPU time 82.26 seconds
Started Feb 18 01:28:03 PM PST 24
Finished Feb 18 01:29:28 PM PST 24
Peak memory 210480 kb
Host smart-818b5d89-1e52-4cdf-8e14-6ea91ce05f2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719403764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab
le.1719403764
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.1477384011
Short name T819
Test name
Test status
Simulation time 3540743436 ps
CPU time 33.05 seconds
Started Feb 18 01:28:02 PM PST 24
Finished Feb 18 01:28:38 PM PST 24
Peak memory 210492 kb
Host smart-59f3faaa-fa96-437d-a1c0-5ce32dd92b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477384011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es
calation.1477384011
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.2230647325
Short name T699
Test name
Test status
Simulation time 2979797771 ps
CPU time 53.22 seconds
Started Feb 18 01:27:58 PM PST 24
Finished Feb 18 01:28:54 PM PST 24
Peak memory 285040 kb
Host smart-ae93ef2a-71c1-43c5-a728-26b358e2eee2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230647325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.2230647325
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.3171330913
Short name T82
Test name
Test status
Simulation time 5949480196 ps
CPU time 137.67 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:30:32 PM PST 24
Peak memory 211336 kb
Host smart-ba8a9a06-7291-49c7-9838-8736d2028f68
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171330913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.3171330913
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.2136697608
Short name T752
Test name
Test status
Simulation time 10435714836 ps
CPU time 155.3 seconds
Started Feb 18 01:28:04 PM PST 24
Finished Feb 18 01:30:42 PM PST 24
Peak memory 202480 kb
Host smart-e3b2d101-51f3-4f7a-ae34-62e4d33fa874
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136697608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr
l_mem_walk.2136697608
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.3129788217
Short name T635
Test name
Test status
Simulation time 20058206796 ps
CPU time 949.2 seconds
Started Feb 18 01:28:00 PM PST 24
Finished Feb 18 01:43:53 PM PST 24
Peak memory 377164 kb
Host smart-8710e572-7697-48ad-b094-cc04fa45653d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129788217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi
ple_keys.3129788217
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.1633403724
Short name T488
Test name
Test status
Simulation time 4424195522 ps
CPU time 14.51 seconds
Started Feb 18 01:28:02 PM PST 24
Finished Feb 18 01:28:19 PM PST 24
Peak memory 202144 kb
Host smart-205bb443-5d87-4e1e-a407-a6074832f129
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633403724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.1633403724
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2382001414
Short name T200
Test name
Test status
Simulation time 36185981566 ps
CPU time 451.53 seconds
Started Feb 18 01:28:02 PM PST 24
Finished Feb 18 01:35:37 PM PST 24
Peak memory 202188 kb
Host smart-be39a5de-2c0b-4d5d-9740-ab0a70a28497
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382001414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.2382001414
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.637457276
Short name T781
Test name
Test status
Simulation time 367251608 ps
CPU time 13.23 seconds
Started Feb 18 01:28:07 PM PST 24
Finished Feb 18 01:28:24 PM PST 24
Peak memory 202412 kb
Host smart-f0b9c036-141b-407a-bf81-76bd4e0e8a0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637457276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.637457276
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.1637586810
Short name T511
Test name
Test status
Simulation time 31250740492 ps
CPU time 731.71 seconds
Started Feb 18 01:28:03 PM PST 24
Finished Feb 18 01:40:17 PM PST 24
Peak memory 376112 kb
Host smart-18350cb8-8e3f-471b-b93b-a5be0b98e2da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637586810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1637586810
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.929957704
Short name T561
Test name
Test status
Simulation time 871065874 ps
CPU time 35.08 seconds
Started Feb 18 01:28:02 PM PST 24
Finished Feb 18 01:28:40 PM PST 24
Peak memory 202156 kb
Host smart-22f9fb9c-b55f-4070-a683-a9de7d1a7929
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929957704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.929957704
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1992165835
Short name T42
Test name
Test status
Simulation time 23460369133 ps
CPU time 232.87 seconds
Started Feb 18 01:28:06 PM PST 24
Finished Feb 18 01:32:02 PM PST 24
Peak memory 202272 kb
Host smart-27441b59-4cb3-4d54-a314-83112cf3be6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992165835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.1992165835
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3444928693
Short name T46
Test name
Test status
Simulation time 1084220292 ps
CPU time 47.44 seconds
Started Feb 18 01:28:00 PM PST 24
Finished Feb 18 01:28:51 PM PST 24
Peak memory 267652 kb
Host smart-538dbfdc-2dd8-4c1b-89b5-711eb6a1ac48
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444928693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.3444928693
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.4114252716
Short name T729
Test name
Test status
Simulation time 10466762507 ps
CPU time 1350.96 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:50:45 PM PST 24
Peak memory 380568 kb
Host smart-63f7a9ff-044e-4b0f-9adb-3394e81240cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114252716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.sram_ctrl_access_during_key_req.4114252716
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.2178901422
Short name T227
Test name
Test status
Simulation time 33507191 ps
CPU time 0.64 seconds
Started Feb 18 01:28:20 PM PST 24
Finished Feb 18 01:28:22 PM PST 24
Peak memory 201992 kb
Host smart-e54bd9a6-5e7f-4043-8899-2a2cdb568c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178901422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.2178901422
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.4095033347
Short name T43
Test name
Test status
Simulation time 473574292206 ps
CPU time 2164.56 seconds
Started Feb 18 01:28:11 PM PST 24
Finished Feb 18 02:04:21 PM PST 24
Peak memory 202364 kb
Host smart-7e2dbeaa-44c6-418f-9419-a0c23dd646be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095033347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection
.4095033347
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_lc_escalation.2524515775
Short name T117
Test name
Test status
Simulation time 9030847981 ps
CPU time 105.55 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:29:59 PM PST 24
Peak memory 202296 kb
Host smart-9f62de15-d585-4fbc-a5be-fb824f68b7ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524515775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_es
calation.2524515775
Directory /workspace/26.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.3687440027
Short name T818
Test name
Test status
Simulation time 1414490065 ps
CPU time 43.51 seconds
Started Feb 18 01:28:11 PM PST 24
Finished Feb 18 01:28:59 PM PST 24
Peak memory 267640 kb
Host smart-e9c20265-6fc4-482a-81eb-05731c4bde0b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687440027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.3687440027
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.2609439517
Short name T637
Test name
Test status
Simulation time 1569270489 ps
CPU time 125.9 seconds
Started Feb 18 01:28:12 PM PST 24
Finished Feb 18 01:30:22 PM PST 24
Peak memory 211236 kb
Host smart-99df9824-c6c5-437d-8546-464607966597
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609439517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_mem_partial_access.2609439517
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.2536691520
Short name T603
Test name
Test status
Simulation time 38394666345 ps
CPU time 143.16 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:30:37 PM PST 24
Peak memory 202372 kb
Host smart-9bbdfd4d-3ea9-4100-8202-9291115ec895
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536691520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr
l_mem_walk.2536691520
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.4158835221
Short name T147
Test name
Test status
Simulation time 30626724371 ps
CPU time 675.61 seconds
Started Feb 18 01:28:11 PM PST 24
Finished Feb 18 01:39:31 PM PST 24
Peak memory 375076 kb
Host smart-c2f7af2a-de30-49de-8234-cd018d08304e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158835221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.4158835221
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.3607531875
Short name T697
Test name
Test status
Simulation time 1301167863 ps
CPU time 20.7 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:28:35 PM PST 24
Peak memory 202088 kb
Host smart-7bbb9f97-92b2-4d88-a858-5b660b77e97b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607531875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_partial_access.3607531875
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1048918114
Short name T248
Test name
Test status
Simulation time 12470689308 ps
CPU time 438.68 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:35:33 PM PST 24
Peak memory 202316 kb
Host smart-420feba3-c913-4ea2-843e-5a8b2fffb564
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048918114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.1048918114
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.1592992808
Short name T444
Test name
Test status
Simulation time 544957317 ps
CPU time 6.8 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:28:21 PM PST 24
Peak memory 202452 kb
Host smart-c7e42571-c9d3-4072-b179-e55a511a9e2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592992808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1592992808
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.1594890867
Short name T431
Test name
Test status
Simulation time 56560969382 ps
CPU time 1197.29 seconds
Started Feb 18 01:28:11 PM PST 24
Finished Feb 18 01:48:13 PM PST 24
Peak memory 379284 kb
Host smart-59868fca-8440-44a4-8958-06adfe7cf949
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594890867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1594890867
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.3841125003
Short name T532
Test name
Test status
Simulation time 1981606482 ps
CPU time 28.47 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:28:42 PM PST 24
Peak memory 269712 kb
Host smart-a800d331-edc0-4412-bb19-f518a70b8f42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841125003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3841125003
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2518960276
Short name T371
Test name
Test status
Simulation time 3947926442 ps
CPU time 187.37 seconds
Started Feb 18 01:28:16 PM PST 24
Finished Feb 18 01:31:24 PM PST 24
Peak memory 202268 kb
Host smart-ef754690-0981-4072-8a1a-0ac44b0e0585
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518960276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.2518960276
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3827398884
Short name T410
Test name
Test status
Simulation time 1604655415 ps
CPU time 159.25 seconds
Started Feb 18 01:28:10 PM PST 24
Finished Feb 18 01:30:53 PM PST 24
Peak memory 371928 kb
Host smart-076a4664-46d2-4666-8414-5bbb61ab6cda
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827398884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3827398884
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.304398421
Short name T712
Test name
Test status
Simulation time 9512377130 ps
CPU time 945.64 seconds
Started Feb 18 01:28:18 PM PST 24
Finished Feb 18 01:44:05 PM PST 24
Peak memory 378152 kb
Host smart-cba3a2b7-feac-4619-8c19-3ab7a726963c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304398421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 27.sram_ctrl_access_during_key_req.304398421
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.2317691598
Short name T524
Test name
Test status
Simulation time 15771247 ps
CPU time 0.7 seconds
Started Feb 18 01:28:32 PM PST 24
Finished Feb 18 01:28:33 PM PST 24
Peak memory 201732 kb
Host smart-b8f41f5b-9b7f-42b6-945e-93a1cd3a8efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317691598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.2317691598
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.3377418427
Short name T311
Test name
Test status
Simulation time 20005469831 ps
CPU time 1383.26 seconds
Started Feb 18 01:28:17 PM PST 24
Finished Feb 18 01:51:21 PM PST 24
Peak memory 202396 kb
Host smart-83c5d27f-9f98-497e-a378-379a3659a54e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377418427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.3377418427
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.2500122963
Short name T122
Test name
Test status
Simulation time 73532385210 ps
CPU time 1179.04 seconds
Started Feb 18 01:28:30 PM PST 24
Finished Feb 18 01:48:10 PM PST 24
Peak memory 375052 kb
Host smart-5ae2283e-90f5-4c50-ad8b-63f1465ef380
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500122963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.2500122963
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.2710708085
Short name T274
Test name
Test status
Simulation time 21379867048 ps
CPU time 134.9 seconds
Started Feb 18 01:28:18 PM PST 24
Finished Feb 18 01:30:34 PM PST 24
Peak memory 210488 kb
Host smart-b2c9bcc8-1e8f-43dc-a2b8-6b1aa7e3d5c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710708085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.2710708085
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.4219320773
Short name T402
Test name
Test status
Simulation time 1583587196 ps
CPU time 167.2 seconds
Started Feb 18 01:28:18 PM PST 24
Finished Feb 18 01:31:06 PM PST 24
Peak memory 363620 kb
Host smart-2b7d97c8-e14b-41ff-90dd-32665dc850bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219320773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sram_ctrl_max_throughput.4219320773
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2531795778
Short name T81
Test name
Test status
Simulation time 6485339198 ps
CPU time 128.06 seconds
Started Feb 18 01:28:29 PM PST 24
Finished Feb 18 01:30:38 PM PST 24
Peak memory 210764 kb
Host smart-cb6c5f9b-9d64-4eec-aa8e-50a0bef6d0fa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531795778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.2531795778
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.3833768290
Short name T442
Test name
Test status
Simulation time 112015345673 ps
CPU time 177.59 seconds
Started Feb 18 01:28:31 PM PST 24
Finished Feb 18 01:31:29 PM PST 24
Peak memory 202236 kb
Host smart-bcb77c8e-b872-4bc6-b1a4-71e05f151ba1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833768290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.3833768290
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.107705062
Short name T586
Test name
Test status
Simulation time 44346187917 ps
CPU time 704.01 seconds
Started Feb 18 01:28:19 PM PST 24
Finished Feb 18 01:40:04 PM PST 24
Peak memory 378204 kb
Host smart-273e5893-53e8-4010-8f6b-e88ae6484ce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107705062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip
le_keys.107705062
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.3000467649
Short name T499
Test name
Test status
Simulation time 848245754 ps
CPU time 106.61 seconds
Started Feb 18 01:28:20 PM PST 24
Finished Feb 18 01:30:08 PM PST 24
Peak memory 341692 kb
Host smart-2075e1cc-3fa9-4ad1-af0d-05a769557d9e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000467649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.3000467649
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2526701959
Short name T711
Test name
Test status
Simulation time 8482287395 ps
CPU time 585.81 seconds
Started Feb 18 01:28:19 PM PST 24
Finished Feb 18 01:38:06 PM PST 24
Peak memory 202264 kb
Host smart-fe856628-5955-4eef-b8eb-863afeb0d864
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526701959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.2526701959
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.2203931720
Short name T475
Test name
Test status
Simulation time 369447179 ps
CPU time 5.4 seconds
Started Feb 18 01:28:32 PM PST 24
Finished Feb 18 01:28:38 PM PST 24
Peak memory 202392 kb
Host smart-16d3280c-600f-4101-8320-0b55566a7b6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203931720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2203931720
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.1417058115
Short name T407
Test name
Test status
Simulation time 11302725611 ps
CPU time 803.59 seconds
Started Feb 18 01:28:30 PM PST 24
Finished Feb 18 01:41:54 PM PST 24
Peak memory 379744 kb
Host smart-ecb2b46c-78f6-4916-a4db-7e26e7b3f3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417058115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1417058115
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.3206358482
Short name T388
Test name
Test status
Simulation time 3431143956 ps
CPU time 39.83 seconds
Started Feb 18 01:28:18 PM PST 24
Finished Feb 18 01:28:58 PM PST 24
Peak memory 202276 kb
Host smart-8161f937-5aab-44de-a66e-060f7ef72a11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206358482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3206358482
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.606458711
Short name T678
Test name
Test status
Simulation time 2319129492 ps
CPU time 164.32 seconds
Started Feb 18 01:28:18 PM PST 24
Finished Feb 18 01:31:03 PM PST 24
Peak memory 202264 kb
Host smart-c0df8a8f-8dff-4032-9250-2682b558353f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606458711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.sram_ctrl_stress_pipeline.606458711
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1550618828
Short name T756
Test name
Test status
Simulation time 679928579 ps
CPU time 26.91 seconds
Started Feb 18 01:28:18 PM PST 24
Finished Feb 18 01:28:46 PM PST 24
Peak memory 214616 kb
Host smart-3ef45493-8403-4bab-aa63-0739588fa19d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550618828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1550618828
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.4020760070
Short name T757
Test name
Test status
Simulation time 46189390569 ps
CPU time 499.98 seconds
Started Feb 18 01:28:35 PM PST 24
Finished Feb 18 01:36:55 PM PST 24
Peak memory 348436 kb
Host smart-289f42df-56d0-4bdd-8b5b-7358dec60c50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020760070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.4020760070
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.2939660855
Short name T377
Test name
Test status
Simulation time 17698184 ps
CPU time 0.65 seconds
Started Feb 18 01:28:42 PM PST 24
Finished Feb 18 01:28:44 PM PST 24
Peak memory 202044 kb
Host smart-b8f41569-107f-4611-8990-9bbf936d78f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939660855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.2939660855
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.2172307860
Short name T141
Test name
Test status
Simulation time 17916452494 ps
CPU time 1269.23 seconds
Started Feb 18 01:28:32 PM PST 24
Finished Feb 18 01:49:42 PM PST 24
Peak memory 202316 kb
Host smart-011cce03-9f42-49ee-b6d2-1f878201e30e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172307860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.2172307860
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.1832532752
Short name T802
Test name
Test status
Simulation time 73213007194 ps
CPU time 920.64 seconds
Started Feb 18 01:28:37 PM PST 24
Finished Feb 18 01:43:58 PM PST 24
Peak memory 377124 kb
Host smart-b1c261d7-d182-46f2-bf69-da52250cf744
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832532752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.1832532752
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.2086952363
Short name T850
Test name
Test status
Simulation time 114718452191 ps
CPU time 134.66 seconds
Started Feb 18 01:28:31 PM PST 24
Finished Feb 18 01:30:46 PM PST 24
Peak memory 210504 kb
Host smart-8eea47c3-f17d-4f35-8edf-f5712def6285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086952363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.2086952363
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.2761610337
Short name T599
Test name
Test status
Simulation time 766377434 ps
CPU time 138.37 seconds
Started Feb 18 01:28:35 PM PST 24
Finished Feb 18 01:30:54 PM PST 24
Peak memory 364692 kb
Host smart-0ea0db6d-b06c-48b1-8e2f-1c65759d0756
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761610337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.2761610337
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3656020096
Short name T510
Test name
Test status
Simulation time 6442805430 ps
CPU time 131.5 seconds
Started Feb 18 01:28:36 PM PST 24
Finished Feb 18 01:30:48 PM PST 24
Peak memory 213796 kb
Host smart-324b1475-16b1-490e-b483-2036038339be
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656020096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.3656020096
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.1640489500
Short name T168
Test name
Test status
Simulation time 13931751599 ps
CPU time 286.79 seconds
Started Feb 18 01:28:31 PM PST 24
Finished Feb 18 01:33:18 PM PST 24
Peak memory 202280 kb
Host smart-c71c36e5-355f-4416-8899-1becf2e1cd1e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640489500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.1640489500
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.1088834634
Short name T536
Test name
Test status
Simulation time 2891151624 ps
CPU time 353.82 seconds
Started Feb 18 01:28:30 PM PST 24
Finished Feb 18 01:34:25 PM PST 24
Peak memory 370968 kb
Host smart-fe4c3355-ec33-4bc7-a585-fe89dc7a5da4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088834634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi
ple_keys.1088834634
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.1342921222
Short name T821
Test name
Test status
Simulation time 1165795942 ps
CPU time 94.48 seconds
Started Feb 18 01:28:30 PM PST 24
Finished Feb 18 01:30:05 PM PST 24
Peak memory 317632 kb
Host smart-d1476adc-c02b-4f8d-aa17-8b96a1f77828
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342921222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
sram_ctrl_partial_access.1342921222
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1916660042
Short name T601
Test name
Test status
Simulation time 8530586261 ps
CPU time 253.27 seconds
Started Feb 18 01:28:31 PM PST 24
Finished Feb 18 01:32:45 PM PST 24
Peak memory 202224 kb
Host smart-17225cee-1c94-4144-a42f-f7a9b628ff09
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916660042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.sram_ctrl_partial_access_b2b.1916660042
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.369931511
Short name T512
Test name
Test status
Simulation time 1200210342 ps
CPU time 6.53 seconds
Started Feb 18 01:28:35 PM PST 24
Finished Feb 18 01:28:42 PM PST 24
Peak memory 202440 kb
Host smart-f3d008bb-5699-4ac2-b115-994d37fe99f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369931511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.369931511
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.3091602480
Short name T403
Test name
Test status
Simulation time 140739024917 ps
CPU time 1710.38 seconds
Started Feb 18 01:28:47 PM PST 24
Finished Feb 18 01:57:21 PM PST 24
Peak memory 378188 kb
Host smart-29399352-cb37-41a2-97d8-9672463b862b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091602480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3091602480
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.3699913989
Short name T745
Test name
Test status
Simulation time 4530448389 ps
CPU time 17.55 seconds
Started Feb 18 01:28:31 PM PST 24
Finished Feb 18 01:28:49 PM PST 24
Peak memory 202248 kb
Host smart-a9606af2-59cc-463b-a1bf-993100626f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699913989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3699913989
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3744763348
Short name T720
Test name
Test status
Simulation time 48743284593 ps
CPU time 341.7 seconds
Started Feb 18 01:28:29 PM PST 24
Finished Feb 18 01:34:12 PM PST 24
Peak memory 202324 kb
Host smart-ec7e6605-81c9-4742-8126-6c3874919b45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744763348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.3744763348
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2202381054
Short name T136
Test name
Test status
Simulation time 3290737962 ps
CPU time 105.12 seconds
Started Feb 18 01:28:38 PM PST 24
Finished Feb 18 01:30:24 PM PST 24
Peak memory 349472 kb
Host smart-b405712a-d98f-473c-a4cf-e6586a20ae72
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202381054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.2202381054
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2024632544
Short name T210
Test name
Test status
Simulation time 7592606109 ps
CPU time 852.09 seconds
Started Feb 18 01:28:54 PM PST 24
Finished Feb 18 01:43:11 PM PST 24
Peak memory 370968 kb
Host smart-ab87b378-7fd3-4e12-8abf-3b894d79af47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024632544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.2024632544
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.2224241215
Short name T677
Test name
Test status
Simulation time 15982804 ps
CPU time 0.67 seconds
Started Feb 18 01:28:52 PM PST 24
Finished Feb 18 01:28:57 PM PST 24
Peak memory 202052 kb
Host smart-56104f2c-3ac9-4820-a609-3040db92be0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224241215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.2224241215
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.556070141
Short name T632
Test name
Test status
Simulation time 481231976296 ps
CPU time 2473.91 seconds
Started Feb 18 01:28:43 PM PST 24
Finished Feb 18 02:09:58 PM PST 24
Peak memory 210464 kb
Host smart-ea123b63-87c4-4331-9797-70c81df39062
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556070141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.
556070141
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.989756020
Short name T764
Test name
Test status
Simulation time 159156568697 ps
CPU time 1027.82 seconds
Started Feb 18 01:28:46 PM PST 24
Finished Feb 18 01:45:55 PM PST 24
Peak memory 374084 kb
Host smart-b248fbe6-a08c-4aa1-8e30-d26356e52404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989756020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executabl
e.989756020
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.3570432581
Short name T654
Test name
Test status
Simulation time 48126814958 ps
CPU time 123.33 seconds
Started Feb 18 01:28:54 PM PST 24
Finished Feb 18 01:31:03 PM PST 24
Peak memory 210820 kb
Host smart-ecf73e39-cdf9-41ae-a3b2-71b02d664955
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570432581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.3570432581
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.2651971667
Short name T680
Test name
Test status
Simulation time 711549702 ps
CPU time 38.34 seconds
Started Feb 18 01:28:49 PM PST 24
Finished Feb 18 01:29:29 PM PST 24
Peak memory 257216 kb
Host smart-55f85ed6-b1c6-42a6-8ace-e3e3a4467d19
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651971667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.2651971667
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.632206564
Short name T612
Test name
Test status
Simulation time 4826425586 ps
CPU time 145.9 seconds
Started Feb 18 01:28:48 PM PST 24
Finished Feb 18 01:31:17 PM PST 24
Peak memory 218608 kb
Host smart-98ba7324-79bd-4197-8f8c-15dbb614e8f0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632206564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_mem_partial_access.632206564
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.4037505716
Short name T193
Test name
Test status
Simulation time 21517085382 ps
CPU time 299.41 seconds
Started Feb 18 01:28:48 PM PST 24
Finished Feb 18 01:33:50 PM PST 24
Peak memory 202164 kb
Host smart-ddb32980-709a-48b2-b900-1eb9ad258f37
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037505716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.4037505716
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.644552556
Short name T163
Test name
Test status
Simulation time 90972076804 ps
CPU time 775.38 seconds
Started Feb 18 01:28:47 PM PST 24
Finished Feb 18 01:41:46 PM PST 24
Peak memory 373980 kb
Host smart-ebe4f44d-c86d-4b5b-b2dd-a3dd1487a6e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644552556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multip
le_keys.644552556
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.3438973757
Short name T598
Test name
Test status
Simulation time 2624108289 ps
CPU time 130.7 seconds
Started Feb 18 01:28:53 PM PST 24
Finished Feb 18 01:31:07 PM PST 24
Peak memory 349256 kb
Host smart-d2977b0b-dee3-47dd-8cd4-8b1674fe3e6e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438973757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.3438973757
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.485599204
Short name T438
Test name
Test status
Simulation time 6740584492 ps
CPU time 423.66 seconds
Started Feb 18 01:28:53 PM PST 24
Finished Feb 18 01:36:00 PM PST 24
Peak memory 202256 kb
Host smart-224fb6b9-71f2-45fe-bb6c-3234be4afcbf
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485599204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.sram_ctrl_partial_access_b2b.485599204
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.655197260
Short name T527
Test name
Test status
Simulation time 480911449 ps
CPU time 6.69 seconds
Started Feb 18 01:28:49 PM PST 24
Finished Feb 18 01:28:57 PM PST 24
Peak memory 202376 kb
Host smart-fcaa8401-0937-4f3b-8937-d14c7e9d197a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655197260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.655197260
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.3762824403
Short name T310
Test name
Test status
Simulation time 3624398305 ps
CPU time 280.06 seconds
Started Feb 18 01:28:48 PM PST 24
Finished Feb 18 01:33:31 PM PST 24
Peak memory 347600 kb
Host smart-816f3711-18d7-4963-bf64-5ae164f5db64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762824403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3762824403
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.3682404159
Short name T181
Test name
Test status
Simulation time 1750160646 ps
CPU time 72.23 seconds
Started Feb 18 01:28:42 PM PST 24
Finished Feb 18 01:29:55 PM PST 24
Peak memory 327944 kb
Host smart-38d7e73f-4f23-4862-ae49-dcdcda0dc88e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682404159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3682404159
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_all.1860194067
Short name T658
Test name
Test status
Simulation time 289751590407 ps
CPU time 2886.23 seconds
Started Feb 18 01:28:57 PM PST 24
Finished Feb 18 02:17:08 PM PST 24
Peak memory 380376 kb
Host smart-1e15e24f-981f-4663-a0ea-4b5319a8c204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860194067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.sram_ctrl_stress_all.1860194067
Directory /workspace/29.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.40666026
Short name T705
Test name
Test status
Simulation time 1821971310 ps
CPU time 136.55 seconds
Started Feb 18 01:28:48 PM PST 24
Finished Feb 18 01:31:07 PM PST 24
Peak memory 202168 kb
Host smart-be16510d-97ff-4fde-943d-42b224a923f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40666026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_stress_pipeline.40666026
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4246360239
Short name T498
Test name
Test status
Simulation time 13317472510 ps
CPU time 28.95 seconds
Started Feb 18 01:28:48 PM PST 24
Finished Feb 18 01:29:20 PM PST 24
Peak memory 210568 kb
Host smart-74cf74c8-3e98-4dd3-8f78-2f88e38a89c8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246360239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.4246360239
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.4186695779
Short name T183
Test name
Test status
Simulation time 2948091137 ps
CPU time 294.56 seconds
Started Feb 18 01:24:26 PM PST 24
Finished Feb 18 01:29:21 PM PST 24
Peak memory 341384 kb
Host smart-5cd3e9a1-cefb-4b3f-a014-bbb7d8645a3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186695779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_access_during_key_req.4186695779
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.749402992
Short name T799
Test name
Test status
Simulation time 45223364 ps
CPU time 0.63 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:24:21 PM PST 24
Peak memory 201728 kb
Host smart-05b4a255-02fd-4f37-806e-55c3065b066a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749402992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.749402992
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.2102364531
Short name T197
Test name
Test status
Simulation time 718799561258 ps
CPU time 2849.12 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 02:11:48 PM PST 24
Peak memory 202404 kb
Host smart-1f9ded36-897e-46ea-b75d-9d12f9da3ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102364531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2102364531
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.751791747
Short name T203
Test name
Test status
Simulation time 7715910040 ps
CPU time 432.85 seconds
Started Feb 18 01:24:15 PM PST 24
Finished Feb 18 01:31:30 PM PST 24
Peak memory 372032 kb
Host smart-d964776f-adf3-43a2-9ae5-1af7261877c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751791747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable
.751791747
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.3817910277
Short name T628
Test name
Test status
Simulation time 53306484864 ps
CPU time 146.13 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:26:48 PM PST 24
Peak memory 210492 kb
Host smart-d98e76c8-9766-4df2-90c7-a95c7fdb0877
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817910277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc
alation.3817910277
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.1637436857
Short name T369
Test name
Test status
Simulation time 4098334138 ps
CPU time 68.31 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 01:25:32 PM PST 24
Peak memory 316772 kb
Host smart-ba8e01e4-571a-47dc-8f6b-f663c7dd8d26
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637436857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_max_throughput.1637436857
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.3555404801
Short name T600
Test name
Test status
Simulation time 17361930872 ps
CPU time 147.72 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 01:26:51 PM PST 24
Peak memory 211276 kb
Host smart-319c0d90-92d1-4765-be6a-96b69ff49866
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555404801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.3555404801
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.2891891634
Short name T140
Test name
Test status
Simulation time 57409906745 ps
CPU time 281.96 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:29:03 PM PST 24
Peak memory 202260 kb
Host smart-1750e01e-05ac-4cd4-8a90-61bccf2fd98c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891891634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.2891891634
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2563811858
Short name T614
Test name
Test status
Simulation time 1966533868 ps
CPU time 54.63 seconds
Started Feb 18 01:24:13 PM PST 24
Finished Feb 18 01:25:08 PM PST 24
Peak memory 287900 kb
Host smart-dc77b489-4637-43a3-a81b-b0eae9d3d46d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563811858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2563811858
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.1409400003
Short name T698
Test name
Test status
Simulation time 3374965222 ps
CPU time 31.11 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 01:24:50 PM PST 24
Peak memory 202260 kb
Host smart-12f542d8-5a30-4fcf-bb88-66f4954866ac
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409400003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s
ram_ctrl_partial_access.1409400003
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.326037488
Short name T590
Test name
Test status
Simulation time 4415072449 ps
CPU time 265.6 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:28:47 PM PST 24
Peak memory 202240 kb
Host smart-fd24330a-e217-479e-be68-c482c4b1bacd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326037488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.sram_ctrl_partial_access_b2b.326037488
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.301335162
Short name T247
Test name
Test status
Simulation time 679370204 ps
CPU time 6.55 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 01:24:26 PM PST 24
Peak memory 202420 kb
Host smart-0a2165aa-61ac-48a8-bea3-30731229ed42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301335162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.301335162
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1416201670
Short name T237
Test name
Test status
Simulation time 46490794826 ps
CPU time 1392.65 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 01:47:36 PM PST 24
Peak memory 367588 kb
Host smart-837d0e7e-0d6e-40ac-987d-67437c8544fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416201670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1416201670
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.2537066012
Short name T19
Test name
Test status
Simulation time 305406217 ps
CPU time 1.91 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:24:23 PM PST 24
Peak memory 221100 kb
Host smart-47814a34-ae13-4862-b9a5-90080e596105
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537066012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.2537066012
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.3827960898
Short name T164
Test name
Test status
Simulation time 2097771352 ps
CPU time 21.18 seconds
Started Feb 18 01:24:17 PM PST 24
Finished Feb 18 01:24:39 PM PST 24
Peak memory 202096 kb
Host smart-bf752c66-f618-48a9-8d31-9d0ac87124af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827960898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3827960898
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.3292930319
Short name T211
Test name
Test status
Simulation time 70253897499 ps
CPU time 1408.53 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:47:50 PM PST 24
Peak memory 369952 kb
Host smart-70d3e66a-22ec-421f-8cff-8ca8d6276894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292930319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.3292930319
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2919884658
Short name T837
Test name
Test status
Simulation time 4310764618 ps
CPU time 255.68 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:28:36 PM PST 24
Peak memory 215568 kb
Host smart-5f6e2f4e-a3ca-4e66-9b6f-1c0670eadfeb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919884658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.2919884658
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1360305273
Short name T480
Test name
Test status
Simulation time 1519586637 ps
CPU time 114.82 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 01:26:13 PM PST 24
Peak memory 335016 kb
Host smart-c7bc5022-9fd6-4c73-a106-079d85eb5709
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360305273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.1360305273
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3853799377
Short name T350
Test name
Test status
Simulation time 2243766117 ps
CPU time 133.58 seconds
Started Feb 18 01:28:57 PM PST 24
Finished Feb 18 01:31:15 PM PST 24
Peak memory 272520 kb
Host smart-1cf66d12-897b-4781-a497-82d47d2b723d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853799377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.3853799377
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.4181000604
Short name T828
Test name
Test status
Simulation time 24829718 ps
CPU time 0.68 seconds
Started Feb 18 01:28:59 PM PST 24
Finished Feb 18 01:29:03 PM PST 24
Peak memory 202036 kb
Host smart-cb3cd12a-8702-4ec8-b8dc-10def4234f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181000604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.4181000604
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.2599284256
Short name T278
Test name
Test status
Simulation time 50648977479 ps
CPU time 825.21 seconds
Started Feb 18 01:28:53 PM PST 24
Finished Feb 18 01:42:42 PM PST 24
Peak memory 202272 kb
Host smart-1ebbd8c1-2dca-4a90-9caa-0f56f5260ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599284256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.2599284256
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.113553232
Short name T13
Test name
Test status
Simulation time 17089478523 ps
CPU time 537.18 seconds
Started Feb 18 01:28:55 PM PST 24
Finished Feb 18 01:37:58 PM PST 24
Peak memory 369464 kb
Host smart-255c5e20-972b-44d8-b0ca-6dfeb00d8bae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113553232 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl
e.113553232
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.3939149367
Short name T195
Test name
Test status
Simulation time 32853357913 ps
CPU time 81.59 seconds
Started Feb 18 01:28:53 PM PST 24
Finished Feb 18 01:30:18 PM PST 24
Peak memory 210444 kb
Host smart-b14cd68c-cf6e-499b-8e7b-36b560d6e2fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939149367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es
calation.3939149367
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.3423648308
Short name T732
Test name
Test status
Simulation time 1516486396 ps
CPU time 31.76 seconds
Started Feb 18 01:29:00 PM PST 24
Finished Feb 18 01:29:35 PM PST 24
Peak memory 226408 kb
Host smart-ab73eaaa-7951-4bdd-8acd-64f27fe7510f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423648308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.3423648308
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3935298813
Short name T597
Test name
Test status
Simulation time 1004816815 ps
CPU time 73.84 seconds
Started Feb 18 01:28:58 PM PST 24
Finished Feb 18 01:30:16 PM PST 24
Peak memory 211352 kb
Host smart-a8b6859b-dc65-4de0-bed0-74cbb44e3910
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935298813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.3935298813
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.3325106549
Short name T737
Test name
Test status
Simulation time 14064331472 ps
CPU time 147.33 seconds
Started Feb 18 01:28:57 PM PST 24
Finished Feb 18 01:31:30 PM PST 24
Peak memory 202668 kb
Host smart-4ff50b08-4160-4cd7-824a-4bba066eaba7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325106549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.3325106549
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.2970238983
Short name T406
Test name
Test status
Simulation time 2352555728 ps
CPU time 225.97 seconds
Started Feb 18 01:28:52 PM PST 24
Finished Feb 18 01:32:43 PM PST 24
Peak memory 375960 kb
Host smart-f35f9894-c3f8-4dd0-980f-3a3fd85b4a13
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970238983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.2970238983
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.3553158771
Short name T573
Test name
Test status
Simulation time 2214447139 ps
CPU time 25.68 seconds
Started Feb 18 01:29:00 PM PST 24
Finished Feb 18 01:29:29 PM PST 24
Peak memory 254480 kb
Host smart-31cff86e-a72a-4709-b5cf-b129f982d19e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553158771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.3553158771
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1727705434
Short name T733
Test name
Test status
Simulation time 17154892253 ps
CPU time 539.01 seconds
Started Feb 18 01:28:51 PM PST 24
Finished Feb 18 01:37:55 PM PST 24
Peak memory 202236 kb
Host smart-e959c09e-61fd-4263-80a4-9de40b1b46c5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727705434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.sram_ctrl_partial_access_b2b.1727705434
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.4161617067
Short name T627
Test name
Test status
Simulation time 1414894131 ps
CPU time 14.01 seconds
Started Feb 18 01:29:00 PM PST 24
Finished Feb 18 01:29:17 PM PST 24
Peak memory 202452 kb
Host smart-378edafe-17cd-4e9f-8989-d90073fc96ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161617067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.4161617067
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.2125423404
Short name T676
Test name
Test status
Simulation time 29071216552 ps
CPU time 631.64 seconds
Started Feb 18 01:28:53 PM PST 24
Finished Feb 18 01:39:29 PM PST 24
Peak memory 373048 kb
Host smart-30eed7fc-de62-4d7c-a737-f391f558d088
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125423404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2125423404
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.914434061
Short name T208
Test name
Test status
Simulation time 1760932659 ps
CPU time 146.1 seconds
Started Feb 18 01:28:54 PM PST 24
Finished Feb 18 01:31:26 PM PST 24
Peak memory 360600 kb
Host smart-7186cf15-62a1-4ea7-9c76-6ab85ef43765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914434061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.914434061
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3092354947
Short name T145
Test name
Test status
Simulation time 23685892720 ps
CPU time 468.31 seconds
Started Feb 18 01:28:57 PM PST 24
Finished Feb 18 01:36:50 PM PST 24
Peak memory 202316 kb
Host smart-6cd6838e-307c-4c63-9af2-9ed192925bb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092354947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.3092354947
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.4061077490
Short name T205
Test name
Test status
Simulation time 1701850067 ps
CPU time 156.8 seconds
Started Feb 18 01:28:51 PM PST 24
Finished Feb 18 01:31:33 PM PST 24
Peak memory 365844 kb
Host smart-7708d58a-7a06-4dc8-ab46-73fda0d1818d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061077490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.4061077490
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1040349333
Short name T207
Test name
Test status
Simulation time 32271062182 ps
CPU time 1045.84 seconds
Started Feb 18 01:29:08 PM PST 24
Finished Feb 18 01:46:36 PM PST 24
Peak memory 372436 kb
Host smart-b43aacc1-79c1-432d-a88b-669aa40c1f35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040349333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.1040349333
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.2093160724
Short name T366
Test name
Test status
Simulation time 66370100 ps
CPU time 0.64 seconds
Started Feb 18 01:29:13 PM PST 24
Finished Feb 18 01:29:14 PM PST 24
Peak memory 201664 kb
Host smart-e29db2b5-d49e-4cbb-8600-f9c4e219a6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093160724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.2093160724
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.2318451406
Short name T155
Test name
Test status
Simulation time 88842580098 ps
CPU time 1456.19 seconds
Started Feb 18 01:29:08 PM PST 24
Finished Feb 18 01:53:27 PM PST 24
Peak memory 202296 kb
Host smart-250d9114-0f81-4322-a016-04629f5e446e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318451406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection
.2318451406
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2161099900
Short name T368
Test name
Test status
Simulation time 8904604906 ps
CPU time 186.1 seconds
Started Feb 18 01:28:58 PM PST 24
Finished Feb 18 01:32:09 PM PST 24
Peak memory 210564 kb
Host smart-289fdf97-896d-485c-b3db-aead23ec0d93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161099900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2161099900
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.493832094
Short name T494
Test name
Test status
Simulation time 727934202 ps
CPU time 47.98 seconds
Started Feb 18 01:28:58 PM PST 24
Finished Feb 18 01:29:50 PM PST 24
Peak memory 291760 kb
Host smart-f40a1fe3-29bf-4317-aa31-c1a8f7b02ab3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493832094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.sram_ctrl_max_throughput.493832094
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.389209196
Short name T408
Test name
Test status
Simulation time 9406830616 ps
CPU time 75.39 seconds
Started Feb 18 01:29:08 PM PST 24
Finished Feb 18 01:30:26 PM PST 24
Peak memory 210788 kb
Host smart-7eb1aad0-c584-4951-a153-3f8e9bc41802
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389209196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.sram_ctrl_mem_partial_access.389209196
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.3567577190
Short name T766
Test name
Test status
Simulation time 73790378938 ps
CPU time 325.1 seconds
Started Feb 18 01:29:07 PM PST 24
Finished Feb 18 01:34:34 PM PST 24
Peak memory 202364 kb
Host smart-ec5c2346-b2ef-4854-954f-6acb9e1cdfc9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567577190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.3567577190
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.781627587
Short name T543
Test name
Test status
Simulation time 12026884453 ps
CPU time 182.49 seconds
Started Feb 18 01:28:58 PM PST 24
Finished Feb 18 01:32:05 PM PST 24
Peak memory 304512 kb
Host smart-5790732b-cfbe-4cd0-a70b-f1f268e01e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781627587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multip
le_keys.781627587
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.435610009
Short name T319
Test name
Test status
Simulation time 6468634886 ps
CPU time 29.14 seconds
Started Feb 18 01:28:59 PM PST 24
Finished Feb 18 01:29:32 PM PST 24
Peak memory 210484 kb
Host smart-747b5ef7-837e-407b-b0cc-79e6b4009840
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435610009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.s
ram_ctrl_partial_access.435610009
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.917645005
Short name T263
Test name
Test status
Simulation time 79394125106 ps
CPU time 538.5 seconds
Started Feb 18 01:29:08 PM PST 24
Finished Feb 18 01:38:09 PM PST 24
Peak memory 216576 kb
Host smart-aa2b99ce-624e-4062-b309-91bfc915d2da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917645005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.sram_ctrl_partial_access_b2b.917645005
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.3024232408
Short name T3
Test name
Test status
Simulation time 2116833516 ps
CPU time 13.95 seconds
Started Feb 18 01:29:05 PM PST 24
Finished Feb 18 01:29:21 PM PST 24
Peak memory 202468 kb
Host smart-a965baab-836b-44e1-a93a-d4c60b7234ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024232408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3024232408
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.524430479
Short name T690
Test name
Test status
Simulation time 35677706347 ps
CPU time 1094.19 seconds
Started Feb 18 01:29:05 PM PST 24
Finished Feb 18 01:47:21 PM PST 24
Peak memory 378168 kb
Host smart-d00a1c6a-7feb-4987-8e48-b6121f17cc7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524430479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.524430479
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.2962452139
Short name T846
Test name
Test status
Simulation time 11853818948 ps
CPU time 114.42 seconds
Started Feb 18 01:29:08 PM PST 24
Finished Feb 18 01:31:05 PM PST 24
Peak memory 341200 kb
Host smart-1fd4d191-9dff-4d2e-bb08-445de33009b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962452139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2962452139
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1779566937
Short name T534
Test name
Test status
Simulation time 2433464166 ps
CPU time 198.04 seconds
Started Feb 18 01:29:08 PM PST 24
Finished Feb 18 01:32:27 PM PST 24
Peak memory 202232 kb
Host smart-ee00c7b1-8d1f-4b59-8fa2-1830e04d0cce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779566937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.1779566937
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2189802998
Short name T449
Test name
Test status
Simulation time 762586981 ps
CPU time 72.92 seconds
Started Feb 18 01:28:59 PM PST 24
Finished Feb 18 01:30:15 PM PST 24
Peak memory 306016 kb
Host smart-b01d3597-bb11-42ef-ad3f-6fe20247e080
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189802998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2189802998
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.632931573
Short name T378
Test name
Test status
Simulation time 8449477089 ps
CPU time 668.75 seconds
Started Feb 18 01:29:14 PM PST 24
Finished Feb 18 01:40:24 PM PST 24
Peak memory 377144 kb
Host smart-001c5af1-63d6-4a8c-9996-a627a553586d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632931573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 32.sram_ctrl_access_during_key_req.632931573
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.3479323274
Short name T735
Test name
Test status
Simulation time 14293041 ps
CPU time 0.66 seconds
Started Feb 18 01:29:16 PM PST 24
Finished Feb 18 01:29:17 PM PST 24
Peak memory 201732 kb
Host smart-382fa323-3650-4d02-8667-15873f84b092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479323274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.3479323274
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.3312743022
Short name T681
Test name
Test status
Simulation time 49527743955 ps
CPU time 790.79 seconds
Started Feb 18 01:29:14 PM PST 24
Finished Feb 18 01:42:25 PM PST 24
Peak memory 202296 kb
Host smart-28be809e-50a0-4bc2-8238-903825ea3581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312743022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection
.3312743022
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.323415988
Short name T744
Test name
Test status
Simulation time 88355249656 ps
CPU time 405.11 seconds
Started Feb 18 01:29:13 PM PST 24
Finished Feb 18 01:35:59 PM PST 24
Peak memory 370988 kb
Host smart-d34d8476-41b7-4793-9529-d8ab1d5f1a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323415988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executabl
e.323415988
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.1732155436
Short name T556
Test name
Test status
Simulation time 62618610654 ps
CPU time 184.18 seconds
Started Feb 18 01:29:14 PM PST 24
Finished Feb 18 01:32:19 PM PST 24
Peak memory 210440 kb
Host smart-57d07c0f-ebc2-487a-8b53-8acdb6729ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732155436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.1732155436
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.1227845459
Short name T149
Test name
Test status
Simulation time 3039192875 ps
CPU time 128.62 seconds
Started Feb 18 01:29:15 PM PST 24
Finished Feb 18 01:31:24 PM PST 24
Peak memory 357676 kb
Host smart-e39217a6-6dfb-4296-b228-fdb8a39366b8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227845459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sram_ctrl_max_throughput.1227845459
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.701486971
Short name T184
Test name
Test status
Simulation time 1971755279 ps
CPU time 75.82 seconds
Started Feb 18 01:29:12 PM PST 24
Finished Feb 18 01:30:29 PM PST 24
Peak memory 218556 kb
Host smart-040b72fa-0531-4d61-b636-aa532958181f
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701486971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.sram_ctrl_mem_partial_access.701486971
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.491758057
Short name T568
Test name
Test status
Simulation time 3982907269 ps
CPU time 261.05 seconds
Started Feb 18 01:29:13 PM PST 24
Finished Feb 18 01:33:35 PM PST 24
Peak memory 202180 kb
Host smart-9b484241-6085-482f-9675-237a7c2cdcf6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491758057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl
_mem_walk.491758057
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.139619092
Short name T131
Test name
Test status
Simulation time 17668868164 ps
CPU time 712.83 seconds
Started Feb 18 01:29:14 PM PST 24
Finished Feb 18 01:41:08 PM PST 24
Peak memory 377744 kb
Host smart-20525049-69fe-4e4e-9f4b-c0a72101485b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139619092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multip
le_keys.139619092
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1668132487
Short name T848
Test name
Test status
Simulation time 1920553753 ps
CPU time 9.94 seconds
Started Feb 18 01:29:13 PM PST 24
Finished Feb 18 01:29:23 PM PST 24
Peak memory 202112 kb
Host smart-401e224c-d88a-42d9-bae2-ac5eb9f3ed3b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668132487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1668132487
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.1147083205
Short name T486
Test name
Test status
Simulation time 1973760947 ps
CPU time 5.93 seconds
Started Feb 18 01:29:16 PM PST 24
Finished Feb 18 01:29:23 PM PST 24
Peak memory 202420 kb
Host smart-99ccdbc8-c533-4bfa-b8d7-a729addd3947
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147083205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1147083205
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.2967557406
Short name T419
Test name
Test status
Simulation time 113750979797 ps
CPU time 1448.62 seconds
Started Feb 18 01:29:25 PM PST 24
Finished Feb 18 01:53:35 PM PST 24
Peak memory 380204 kb
Host smart-b4dedba2-d45c-432f-b378-ddc279cfb077
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967557406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2967557406
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.3910996928
Short name T841
Test name
Test status
Simulation time 3190040395 ps
CPU time 19.36 seconds
Started Feb 18 01:29:17 PM PST 24
Finished Feb 18 01:29:37 PM PST 24
Peak memory 202308 kb
Host smart-20189af8-7cea-4660-b6b9-12b926764f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910996928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3910996928
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.3768382800
Short name T714
Test name
Test status
Simulation time 244824254107 ps
CPU time 4407.71 seconds
Started Feb 18 01:29:14 PM PST 24
Finished Feb 18 02:42:43 PM PST 24
Peak memory 375068 kb
Host smart-940546ca-e7c9-4a64-97f7-75575da8afa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768382800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.sram_ctrl_stress_all.3768382800
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3178741151
Short name T577
Test name
Test status
Simulation time 6095726754 ps
CPU time 371.21 seconds
Started Feb 18 01:29:13 PM PST 24
Finished Feb 18 01:35:25 PM PST 24
Peak memory 202316 kb
Host smart-bb81f019-9da9-45c9-9bc6-9bc94a133613
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178741151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.3178741151
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2219756511
Short name T514
Test name
Test status
Simulation time 9480165304 ps
CPU time 135.97 seconds
Started Feb 18 01:29:14 PM PST 24
Finished Feb 18 01:31:30 PM PST 24
Peak memory 338304 kb
Host smart-6aa907e8-dffa-43e0-8ee3-7ca5280ad754
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219756511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2219756511
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2723852224
Short name T786
Test name
Test status
Simulation time 12174394888 ps
CPU time 1891.92 seconds
Started Feb 18 01:29:19 PM PST 24
Finished Feb 18 02:00:52 PM PST 24
Peak memory 376044 kb
Host smart-083f55b7-e317-4013-8e9a-05295917fbaf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723852224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.2723852224
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.4148746954
Short name T478
Test name
Test status
Simulation time 17144235 ps
CPU time 0.66 seconds
Started Feb 18 01:29:28 PM PST 24
Finished Feb 18 01:29:29 PM PST 24
Peak memory 202032 kb
Host smart-94bd9502-2759-4b44-9e79-3d01ce342ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148746954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.4148746954
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.4131835162
Short name T30
Test name
Test status
Simulation time 260248727449 ps
CPU time 703.15 seconds
Started Feb 18 01:29:20 PM PST 24
Finished Feb 18 01:41:04 PM PST 24
Peak memory 210492 kb
Host smart-bfb558c7-1828-4401-8ef1-37f47446c986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131835162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.4131835162
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.2519585789
Short name T822
Test name
Test status
Simulation time 13758958983 ps
CPU time 798.53 seconds
Started Feb 18 01:29:22 PM PST 24
Finished Feb 18 01:42:41 PM PST 24
Peak memory 368560 kb
Host smart-9efdeeb1-0c27-4d76-8540-9d1f377d7166
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519585789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab
le.2519585789
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.754035157
Short name T342
Test name
Test status
Simulation time 4386453861 ps
CPU time 102.96 seconds
Started Feb 18 01:29:22 PM PST 24
Finished Feb 18 01:31:06 PM PST 24
Peak memory 202364 kb
Host smart-82cb1b97-15f7-4bbd-a582-5daf39a04fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754035157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc
alation.754035157
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.2617129632
Short name T325
Test name
Test status
Simulation time 1455198152 ps
CPU time 50 seconds
Started Feb 18 01:29:20 PM PST 24
Finished Feb 18 01:30:10 PM PST 24
Peak memory 273292 kb
Host smart-c5dff2fa-c01d-4477-8e3d-91e50dcc7196
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617129632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.2617129632
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3166071226
Short name T393
Test name
Test status
Simulation time 3101956416 ps
CPU time 133.7 seconds
Started Feb 18 01:29:21 PM PST 24
Finished Feb 18 01:31:36 PM PST 24
Peak memory 214528 kb
Host smart-5a36cf61-cff1-49af-952f-878b0063ee2b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166071226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.3166071226
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.3330180044
Short name T298
Test name
Test status
Simulation time 14209560810 ps
CPU time 292.88 seconds
Started Feb 18 01:29:17 PM PST 24
Finished Feb 18 01:34:11 PM PST 24
Peak memory 202248 kb
Host smart-7623c4a7-956f-4bb4-9a0c-cc3375cbb2e8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330180044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr
l_mem_walk.3330180044
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.2539724294
Short name T333
Test name
Test status
Simulation time 14608012289 ps
CPU time 2076.91 seconds
Started Feb 18 01:29:21 PM PST 24
Finished Feb 18 02:03:59 PM PST 24
Peak memory 380224 kb
Host smart-14c13534-5c53-4dfc-8c6f-9147a05dd1a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539724294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi
ple_keys.2539724294
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.2127332847
Short name T489
Test name
Test status
Simulation time 12029412401 ps
CPU time 31.54 seconds
Started Feb 18 01:29:20 PM PST 24
Finished Feb 18 01:29:52 PM PST 24
Peak memory 202288 kb
Host smart-adf1bd56-54fd-42be-8c8e-ff9e2ceb2c98
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127332847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.2127332847
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.645843949
Short name T773
Test name
Test status
Simulation time 58744094233 ps
CPU time 224.37 seconds
Started Feb 18 01:29:24 PM PST 24
Finished Feb 18 01:33:09 PM PST 24
Peak memory 202236 kb
Host smart-e3b39866-8eb3-49aa-b8e7-faa36046dd95
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645843949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.sram_ctrl_partial_access_b2b.645843949
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.2451533725
Short name T36
Test name
Test status
Simulation time 1298033921 ps
CPU time 13.82 seconds
Started Feb 18 01:29:20 PM PST 24
Finished Feb 18 01:29:34 PM PST 24
Peak memory 202472 kb
Host smart-4069ec99-595c-469d-82b4-87d0ce717bb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451533725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2451533725
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.2763399207
Short name T301
Test name
Test status
Simulation time 48797069193 ps
CPU time 1503.51 seconds
Started Feb 18 01:29:21 PM PST 24
Finished Feb 18 01:54:25 PM PST 24
Peak memory 378180 kb
Host smart-9718428f-40f4-4aa0-a12b-76d9222a3168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763399207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.2763399207
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.1812280146
Short name T165
Test name
Test status
Simulation time 2792380220 ps
CPU time 135.65 seconds
Started Feb 18 01:29:18 PM PST 24
Finished Feb 18 01:31:34 PM PST 24
Peak memory 373212 kb
Host smart-cd2a9f1f-a7c0-4b61-bd5b-e17755600311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812280146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1812280146
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.4136494122
Short name T320
Test name
Test status
Simulation time 19859147457 ps
CPU time 312.21 seconds
Started Feb 18 01:29:20 PM PST 24
Finished Feb 18 01:34:33 PM PST 24
Peak memory 210464 kb
Host smart-d58d4ae7-ae7d-49ab-b546-4c664565498d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136494122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.4136494122
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1543652484
Short name T717
Test name
Test status
Simulation time 4157244799 ps
CPU time 40.88 seconds
Started Feb 18 01:29:16 PM PST 24
Finished Feb 18 01:29:58 PM PST 24
Peak memory 263052 kb
Host smart-0fc6012c-76d6-4128-98ac-fbd2694df155
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543652484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.1543652484
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.503054463
Short name T578
Test name
Test status
Simulation time 3665675559 ps
CPU time 296.43 seconds
Started Feb 18 01:29:33 PM PST 24
Finished Feb 18 01:34:30 PM PST 24
Peak memory 366872 kb
Host smart-19a8f9e2-f4ec-418b-a148-b35224a1ce55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503054463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.sram_ctrl_access_during_key_req.503054463
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.1281801321
Short name T153
Test name
Test status
Simulation time 12561665 ps
CPU time 0.63 seconds
Started Feb 18 01:29:33 PM PST 24
Finished Feb 18 01:29:35 PM PST 24
Peak memory 201648 kb
Host smart-c619f819-25de-4bcd-ad49-bbe526cc3e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281801321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.1281801321
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.3913959735
Short name T380
Test name
Test status
Simulation time 95927742632 ps
CPU time 2143.46 seconds
Started Feb 18 01:29:26 PM PST 24
Finished Feb 18 02:05:10 PM PST 24
Peak memory 210468 kb
Host smart-88a4c733-3ce6-4e48-8ab7-4befa13e844e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913959735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.3913959735
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.2195926449
Short name T400
Test name
Test status
Simulation time 70153096625 ps
CPU time 409.81 seconds
Started Feb 18 01:29:35 PM PST 24
Finished Feb 18 01:36:25 PM PST 24
Peak memory 361880 kb
Host smart-421020dc-7537-417d-8017-fdc510f27d58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195926449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.2195926449
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.1256345423
Short name T608
Test name
Test status
Simulation time 77717582213 ps
CPU time 125.89 seconds
Started Feb 18 01:29:37 PM PST 24
Finished Feb 18 01:31:45 PM PST 24
Peak memory 202216 kb
Host smart-f739c8e1-ab4e-47f7-946b-4cd97eeaad7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256345423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.1256345423
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.3944230453
Short name T825
Test name
Test status
Simulation time 1460805115 ps
CPU time 53.91 seconds
Started Feb 18 01:29:32 PM PST 24
Finished Feb 18 01:30:27 PM PST 24
Peak memory 288048 kb
Host smart-b14aa12b-b98f-4693-8339-6d6f3944c79c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944230453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.3944230453
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.117730600
Short name T196
Test name
Test status
Simulation time 1604320237 ps
CPU time 132.97 seconds
Started Feb 18 01:29:36 PM PST 24
Finished Feb 18 01:31:50 PM PST 24
Peak memory 210684 kb
Host smart-b7f3d777-aeb0-4aa3-864e-6023d422ae35
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117730600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_mem_partial_access.117730600
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.2050482321
Short name T634
Test name
Test status
Simulation time 127656997392 ps
CPU time 321.88 seconds
Started Feb 18 01:29:34 PM PST 24
Finished Feb 18 01:34:56 PM PST 24
Peak memory 202704 kb
Host smart-b47b56aa-6a82-4a6a-ad9f-2389c5997c76
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050482321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.2050482321
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.3392838166
Short name T843
Test name
Test status
Simulation time 14736461337 ps
CPU time 1293.54 seconds
Started Feb 18 01:29:34 PM PST 24
Finished Feb 18 01:51:08 PM PST 24
Peak memory 379220 kb
Host smart-4e9b4c71-1610-498b-9c6e-7510efd70596
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392838166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.3392838166
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.3625024571
Short name T275
Test name
Test status
Simulation time 1537910843 ps
CPU time 16.09 seconds
Started Feb 18 01:29:34 PM PST 24
Finished Feb 18 01:29:50 PM PST 24
Peak memory 211296 kb
Host smart-2f8aaeac-a55d-4c2a-9dca-6fe718038421
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625024571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.3625024571
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3694265379
Short name T647
Test name
Test status
Simulation time 6095326824 ps
CPU time 327.49 seconds
Started Feb 18 01:29:33 PM PST 24
Finished Feb 18 01:35:01 PM PST 24
Peak memory 202212 kb
Host smart-7afa1d61-917e-48b8-b798-e2a3168046ad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694265379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.sram_ctrl_partial_access_b2b.3694265379
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.3183886810
Short name T560
Test name
Test status
Simulation time 720488373 ps
CPU time 5.58 seconds
Started Feb 18 01:29:34 PM PST 24
Finished Feb 18 01:29:40 PM PST 24
Peak memory 202480 kb
Host smart-06baa710-0c52-4ff4-b2b1-33a30f01bd1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183886810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3183886810
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.247414695
Short name T21
Test name
Test status
Simulation time 22765782828 ps
CPU time 627.91 seconds
Started Feb 18 01:29:37 PM PST 24
Finished Feb 18 01:40:07 PM PST 24
Peak memory 368932 kb
Host smart-b81d95a6-2485-4fdd-a5c9-3c6be866510a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247414695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.247414695
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.2381248506
Short name T519
Test name
Test status
Simulation time 4602937160 ps
CPU time 15.14 seconds
Started Feb 18 01:29:29 PM PST 24
Finished Feb 18 01:29:45 PM PST 24
Peak memory 210488 kb
Host smart-4774cb22-4f68-48ed-9d73-9d310cdc125a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381248506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2381248506
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_all.3535308055
Short name T382
Test name
Test status
Simulation time 457216586160 ps
CPU time 3718.41 seconds
Started Feb 18 01:29:34 PM PST 24
Finished Feb 18 02:31:33 PM PST 24
Peak memory 218068 kb
Host smart-d43f0a2e-5edd-4891-852a-e618e7cc1415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535308055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.sram_ctrl_stress_all.3535308055
Directory /workspace/34.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.3974896432
Short name T836
Test name
Test status
Simulation time 10647308491 ps
CPU time 405.64 seconds
Started Feb 18 01:29:32 PM PST 24
Finished Feb 18 01:36:19 PM PST 24
Peak memory 202284 kb
Host smart-4d172796-0ad7-4b5e-91b8-c80f8758d164
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974896432 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.sram_ctrl_stress_pipeline.3974896432
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2952366905
Short name T340
Test name
Test status
Simulation time 1448124620 ps
CPU time 40.58 seconds
Started Feb 18 01:29:31 PM PST 24
Finished Feb 18 01:30:12 PM PST 24
Peak memory 258356 kb
Host smart-681dc6a0-2627-4d89-a739-4992b2689e34
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952366905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2952366905
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2051608456
Short name T758
Test name
Test status
Simulation time 21114616371 ps
CPU time 1263.2 seconds
Started Feb 18 01:29:41 PM PST 24
Finished Feb 18 01:50:46 PM PST 24
Peak memory 379200 kb
Host smart-b11254f8-ff25-4d6d-8e46-6e4c2a841344
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051608456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.2051608456
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.1431566097
Short name T397
Test name
Test status
Simulation time 15587992 ps
CPU time 0.65 seconds
Started Feb 18 01:29:39 PM PST 24
Finished Feb 18 01:29:42 PM PST 24
Peak memory 202076 kb
Host smart-8ee2acbe-25af-49f7-b313-29df4c036938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431566097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.1431566097
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.1406761482
Short name T307
Test name
Test status
Simulation time 241377511743 ps
CPU time 1962.55 seconds
Started Feb 18 01:29:33 PM PST 24
Finished Feb 18 02:02:16 PM PST 24
Peak memory 202436 kb
Host smart-30463755-e3f3-43f7-81ce-43f03833626f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406761482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.1406761482
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.4238297567
Short name T736
Test name
Test status
Simulation time 20781528143 ps
CPU time 87.51 seconds
Started Feb 18 01:29:40 PM PST 24
Finished Feb 18 01:31:09 PM PST 24
Peak memory 210536 kb
Host smart-84a9b6bd-ac78-4b6f-b77f-301ab4131d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238297567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.4238297567
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.4221590723
Short name T703
Test name
Test status
Simulation time 1490744759 ps
CPU time 76.96 seconds
Started Feb 18 01:29:38 PM PST 24
Finished Feb 18 01:30:57 PM PST 24
Peak memory 330132 kb
Host smart-06ce117b-ddc2-4b47-9120-eb10f789f78c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221590723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.4221590723
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2009283966
Short name T685
Test name
Test status
Simulation time 9784214761 ps
CPU time 79.37 seconds
Started Feb 18 01:29:37 PM PST 24
Finished Feb 18 01:30:59 PM PST 24
Peak memory 218596 kb
Host smart-70b9ea3f-4b31-4bd4-98a9-7f2f6891ba2a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009283966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_mem_partial_access.2009283966
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.1065568752
Short name T619
Test name
Test status
Simulation time 21272256774 ps
CPU time 298.36 seconds
Started Feb 18 01:29:38 PM PST 24
Finished Feb 18 01:34:39 PM PST 24
Peak memory 202360 kb
Host smart-640e7887-c76b-48ea-8c46-f920ca4e85e1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065568752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.1065568752
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.3956452353
Short name T771
Test name
Test status
Simulation time 12031023725 ps
CPU time 606.16 seconds
Started Feb 18 01:29:35 PM PST 24
Finished Feb 18 01:39:42 PM PST 24
Peak memory 374032 kb
Host smart-a0b0c965-040c-43b3-a0cd-0b22270314d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956452353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.3956452353
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.3716538978
Short name T722
Test name
Test status
Simulation time 963852416 ps
CPU time 14.65 seconds
Started Feb 18 01:29:38 PM PST 24
Finished Feb 18 01:29:55 PM PST 24
Peak memory 210288 kb
Host smart-9b1d7b52-6cfa-455e-b716-27bb5a58c2d6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716538978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
sram_ctrl_partial_access.3716538978
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3697789731
Short name T537
Test name
Test status
Simulation time 7384876316 ps
CPU time 330.59 seconds
Started Feb 18 01:29:37 PM PST 24
Finished Feb 18 01:35:09 PM PST 24
Peak memory 202304 kb
Host smart-34bead07-c7d7-4080-9a33-e111a966fe46
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697789731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.3697789731
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.1293537394
Short name T689
Test name
Test status
Simulation time 354860824 ps
CPU time 6.76 seconds
Started Feb 18 01:29:38 PM PST 24
Finished Feb 18 01:29:47 PM PST 24
Peak memory 202448 kb
Host smart-fed6bed5-666d-4412-b5ee-2acf47ab4bf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293537394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1293537394
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.1114184602
Short name T362
Test name
Test status
Simulation time 14184217840 ps
CPU time 734.02 seconds
Started Feb 18 01:29:41 PM PST 24
Finished Feb 18 01:41:57 PM PST 24
Peak memory 377156 kb
Host smart-4f7948fb-8a40-4dd7-9d3d-fb642bc3d34e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114184602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1114184602
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.3041430102
Short name T189
Test name
Test status
Simulation time 1652955261 ps
CPU time 35.71 seconds
Started Feb 18 01:29:36 PM PST 24
Finished Feb 18 01:30:14 PM PST 24
Peak memory 202180 kb
Host smart-c95e59e5-1a10-49f7-82aa-73695e4d395d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041430102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3041430102
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.884308417
Short name T335
Test name
Test status
Simulation time 99047940307 ps
CPU time 2107.75 seconds
Started Feb 18 01:29:39 PM PST 24
Finished Feb 18 02:04:49 PM PST 24
Peak memory 368912 kb
Host smart-2ce3e093-c8c3-4e65-af3a-4d755145644b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884308417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_stress_all.884308417
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.3847115346
Short name T334
Test name
Test status
Simulation time 6041433102 ps
CPU time 427.5 seconds
Started Feb 18 01:29:37 PM PST 24
Finished Feb 18 01:36:46 PM PST 24
Peak memory 210468 kb
Host smart-a4677e19-2175-4d84-87af-43316d9bc85e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847115346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.sram_ctrl_stress_pipeline.3847115346
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1520383773
Short name T473
Test name
Test status
Simulation time 2879082096 ps
CPU time 70.33 seconds
Started Feb 18 01:29:39 PM PST 24
Finished Feb 18 01:30:51 PM PST 24
Peak memory 310624 kb
Host smart-fe5b7828-f659-4069-a488-d261b230157b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520383773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.1520383773
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2455772277
Short name T80
Test name
Test status
Simulation time 11051211401 ps
CPU time 967.6 seconds
Started Feb 18 01:29:51 PM PST 24
Finished Feb 18 01:46:00 PM PST 24
Peak memory 378144 kb
Host smart-8654b51f-96d7-4f7a-97a7-e6f3f1ee95bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455772277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.sram_ctrl_access_during_key_req.2455772277
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.2044012467
Short name T688
Test name
Test status
Simulation time 13805999 ps
CPU time 0.64 seconds
Started Feb 18 01:29:50 PM PST 24
Finished Feb 18 01:29:51 PM PST 24
Peak memory 202064 kb
Host smart-63646f9c-5ef6-4c3a-9ee6-a84767a6916a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044012467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.2044012467
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.3121410087
Short name T169
Test name
Test status
Simulation time 147898043393 ps
CPU time 2399.2 seconds
Started Feb 18 01:29:38 PM PST 24
Finished Feb 18 02:09:40 PM PST 24
Peak memory 202272 kb
Host smart-d226bfbd-77a5-4511-a1c2-8f8e850eb753
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121410087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.3121410087
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.156423283
Short name T671
Test name
Test status
Simulation time 103242131372 ps
CPU time 726.12 seconds
Started Feb 18 01:29:45 PM PST 24
Finished Feb 18 01:41:52 PM PST 24
Peak memory 374036 kb
Host smart-879872b0-f0b3-466d-aa5f-7ada3f738afb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156423283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl
e.156423283
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.2690788611
Short name T105
Test name
Test status
Simulation time 8932763821 ps
CPU time 78.71 seconds
Started Feb 18 01:29:46 PM PST 24
Finished Feb 18 01:31:06 PM PST 24
Peak memory 210508 kb
Host smart-21d7e772-ef34-4b2d-a501-b1cac3323615
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690788611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.2690788611
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.4270117734
Short name T585
Test name
Test status
Simulation time 1143356171 ps
CPU time 159.87 seconds
Started Feb 18 01:29:51 PM PST 24
Finished Feb 18 01:32:32 PM PST 24
Peak memory 369900 kb
Host smart-036ee3ab-d75f-4c25-ac66-5b55b3d50626
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270117734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.4270117734
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.568212329
Short name T618
Test name
Test status
Simulation time 3768281350 ps
CPU time 83.7 seconds
Started Feb 18 01:29:50 PM PST 24
Finished Feb 18 01:31:15 PM PST 24
Peak memory 210856 kb
Host smart-eb298acc-da51-4944-834d-abfd9803585e
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568212329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_mem_partial_access.568212329
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.640817506
Short name T262
Test name
Test status
Simulation time 15177592901 ps
CPU time 126.52 seconds
Started Feb 18 01:29:50 PM PST 24
Finished Feb 18 01:31:58 PM PST 24
Peak memory 202332 kb
Host smart-d371f93f-7e90-495f-b6e6-c1d133b18231
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640817506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl
_mem_walk.640817506
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.4068111536
Short name T443
Test name
Test status
Simulation time 13740478173 ps
CPU time 212.7 seconds
Started Feb 18 01:29:40 PM PST 24
Finished Feb 18 01:33:14 PM PST 24
Peak memory 320904 kb
Host smart-02a9db2a-6c0f-493f-9181-a285eb2e21f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068111536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.4068111536
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.1767907126
Short name T353
Test name
Test status
Simulation time 3779983815 ps
CPU time 136.5 seconds
Started Feb 18 01:29:46 PM PST 24
Finished Feb 18 01:32:03 PM PST 24
Peak memory 369988 kb
Host smart-786d1cf7-2f30-49d1-9d01-a7baff87b582
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767907126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
sram_ctrl_partial_access.1767907126
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1570637628
Short name T228
Test name
Test status
Simulation time 15794107346 ps
CPU time 388.07 seconds
Started Feb 18 01:29:47 PM PST 24
Finished Feb 18 01:36:16 PM PST 24
Peak memory 202248 kb
Host smart-12ea0551-2f01-4b5e-80a0-c09259ae374c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570637628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.1570637628
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.3635906517
Short name T583
Test name
Test status
Simulation time 363147575 ps
CPU time 14.05 seconds
Started Feb 18 01:29:51 PM PST 24
Finished Feb 18 01:30:06 PM PST 24
Peak memory 202452 kb
Host smart-fd4e0234-ae4d-4e69-a0f7-bc371307153f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635906517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3635906517
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.1570347643
Short name T354
Test name
Test status
Simulation time 129571069421 ps
CPU time 1174.89 seconds
Started Feb 18 01:29:46 PM PST 24
Finished Feb 18 01:49:21 PM PST 24
Peak memory 377156 kb
Host smart-b6ad4fdd-b8be-4053-951d-1ba01d4cec10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570347643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1570347643
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.3910470046
Short name T363
Test name
Test status
Simulation time 4931542134 ps
CPU time 31.16 seconds
Started Feb 18 01:29:40 PM PST 24
Finished Feb 18 01:30:13 PM PST 24
Peak memory 210344 kb
Host smart-d5153b21-77c7-490b-82e7-c94b33a77b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910470046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3910470046
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2230332646
Short name T466
Test name
Test status
Simulation time 4160961993 ps
CPU time 322.95 seconds
Started Feb 18 01:29:51 PM PST 24
Finished Feb 18 01:35:15 PM PST 24
Peak memory 202328 kb
Host smart-1d91fbfe-1b94-485b-a618-c4b81595dac6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230332646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.sram_ctrl_stress_pipeline.2230332646
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.767154002
Short name T101
Test name
Test status
Simulation time 1363023365 ps
CPU time 29.43 seconds
Started Feb 18 01:29:51 PM PST 24
Finished Feb 18 01:30:22 PM PST 24
Peak memory 222292 kb
Host smart-f1d09b13-fa71-46e3-b394-0c9c7bcd630b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767154002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_throughput_w_partial_write.767154002
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.597100349
Short name T185
Test name
Test status
Simulation time 4260759621 ps
CPU time 1058.45 seconds
Started Feb 18 01:30:07 PM PST 24
Finished Feb 18 01:47:46 PM PST 24
Peak memory 378208 kb
Host smart-731ed2f5-c862-4a87-93a1-d2701d19b55e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597100349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 37.sram_ctrl_access_during_key_req.597100349
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.901233963
Short name T23
Test name
Test status
Simulation time 37069992 ps
CPU time 0.66 seconds
Started Feb 18 01:29:56 PM PST 24
Finished Feb 18 01:29:57 PM PST 24
Peak memory 202060 kb
Host smart-4915c271-9c7c-4c19-a09f-87899788df9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901233963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.901233963
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.304485124
Short name T805
Test name
Test status
Simulation time 110636694178 ps
CPU time 1914.53 seconds
Started Feb 18 01:30:06 PM PST 24
Finished Feb 18 02:02:01 PM PST 24
Peak memory 202408 kb
Host smart-4f42b7ee-2188-42c6-a87c-1640620699c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304485124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.
304485124
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.240417452
Short name T648
Test name
Test status
Simulation time 2958524968 ps
CPU time 55.69 seconds
Started Feb 18 01:29:58 PM PST 24
Finished Feb 18 01:30:55 PM PST 24
Peak memory 228944 kb
Host smart-8da57332-0b58-4ea8-bb58-b3d35496e63b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240417452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executabl
e.240417452
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.3657399378
Short name T177
Test name
Test status
Simulation time 9522691885 ps
CPU time 179.91 seconds
Started Feb 18 01:29:56 PM PST 24
Finished Feb 18 01:32:56 PM PST 24
Peak memory 363876 kb
Host smart-3d21c1f5-019e-43d9-bb4e-8c455ed52ff2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657399378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_max_throughput.3657399378
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.4185139716
Short name T222
Test name
Test status
Simulation time 11224660477 ps
CPU time 150.79 seconds
Started Feb 18 01:30:07 PM PST 24
Finished Feb 18 01:32:38 PM PST 24
Peak memory 211344 kb
Host smart-fb0b306e-8c2a-4841-a31a-bf5c76334182
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185139716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_mem_partial_access.4185139716
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.992675018
Short name T364
Test name
Test status
Simulation time 41287978218 ps
CPU time 152.09 seconds
Started Feb 18 01:29:58 PM PST 24
Finished Feb 18 01:32:31 PM PST 24
Peak memory 202284 kb
Host smart-400dff4e-459b-4cd1-a649-b326efa56015
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992675018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl
_mem_walk.992675018
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.1647808978
Short name T8
Test name
Test status
Simulation time 6898537947 ps
CPU time 561.45 seconds
Started Feb 18 01:29:50 PM PST 24
Finished Feb 18 01:39:12 PM PST 24
Peak memory 364960 kb
Host smart-03086f4c-509a-4009-9907-452e717c3f86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647808978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.1647808978
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.3294349014
Short name T425
Test name
Test status
Simulation time 458968187 ps
CPU time 21.13 seconds
Started Feb 18 01:29:51 PM PST 24
Finished Feb 18 01:30:15 PM PST 24
Peak memory 202196 kb
Host smart-50faf5db-3b5b-4739-bc6c-6c12b8646027
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294349014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_partial_access.3294349014
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2217003908
Short name T660
Test name
Test status
Simulation time 40476250755 ps
CPU time 442.88 seconds
Started Feb 18 01:29:51 PM PST 24
Finished Feb 18 01:37:17 PM PST 24
Peak memory 210424 kb
Host smart-2c726b99-a325-43c1-8b2a-2f7c73f46027
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217003908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.2217003908
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.211112346
Short name T226
Test name
Test status
Simulation time 349936544 ps
CPU time 13.88 seconds
Started Feb 18 01:29:58 PM PST 24
Finished Feb 18 01:30:13 PM PST 24
Peak memory 202536 kb
Host smart-1add03d7-fadf-4974-bdd1-9daae6f0730c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211112346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.211112346
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.486174978
Short name T645
Test name
Test status
Simulation time 5856857724 ps
CPU time 572.25 seconds
Started Feb 18 01:29:55 PM PST 24
Finished Feb 18 01:39:28 PM PST 24
Peak memory 372004 kb
Host smart-948152e2-c46c-4c06-baf5-883454f97029
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486174978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.486174978
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.3392650317
Short name T539
Test name
Test status
Simulation time 1601008976 ps
CPU time 33.45 seconds
Started Feb 18 01:29:52 PM PST 24
Finished Feb 18 01:30:28 PM PST 24
Peak memory 261444 kb
Host smart-e749bcce-4fe7-4f6f-83ab-a7ecc254c35b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392650317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3392650317
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.1560104988
Short name T344
Test name
Test status
Simulation time 61320351319 ps
CPU time 2437.88 seconds
Started Feb 18 01:29:56 PM PST 24
Finished Feb 18 02:10:35 PM PST 24
Peak memory 374228 kb
Host smart-dd568c51-f92e-4a7e-a1ed-ad77c2d67191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560104988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.1560104988
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2897495807
Short name T769
Test name
Test status
Simulation time 5819129294 ps
CPU time 441.39 seconds
Started Feb 18 01:29:50 PM PST 24
Finished Feb 18 01:37:13 PM PST 24
Peak memory 210528 kb
Host smart-4eb07e0e-f1f8-4466-8ed1-17ea672d5ec9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897495807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.sram_ctrl_stress_pipeline.2897495807
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2111595856
Short name T216
Test name
Test status
Simulation time 1576838118 ps
CPU time 118.29 seconds
Started Feb 18 01:29:57 PM PST 24
Finished Feb 18 01:31:56 PM PST 24
Peak memory 333020 kb
Host smart-c823f7b8-b808-4d98-bea9-d33b673657eb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111595856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.2111595856
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3957897150
Short name T620
Test name
Test status
Simulation time 5681644175 ps
CPU time 762.91 seconds
Started Feb 18 01:30:17 PM PST 24
Finished Feb 18 01:43:01 PM PST 24
Peak memory 374100 kb
Host smart-21da054b-0cbf-4655-9ad2-a8bcc42484d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957897150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.3957897150
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.4088097176
Short name T314
Test name
Test status
Simulation time 19242589 ps
CPU time 0.64 seconds
Started Feb 18 01:30:14 PM PST 24
Finished Feb 18 01:30:15 PM PST 24
Peak memory 201948 kb
Host smart-0e888190-4f99-4747-ae64-974e0c6dd70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088097176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.4088097176
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.1097931835
Short name T135
Test name
Test status
Simulation time 155231718317 ps
CPU time 1313.65 seconds
Started Feb 18 01:29:57 PM PST 24
Finished Feb 18 01:51:52 PM PST 24
Peak memory 202356 kb
Host smart-e8e6f2f4-99bf-41bd-826d-fe8197809715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097931835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.1097931835
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.3068204104
Short name T693
Test name
Test status
Simulation time 763457751 ps
CPU time 107.15 seconds
Started Feb 18 01:30:09 PM PST 24
Finished Feb 18 01:31:56 PM PST 24
Peak memory 333064 kb
Host smart-37a83278-9b2f-4cf8-b7e9-e3864fdf0c91
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068204104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.3068204104
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.226022664
Short name T492
Test name
Test status
Simulation time 1004504738 ps
CPU time 69.92 seconds
Started Feb 18 01:30:17 PM PST 24
Finished Feb 18 01:31:28 PM PST 24
Peak memory 211280 kb
Host smart-1ef3f0de-acb5-4ca4-a1ef-6f73b6853b11
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226022664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_mem_partial_access.226022664
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.2595603623
Short name T646
Test name
Test status
Simulation time 26538221879 ps
CPU time 144.04 seconds
Started Feb 18 01:30:15 PM PST 24
Finished Feb 18 01:32:40 PM PST 24
Peak memory 202240 kb
Host smart-f6293e0d-d79c-4ce9-90de-ac559d6367e5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595603623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.2595603623
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.1969544646
Short name T308
Test name
Test status
Simulation time 7392269440 ps
CPU time 1088.32 seconds
Started Feb 18 01:30:00 PM PST 24
Finished Feb 18 01:48:09 PM PST 24
Peak memory 375100 kb
Host smart-0d2e9e17-720d-49a0-9654-1e18ed01e12b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969544646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.1969544646
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.3265839256
Short name T587
Test name
Test status
Simulation time 2572772108 ps
CPU time 24.87 seconds
Started Feb 18 01:30:00 PM PST 24
Finished Feb 18 01:30:25 PM PST 24
Peak memory 265784 kb
Host smart-b17c3602-2d4b-454a-be41-cdf66511575d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265839256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
sram_ctrl_partial_access.3265839256
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.388668311
Short name T763
Test name
Test status
Simulation time 71671592230 ps
CPU time 449.56 seconds
Started Feb 18 01:29:55 PM PST 24
Finished Feb 18 01:37:26 PM PST 24
Peak memory 202244 kb
Host smart-69bcb8f2-74d0-4af6-a282-e74f36a4ea48
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388668311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.sram_ctrl_partial_access_b2b.388668311
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.493515647
Short name T257
Test name
Test status
Simulation time 1410051992 ps
CPU time 6.15 seconds
Started Feb 18 01:30:15 PM PST 24
Finished Feb 18 01:30:22 PM PST 24
Peak memory 202444 kb
Host smart-8cb86248-7378-48f7-9b5b-5d3d6bd8d078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493515647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.493515647
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.633601533
Short name T118
Test name
Test status
Simulation time 14764060886 ps
CPU time 831.73 seconds
Started Feb 18 01:30:09 PM PST 24
Finished Feb 18 01:44:02 PM PST 24
Peak memory 380296 kb
Host smart-069575df-c9fe-4282-9a2b-0ed8e5fbb093
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633601533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.633601533
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.1183605365
Short name T337
Test name
Test status
Simulation time 350269498 ps
CPU time 14.23 seconds
Started Feb 18 01:30:07 PM PST 24
Finished Feb 18 01:30:22 PM PST 24
Peak memory 202208 kb
Host smart-70781a5e-a0f7-48ae-9ac5-98ad267ae274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183605365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1183605365
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.3583350167
Short name T231
Test name
Test status
Simulation time 36529846857 ps
CPU time 182.24 seconds
Started Feb 18 01:29:56 PM PST 24
Finished Feb 18 01:32:59 PM PST 24
Peak memory 202316 kb
Host smart-c01e535a-c4f7-4763-a6ae-44d3c25f915d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583350167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.3583350167
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3187425292
Short name T673
Test name
Test status
Simulation time 2692911834 ps
CPU time 39.15 seconds
Started Feb 18 01:30:07 PM PST 24
Finished Feb 18 01:30:47 PM PST 24
Peak memory 251400 kb
Host smart-d4136502-8b91-4e29-b0f4-38ae8545810f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187425292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.3187425292
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.3647283772
Short name T845
Test name
Test status
Simulation time 20574910310 ps
CPU time 509.36 seconds
Started Feb 18 01:30:16 PM PST 24
Finished Feb 18 01:38:46 PM PST 24
Peak memory 371884 kb
Host smart-f3064ca7-e217-4558-ad6b-1909de41b52a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647283772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.sram_ctrl_access_during_key_req.3647283772
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.3893762458
Short name T800
Test name
Test status
Simulation time 15409164 ps
CPU time 0.66 seconds
Started Feb 18 01:30:21 PM PST 24
Finished Feb 18 01:30:23 PM PST 24
Peak memory 201740 kb
Host smart-aa0eae07-9420-4fbf-bd1b-c0c44d097cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893762458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.3893762458
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.1725149943
Short name T521
Test name
Test status
Simulation time 20026102223 ps
CPU time 1403.93 seconds
Started Feb 18 01:30:14 PM PST 24
Finished Feb 18 01:53:39 PM PST 24
Peak memory 202440 kb
Host smart-482856ab-b2c1-4f72-8e05-482fdea29c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725149943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.1725149943
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.1050369094
Short name T120
Test name
Test status
Simulation time 45207858219 ps
CPU time 902.33 seconds
Started Feb 18 01:30:16 PM PST 24
Finished Feb 18 01:45:20 PM PST 24
Peak memory 377020 kb
Host smart-bb6cd2d5-0cf4-46fe-8b40-036b083f02ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050369094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.1050369094
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3390747310
Short name T640
Test name
Test status
Simulation time 1461835176 ps
CPU time 43.12 seconds
Started Feb 18 01:30:16 PM PST 24
Finished Feb 18 01:31:00 PM PST 24
Peak memory 268656 kb
Host smart-d8ec32ac-6dc1-4f50-83f4-b90f13440767
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390747310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3390747310
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.939124821
Short name T813
Test name
Test status
Simulation time 4713476601 ps
CPU time 151.54 seconds
Started Feb 18 01:30:21 PM PST 24
Finished Feb 18 01:32:54 PM PST 24
Peak memory 211336 kb
Host smart-9cc0e774-63e2-46e9-b15d-09730f6d809c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939124821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.sram_ctrl_mem_partial_access.939124821
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.1029714697
Short name T542
Test name
Test status
Simulation time 3951922866 ps
CPU time 126.81 seconds
Started Feb 18 01:30:24 PM PST 24
Finished Feb 18 01:32:31 PM PST 24
Peak memory 202192 kb
Host smart-d3af387a-6441-4a40-a57c-34b1f64d9bd6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029714697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.1029714697
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.2992370895
Short name T290
Test name
Test status
Simulation time 95714492721 ps
CPU time 1861.4 seconds
Started Feb 18 01:30:20 PM PST 24
Finished Feb 18 02:01:22 PM PST 24
Peak memory 378220 kb
Host smart-ec3a8284-d6d1-46ac-bf6a-d74691baf45f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992370895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.2992370895
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.137215742
Short name T816
Test name
Test status
Simulation time 7212778092 ps
CPU time 51.74 seconds
Started Feb 18 01:30:14 PM PST 24
Finished Feb 18 01:31:07 PM PST 24
Peak memory 301372 kb
Host smart-8431f632-5e6d-4148-ab1a-9a2391bce3e6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137215742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s
ram_ctrl_partial_access.137215742
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3320571638
Short name T808
Test name
Test status
Simulation time 23962412935 ps
CPU time 368.83 seconds
Started Feb 18 01:30:14 PM PST 24
Finished Feb 18 01:36:24 PM PST 24
Peak memory 202304 kb
Host smart-81f2c64b-6edc-40bc-be4c-19550dd8901f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320571638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 39.sram_ctrl_partial_access_b2b.3320571638
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.4271183310
Short name T37
Test name
Test status
Simulation time 1411600995 ps
CPU time 5.75 seconds
Started Feb 18 01:30:16 PM PST 24
Finished Feb 18 01:30:22 PM PST 24
Peak memory 202472 kb
Host smart-e215dd02-39a1-4c72-872f-077763436aa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271183310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.4271183310
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.3866234982
Short name T563
Test name
Test status
Simulation time 3377416907 ps
CPU time 299.45 seconds
Started Feb 18 01:30:14 PM PST 24
Finished Feb 18 01:35:14 PM PST 24
Peak memory 375988 kb
Host smart-de0d353e-ec25-4424-abf1-f16fcb6505a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866234982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3866234982
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.151424777
Short name T421
Test name
Test status
Simulation time 1103787993 ps
CPU time 18.51 seconds
Started Feb 18 01:30:15 PM PST 24
Finished Feb 18 01:30:34 PM PST 24
Peak memory 202132 kb
Host smart-c636a7de-39ce-43b3-87ce-b3be84821b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151424777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.151424777
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1280241390
Short name T516
Test name
Test status
Simulation time 6240850036 ps
CPU time 148.07 seconds
Started Feb 18 01:30:13 PM PST 24
Finished Feb 18 01:32:42 PM PST 24
Peak memory 202316 kb
Host smart-5a096ba8-9815-418c-af95-4f9515499f31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280241390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.1280241390
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2706131982
Short name T134
Test name
Test status
Simulation time 762665740 ps
CPU time 66.01 seconds
Started Feb 18 01:30:16 PM PST 24
Finished Feb 18 01:31:22 PM PST 24
Peak memory 287908 kb
Host smart-c69c92bf-e05c-48be-a777-71eba1e2b957
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706131982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2706131982
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2501450633
Short name T9
Test name
Test status
Simulation time 11438193992 ps
CPU time 2016.38 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:57:58 PM PST 24
Peak memory 378140 kb
Host smart-4cfd2e78-ff77-48ff-9e03-970da598e63c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501450633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.2501450633
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1094918753
Short name T761
Test name
Test status
Simulation time 18516965 ps
CPU time 0.63 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 01:24:19 PM PST 24
Peak memory 201740 kb
Host smart-937007bb-821e-4c9f-9227-e47e10e5dd59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094918753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1094918753
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.1574781923
Short name T672
Test name
Test status
Simulation time 460426134080 ps
CPU time 2589.95 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 02:07:33 PM PST 24
Peak memory 210064 kb
Host smart-168b8e2f-d13c-4b49-baa0-cfde82a780b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574781923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
1574781923
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.3376072637
Short name T25
Test name
Test status
Simulation time 1496895641 ps
CPU time 18.31 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 01:24:38 PM PST 24
Peak memory 210372 kb
Host smart-65be9f93-6e03-4acd-81c3-2e497d7c8e2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376072637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esc
alation.3376072637
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.210579549
Short name T508
Test name
Test status
Simulation time 774262001 ps
CPU time 122.04 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 01:26:25 PM PST 24
Peak memory 364764 kb
Host smart-695de5e8-97e0-4977-8229-956f175f2e54
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210579549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.sram_ctrl_max_throughput.210579549
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3085683607
Short name T229
Test name
Test status
Simulation time 10176582465 ps
CPU time 142 seconds
Started Feb 18 01:24:21 PM PST 24
Finished Feb 18 01:26:44 PM PST 24
Peak memory 218540 kb
Host smart-286712c1-3037-4118-9078-846c85c9ac97
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085683607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_mem_partial_access.3085683607
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.967715703
Short name T214
Test name
Test status
Simulation time 8382613940 ps
CPU time 248.04 seconds
Started Feb 18 01:24:27 PM PST 24
Finished Feb 18 01:28:36 PM PST 24
Peak memory 202324 kb
Host smart-6a5027ab-b05a-470d-9997-e69f80569a84
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967715703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
mem_walk.967715703
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.2196080495
Short name T784
Test name
Test status
Simulation time 1771325400 ps
CPU time 37.07 seconds
Started Feb 18 01:24:18 PM PST 24
Finished Feb 18 01:24:56 PM PST 24
Peak memory 257700 kb
Host smart-68b2da7b-9c83-41f7-ae24-3706b9ad5510
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196080495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip
le_keys.2196080495
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.2636487539
Short name T485
Test name
Test status
Simulation time 382259737 ps
CPU time 14.34 seconds
Started Feb 18 01:24:16 PM PST 24
Finished Feb 18 01:24:31 PM PST 24
Peak memory 202168 kb
Host smart-3ab57ed7-17ad-40d9-ac9e-bb0e6372fcfc
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636487539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s
ram_ctrl_partial_access.2636487539
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1372078961
Short name T256
Test name
Test status
Simulation time 9576233421 ps
CPU time 197.3 seconds
Started Feb 18 01:24:21 PM PST 24
Finished Feb 18 01:27:39 PM PST 24
Peak memory 202152 kb
Host smart-fa1432e5-0458-4b15-9ac8-e042786eefad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372078961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.1372078961
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.1531942650
Short name T286
Test name
Test status
Simulation time 2573899988 ps
CPU time 6.88 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 01:24:30 PM PST 24
Peak memory 202540 kb
Host smart-2d6bbb6e-fb93-4914-bd86-17d849379128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531942650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1531942650
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.2337814140
Short name T27
Test name
Test status
Simulation time 2793377422 ps
CPU time 347.65 seconds
Started Feb 18 01:24:20 PM PST 24
Finished Feb 18 01:30:09 PM PST 24
Peak memory 375056 kb
Host smart-e72dee11-78ee-44f9-a1ec-c02016d4fc9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337814140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.2337814140
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.52352186
Short name T18
Test name
Test status
Simulation time 416303225 ps
CPU time 3.41 seconds
Started Feb 18 01:24:16 PM PST 24
Finished Feb 18 01:24:20 PM PST 24
Peak memory 221224 kb
Host smart-e9546ca5-bfb9-40d0-aa52-5e37853bd7e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52352186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_sec_cm.52352186
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.2044226811
Short name T653
Test name
Test status
Simulation time 730219123 ps
CPU time 15.01 seconds
Started Feb 18 01:24:19 PM PST 24
Finished Feb 18 01:24:35 PM PST 24
Peak memory 202116 kb
Host smart-712a26a2-4418-4f0b-9d9b-158037f1c372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044226811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2044226811
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3080314511
Short name T367
Test name
Test status
Simulation time 3597457391 ps
CPU time 263.53 seconds
Started Feb 18 01:24:22 PM PST 24
Finished Feb 18 01:28:47 PM PST 24
Peak memory 202304 kb
Host smart-4f5cb36d-8659-4ce8-b040-3a99486e2e70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080314511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.3080314511
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1376732198
Short name T810
Test name
Test status
Simulation time 755067260 ps
CPU time 66.77 seconds
Started Feb 18 01:24:21 PM PST 24
Finished Feb 18 01:25:29 PM PST 24
Peak memory 326868 kb
Host smart-bb32ab8a-eacd-4c25-b67b-266881adaf02
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376732198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.1376732198
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.4293731884
Short name T726
Test name
Test status
Simulation time 17593033369 ps
CPU time 841.77 seconds
Started Feb 18 01:30:29 PM PST 24
Finished Feb 18 01:44:32 PM PST 24
Peak memory 369896 kb
Host smart-90a140b9-1a8f-4166-b8c6-fc20199b1592
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293731884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.4293731884
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.3427392157
Short name T533
Test name
Test status
Simulation time 31638915 ps
CPU time 0.61 seconds
Started Feb 18 01:30:33 PM PST 24
Finished Feb 18 01:30:36 PM PST 24
Peak memory 201732 kb
Host smart-a8d25d18-28f5-4d92-bbf8-e44907bad119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427392157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.3427392157
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.1137492817
Short name T413
Test name
Test status
Simulation time 169082703548 ps
CPU time 1371.39 seconds
Started Feb 18 01:30:22 PM PST 24
Finished Feb 18 01:53:14 PM PST 24
Peak memory 202360 kb
Host smart-794cea6f-e255-49f5-88c3-f2b877708670
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137492817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection
.1137492817
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.3984149778
Short name T121
Test name
Test status
Simulation time 128068877902 ps
CPU time 893.66 seconds
Started Feb 18 01:30:29 PM PST 24
Finished Feb 18 01:45:24 PM PST 24
Peak memory 374972 kb
Host smart-c2049df4-86b3-4a0e-8f2d-cb55535c60ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984149778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.3984149778
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.3065465269
Short name T582
Test name
Test status
Simulation time 6961997063 ps
CPU time 16.66 seconds
Started Feb 18 01:30:28 PM PST 24
Finished Feb 18 01:30:47 PM PST 24
Peak memory 213844 kb
Host smart-55a2ef5f-e569-4b75-9bcd-850ed4030108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065465269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.3065465269
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.283362402
Short name T133
Test name
Test status
Simulation time 2909073553 ps
CPU time 38.62 seconds
Started Feb 18 01:30:30 PM PST 24
Finished Feb 18 01:31:10 PM PST 24
Peak memory 251308 kb
Host smart-cf2c0cb3-773c-4b0e-b4f5-d14c5d001a67
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283362402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.sram_ctrl_max_throughput.283362402
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2061671137
Short name T346
Test name
Test status
Simulation time 3971570628 ps
CPU time 72.1 seconds
Started Feb 18 01:30:34 PM PST 24
Finished Feb 18 01:31:48 PM PST 24
Peak memory 211300 kb
Host smart-3cb75b78-0204-4d9a-9199-5ece478703a5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061671137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.2061671137
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.1177666514
Short name T718
Test name
Test status
Simulation time 55080402605 ps
CPU time 293.82 seconds
Started Feb 18 01:30:28 PM PST 24
Finished Feb 18 01:35:24 PM PST 24
Peak memory 202272 kb
Host smart-d0cf5a2e-564b-4279-b014-d356e615daeb
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177666514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.1177666514
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.1625482439
Short name T130
Test name
Test status
Simulation time 4824412573 ps
CPU time 420.38 seconds
Started Feb 18 01:30:22 PM PST 24
Finished Feb 18 01:37:23 PM PST 24
Peak memory 375580 kb
Host smart-4a602ad9-18a5-47a5-85d2-c65c5130746b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625482439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.1625482439
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.654588910
Short name T701
Test name
Test status
Simulation time 570526878 ps
CPU time 21.79 seconds
Started Feb 18 01:30:25 PM PST 24
Finished Feb 18 01:30:47 PM PST 24
Peak memory 255272 kb
Host smart-d80c7a17-db26-4a69-8cde-8b69f4f9daf7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654588910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s
ram_ctrl_partial_access.654588910
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3300431582
Short name T330
Test name
Test status
Simulation time 17389733632 ps
CPU time 441.64 seconds
Started Feb 18 01:30:25 PM PST 24
Finished Feb 18 01:37:47 PM PST 24
Peak memory 202224 kb
Host smart-dc85946a-a6ba-409b-a981-b8c591e0ecf6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300431582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.3300431582
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.53804709
Short name T849
Test name
Test status
Simulation time 346254411 ps
CPU time 14.59 seconds
Started Feb 18 01:30:30 PM PST 24
Finished Feb 18 01:30:46 PM PST 24
Peak memory 202436 kb
Host smart-1818f2ce-823d-4c10-a00c-9792db854ee7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53804709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf
g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.53804709
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.2583204491
Short name T785
Test name
Test status
Simulation time 139711646094 ps
CPU time 984.57 seconds
Started Feb 18 01:30:29 PM PST 24
Finished Feb 18 01:46:56 PM PST 24
Peak memory 377128 kb
Host smart-ef3ee646-b273-4714-a05e-a81878bb44c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583204491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2583204491
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.231983897
Short name T657
Test name
Test status
Simulation time 7332719246 ps
CPU time 33.49 seconds
Started Feb 18 01:30:24 PM PST 24
Finished Feb 18 01:30:58 PM PST 24
Peak memory 202352 kb
Host smart-6163baaa-6e5b-4465-94d8-e43ad68b5e80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231983897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.231983897
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3150359962
Short name T851
Test name
Test status
Simulation time 5014473980 ps
CPU time 337.31 seconds
Started Feb 18 01:30:22 PM PST 24
Finished Feb 18 01:36:00 PM PST 24
Peak memory 202268 kb
Host smart-c6740474-d875-43bb-8b96-3e0124858cfd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150359962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.3150359962
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2592432249
Short name T225
Test name
Test status
Simulation time 1447583860 ps
CPU time 33.23 seconds
Started Feb 18 01:30:28 PM PST 24
Finished Feb 18 01:31:04 PM PST 24
Peak memory 234916 kb
Host smart-e1a83354-73ec-4a78-a091-74d285e0c043
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592432249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2592432249
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1339688158
Short name T702
Test name
Test status
Simulation time 10351078262 ps
CPU time 970.36 seconds
Started Feb 18 01:30:39 PM PST 24
Finished Feb 18 01:46:50 PM PST 24
Peak memory 370992 kb
Host smart-f4942cf5-454f-409e-942f-277ec84c54bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339688158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.1339688158
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.616556780
Short name T789
Test name
Test status
Simulation time 11306439 ps
CPU time 0.65 seconds
Started Feb 18 01:30:50 PM PST 24
Finished Feb 18 01:30:52 PM PST 24
Peak memory 202048 kb
Host smart-1a68166d-19dc-4d3d-88f2-24f80e3122ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616556780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.616556780
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.3941004490
Short name T219
Test name
Test status
Simulation time 131169943735 ps
CPU time 567.9 seconds
Started Feb 18 01:30:32 PM PST 24
Finished Feb 18 01:40:02 PM PST 24
Peak memory 202348 kb
Host smart-1604e79d-b9fe-49fd-81ed-b32d6f224f43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941004490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.3941004490
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.882571923
Short name T313
Test name
Test status
Simulation time 11912080694 ps
CPU time 132.9 seconds
Started Feb 18 01:30:39 PM PST 24
Finished Feb 18 01:32:53 PM PST 24
Peak memory 210484 kb
Host smart-c2b8d963-ac46-4985-b37d-6de4b8665d80
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882571923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_esc
alation.882571923
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.3321981122
Short name T420
Test name
Test status
Simulation time 2802436363 ps
CPU time 29.74 seconds
Started Feb 18 01:30:33 PM PST 24
Finished Feb 18 01:31:04 PM PST 24
Peak memory 215508 kb
Host smart-dfabf0c1-5b37-4478-baeb-de4b922d32a9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321981122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.3321981122
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.3927376337
Short name T341
Test name
Test status
Simulation time 43720933099 ps
CPU time 150.95 seconds
Started Feb 18 01:30:39 PM PST 24
Finished Feb 18 01:33:10 PM PST 24
Peak memory 218632 kb
Host smart-345a9253-7572-43a4-8f2c-f1404b6bb5d5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927376337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.3927376337
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.422219438
Short name T284
Test name
Test status
Simulation time 7178181984 ps
CPU time 151.88 seconds
Started Feb 18 01:30:40 PM PST 24
Finished Feb 18 01:33:13 PM PST 24
Peak memory 202288 kb
Host smart-4ed34f08-70b8-4dc8-a04d-aa83bb21df4f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422219438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl
_mem_walk.422219438
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.2322226870
Short name T615
Test name
Test status
Simulation time 69250701153 ps
CPU time 1670.4 seconds
Started Feb 18 01:30:33 PM PST 24
Finished Feb 18 01:58:25 PM PST 24
Peak memory 376192 kb
Host smart-faa4ef6d-5c07-42dd-a0fa-370c9814ad64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322226870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi
ple_keys.2322226870
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.3047903522
Short name T814
Test name
Test status
Simulation time 4112409123 ps
CPU time 17.91 seconds
Started Feb 18 01:30:33 PM PST 24
Finished Feb 18 01:30:52 PM PST 24
Peak memory 202228 kb
Host smart-e302cab3-9101-4dbc-9840-796a929160ff
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047903522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.3047903522
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4273098775
Short name T740
Test name
Test status
Simulation time 41370562930 ps
CPU time 501.92 seconds
Started Feb 18 01:30:42 PM PST 24
Finished Feb 18 01:39:06 PM PST 24
Peak memory 202224 kb
Host smart-64fe316b-b6ce-4812-a7f1-c7661f6ff42e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273098775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 41.sram_ctrl_partial_access_b2b.4273098775
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.2832069475
Short name T776
Test name
Test status
Simulation time 356539450 ps
CPU time 13.31 seconds
Started Feb 18 01:30:39 PM PST 24
Finished Feb 18 01:30:53 PM PST 24
Peak memory 202472 kb
Host smart-e31b1775-204d-4f49-8528-c46b6b3f226a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832069475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2832069475
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.4005806181
Short name T723
Test name
Test status
Simulation time 741002122 ps
CPU time 14.19 seconds
Started Feb 18 01:30:42 PM PST 24
Finished Feb 18 01:30:58 PM PST 24
Peak memory 208540 kb
Host smart-8fe62e45-aa8f-4078-af51-5f956531d097
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005806181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4005806181
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3159127052
Short name T507
Test name
Test status
Simulation time 14453242218 ps
CPU time 269.21 seconds
Started Feb 18 01:30:42 PM PST 24
Finished Feb 18 01:35:13 PM PST 24
Peak memory 202304 kb
Host smart-16810f75-f763-44b8-904f-1d2e27efa681
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159127052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3159127052
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3020601940
Short name T386
Test name
Test status
Simulation time 1423134716 ps
CPU time 34.24 seconds
Started Feb 18 01:30:32 PM PST 24
Finished Feb 18 01:31:08 PM PST 24
Peak memory 239380 kb
Host smart-1f06b631-2510-47ac-9efc-4c850e8e5f55
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020601940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3020601940
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1543306407
Short name T695
Test name
Test status
Simulation time 29320585821 ps
CPU time 741.04 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:43:26 PM PST 24
Peak memory 371948 kb
Host smart-1b8ce333-ba75-4a99-8112-b978e15b5652
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543306407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.1543306407
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.103426470
Short name T292
Test name
Test status
Simulation time 124769715 ps
CPU time 0.67 seconds
Started Feb 18 01:31:06 PM PST 24
Finished Feb 18 01:31:09 PM PST 24
Peak memory 201872 kb
Host smart-b71e6375-30e4-4c1d-8e87-48a3e42facb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103426470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.103426470
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.3251253608
Short name T605
Test name
Test status
Simulation time 402672602672 ps
CPU time 1613.76 seconds
Started Feb 18 01:30:59 PM PST 24
Finished Feb 18 01:57:54 PM PST 24
Peak memory 202372 kb
Host smart-9cf40aec-3935-4c92-8a4e-648b5e4bb8a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251253608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.3251253608
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.203029019
Short name T579
Test name
Test status
Simulation time 25503876554 ps
CPU time 712.79 seconds
Started Feb 18 01:30:59 PM PST 24
Finished Feb 18 01:42:53 PM PST 24
Peak memory 370284 kb
Host smart-743c37a0-a3fa-457a-859d-49aced93f474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203029019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executabl
e.203029019
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.3205973406
Short name T4
Test name
Test status
Simulation time 37395544990 ps
CPU time 241.46 seconds
Started Feb 18 01:30:58 PM PST 24
Finished Feb 18 01:35:01 PM PST 24
Peak memory 210472 kb
Host smart-5d62a34b-b50a-4ecb-9f5f-030ab255d5e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205973406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.3205973406
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.3494310708
Short name T621
Test name
Test status
Simulation time 794818263 ps
CPU time 150.63 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:33:36 PM PST 24
Peak memory 370932 kb
Host smart-d4ed36a1-6d17-4640-a26f-f0dd277e658e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494310708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.3494310708
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2198795132
Short name T358
Test name
Test status
Simulation time 1655678605 ps
CPU time 132.32 seconds
Started Feb 18 01:30:59 PM PST 24
Finished Feb 18 01:33:12 PM PST 24
Peak memory 214152 kb
Host smart-15d9b1f7-e1e7-4605-8d6f-7ab783cd0e1b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198795132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.2198795132
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.1837106779
Short name T261
Test name
Test status
Simulation time 1999542243 ps
CPU time 120.51 seconds
Started Feb 18 01:30:58 PM PST 24
Finished Feb 18 01:33:00 PM PST 24
Peak memory 202104 kb
Host smart-4c6f687f-73f9-40b5-8037-e7903b98d5a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837106779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr
l_mem_walk.1837106779
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.2636617167
Short name T418
Test name
Test status
Simulation time 39049039402 ps
CPU time 283.96 seconds
Started Feb 18 01:30:56 PM PST 24
Finished Feb 18 01:35:40 PM PST 24
Peak memory 377092 kb
Host smart-50c4c658-6a8c-40ca-ad68-eb86d5057ec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636617167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.2636617167
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.2548111397
Short name T171
Test name
Test status
Simulation time 4578476486 ps
CPU time 133.68 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:33:19 PM PST 24
Peak memory 363716 kb
Host smart-611cdd63-80f1-4776-b45b-5d14920fbe41
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548111397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
sram_ctrl_partial_access.2548111397
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3619691317
Short name T622
Test name
Test status
Simulation time 23694324943 ps
CPU time 144.8 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:33:30 PM PST 24
Peak memory 202212 kb
Host smart-67b04f0a-b08c-4732-995c-9170de4ac739
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619691317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.3619691317
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.2283642233
Short name T357
Test name
Test status
Simulation time 1366305808 ps
CPU time 5.68 seconds
Started Feb 18 01:30:59 PM PST 24
Finished Feb 18 01:31:06 PM PST 24
Peak memory 202376 kb
Host smart-1b4ce329-53e8-4091-a3aa-7de7dd5d801d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283642233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2283642233
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.4221533282
Short name T559
Test name
Test status
Simulation time 25990580240 ps
CPU time 517.71 seconds
Started Feb 18 01:30:58 PM PST 24
Finished Feb 18 01:39:37 PM PST 24
Peak memory 379292 kb
Host smart-ad7da2ff-9185-48e0-8a3f-c312ccf380e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221533282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.4221533282
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.3852690841
Short name T167
Test name
Test status
Simulation time 387958402 ps
CPU time 16 seconds
Started Feb 18 01:30:58 PM PST 24
Finished Feb 18 01:31:16 PM PST 24
Peak memory 202212 kb
Host smart-134fa742-035b-4a33-9008-efdff6bd8d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852690841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3852690841
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.333750546
Short name T613
Test name
Test status
Simulation time 113542426182 ps
CPU time 4763.72 seconds
Started Feb 18 01:31:03 PM PST 24
Finished Feb 18 02:50:29 PM PST 24
Peak memory 380204 kb
Host smart-3a0b7294-e3a9-4f61-90eb-d3bb54f812d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333750546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_stress_all.333750546
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2546431658
Short name T589
Test name
Test status
Simulation time 23965593717 ps
CPU time 461.67 seconds
Started Feb 18 01:30:58 PM PST 24
Finished Feb 18 01:38:41 PM PST 24
Peak memory 202348 kb
Host smart-69bbb44a-a562-4aad-bd4f-d725ac9b6bc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546431658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.2546431658
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.2819670307
Short name T728
Test name
Test status
Simulation time 740673727 ps
CPU time 80.96 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:32:26 PM PST 24
Peak memory 303372 kb
Host smart-24b95460-5046-449c-9e49-60659eff8747
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819670307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.2819670307
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2835464245
Short name T235
Test name
Test status
Simulation time 1289614976 ps
CPU time 184.45 seconds
Started Feb 18 01:31:07 PM PST 24
Finished Feb 18 01:34:13 PM PST 24
Peak memory 314192 kb
Host smart-edc6a6f3-83a5-4a0e-b4ec-15690ca1301a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835464245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.2835464245
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.1388742398
Short name T404
Test name
Test status
Simulation time 44810960 ps
CPU time 0.65 seconds
Started Feb 18 01:31:10 PM PST 24
Finished Feb 18 01:31:11 PM PST 24
Peak memory 202096 kb
Host smart-931ff7d0-9826-4b8b-b813-05b4bd25c4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388742398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.1388742398
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.271638070
Short name T806
Test name
Test status
Simulation time 111406186189 ps
CPU time 657.53 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:42:03 PM PST 24
Peak memory 210488 kb
Host smart-22c4d3cc-d8a7-49a8-a4d4-263c5510423f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271638070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.
271638070
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.1143219581
Short name T202
Test name
Test status
Simulation time 12179756090 ps
CPU time 126.07 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:33:11 PM PST 24
Peak memory 210452 kb
Host smart-137d743a-9c4b-44ee-9f1c-0eeb3d36b4c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143219581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.1143219581
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.3882280480
Short name T523
Test name
Test status
Simulation time 3208203338 ps
CPU time 108.37 seconds
Started Feb 18 01:31:05 PM PST 24
Finished Feb 18 01:32:54 PM PST 24
Peak memory 373224 kb
Host smart-02497725-2a2e-409d-a133-a5c9e3787674
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882280480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.3882280480
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.29996644
Short name T801
Test name
Test status
Simulation time 30052357985 ps
CPU time 158.18 seconds
Started Feb 18 01:31:03 PM PST 24
Finished Feb 18 01:33:42 PM PST 24
Peak memory 211332 kb
Host smart-5bf509bf-91c8-4c01-a815-47084f212f10
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_mem_partial_access.29996644
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.1446226032
Short name T138
Test name
Test status
Simulation time 9344260138 ps
CPU time 159.11 seconds
Started Feb 18 01:31:07 PM PST 24
Finished Feb 18 01:33:48 PM PST 24
Peak memory 202284 kb
Host smart-857c4d15-4b9d-4b9f-9557-080e83ce3df1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446226032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr
l_mem_walk.1446226032
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.3408839192
Short name T760
Test name
Test status
Simulation time 5598410134 ps
CPU time 702.43 seconds
Started Feb 18 01:31:05 PM PST 24
Finished Feb 18 01:42:49 PM PST 24
Peak memory 378252 kb
Host smart-c2b57e53-4bd8-45c3-94ce-ffdb775d2ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408839192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi
ple_keys.3408839192
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.3165728621
Short name T684
Test name
Test status
Simulation time 1699609206 ps
CPU time 80.83 seconds
Started Feb 18 01:31:05 PM PST 24
Finished Feb 18 01:32:27 PM PST 24
Peak memory 331132 kb
Host smart-d7520ddb-b292-4aea-83dc-2b9d01e13ac7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165728621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.3165728621
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.287450086
Short name T304
Test name
Test status
Simulation time 6033599182 ps
CPU time 383.28 seconds
Started Feb 18 01:31:06 PM PST 24
Finished Feb 18 01:37:31 PM PST 24
Peak memory 202304 kb
Host smart-ad327318-d6b6-476f-be1d-8c8826c6438c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287450086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.sram_ctrl_partial_access_b2b.287450086
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.344604736
Short name T518
Test name
Test status
Simulation time 1345628196 ps
CPU time 6.5 seconds
Started Feb 18 01:31:06 PM PST 24
Finished Feb 18 01:31:14 PM PST 24
Peak memory 202432 kb
Host smart-b4d772c9-c603-4769-9e99-8cae3bcedb50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344604736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.344604736
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3533806014
Short name T458
Test name
Test status
Simulation time 35467286516 ps
CPU time 521.25 seconds
Started Feb 18 01:31:06 PM PST 24
Finished Feb 18 01:39:48 PM PST 24
Peak memory 362860 kb
Host smart-9b4eaeb0-fa7f-4fbb-841b-0b132a758e01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533806014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3533806014
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.929825428
Short name T546
Test name
Test status
Simulation time 1828343110 ps
CPU time 42.06 seconds
Started Feb 18 01:31:04 PM PST 24
Finished Feb 18 01:31:47 PM PST 24
Peak memory 202208 kb
Host smart-031480b1-f86f-4b85-9e48-b6f7a8dd95a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929825428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.929825428
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1477390396
Short name T832
Test name
Test status
Simulation time 3730000069 ps
CPU time 245.8 seconds
Started Feb 18 01:31:05 PM PST 24
Finished Feb 18 01:35:12 PM PST 24
Peak memory 202300 kb
Host smart-c0ad0031-2416-433f-9ba1-be5cfa485e46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477390396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1477390396
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3161823936
Short name T707
Test name
Test status
Simulation time 3876480294 ps
CPU time 140.5 seconds
Started Feb 18 01:31:06 PM PST 24
Finished Feb 18 01:33:28 PM PST 24
Peak memory 359548 kb
Host smart-7dac1ccf-1a87-43e2-a90d-46f79837b6c0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161823936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.3161823936
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1877615370
Short name T435
Test name
Test status
Simulation time 42978638940 ps
CPU time 1775.88 seconds
Started Feb 18 01:31:18 PM PST 24
Finished Feb 18 02:00:54 PM PST 24
Peak memory 375100 kb
Host smart-a73f2249-c771-4360-868b-67bd64364dad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877615370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.sram_ctrl_access_during_key_req.1877615370
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.2950419450
Short name T777
Test name
Test status
Simulation time 38764139 ps
CPU time 0.72 seconds
Started Feb 18 01:31:23 PM PST 24
Finished Feb 18 01:31:24 PM PST 24
Peak memory 201724 kb
Host smart-de348b5c-fe71-4daa-9cca-3eca7eff15b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950419450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.2950419450
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.1685420927
Short name T238
Test name
Test status
Simulation time 94267986192 ps
CPU time 1035.85 seconds
Started Feb 18 01:31:12 PM PST 24
Finished Feb 18 01:48:28 PM PST 24
Peak memory 202296 kb
Host smart-7e4d46d8-eabd-43c3-8021-5d738569746b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685420927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.1685420927
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.3320253879
Short name T567
Test name
Test status
Simulation time 1156719022 ps
CPU time 20.86 seconds
Started Feb 18 01:31:18 PM PST 24
Finished Feb 18 01:31:40 PM PST 24
Peak memory 210332 kb
Host smart-1902b8fb-2339-4a92-b052-644272fd1691
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320253879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.3320253879
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.1508091065
Short name T606
Test name
Test status
Simulation time 1534813804 ps
CPU time 179.2 seconds
Started Feb 18 01:31:09 PM PST 24
Finished Feb 18 01:34:09 PM PST 24
Peak memory 369840 kb
Host smart-f75ebd45-0ab7-4e2d-a69f-495955402f8f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508091065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.1508091065
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1358122651
Short name T12
Test name
Test status
Simulation time 8361321659 ps
CPU time 79.52 seconds
Started Feb 18 01:31:23 PM PST 24
Finished Feb 18 01:32:43 PM PST 24
Peak memory 211364 kb
Host smart-be40274a-d3de-4800-94f7-c75ebbd7e737
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358122651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1358122651
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.3883290897
Short name T649
Test name
Test status
Simulation time 4022370429 ps
CPU time 250.28 seconds
Started Feb 18 01:31:16 PM PST 24
Finished Feb 18 01:35:26 PM PST 24
Peak memory 202244 kb
Host smart-885b0850-2510-4d4e-a8a9-724b90482645
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883290897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.3883290897
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.1480868554
Short name T824
Test name
Test status
Simulation time 6654109946 ps
CPU time 130.02 seconds
Started Feb 18 01:31:09 PM PST 24
Finished Feb 18 01:33:21 PM PST 24
Peak memory 337216 kb
Host smart-54bc5a32-66d0-49a6-9e2f-f9df142cbcbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480868554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.1480868554
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.3379594928
Short name T376
Test name
Test status
Simulation time 385483203 ps
CPU time 17.83 seconds
Started Feb 18 01:31:11 PM PST 24
Finished Feb 18 01:31:30 PM PST 24
Peak memory 220776 kb
Host smart-66ee7bf6-6c89-4937-bb08-e01c9358e491
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379594928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.3379594928
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1900956153
Short name T833
Test name
Test status
Simulation time 10116715269 ps
CPU time 281.17 seconds
Started Feb 18 01:31:11 PM PST 24
Finished Feb 18 01:35:53 PM PST 24
Peak memory 210400 kb
Host smart-27cbe996-3ac7-4ba3-b269-758b56158c2f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900956153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.1900956153
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.1267301265
Short name T636
Test name
Test status
Simulation time 367519669 ps
CPU time 6.24 seconds
Started Feb 18 01:31:17 PM PST 24
Finished Feb 18 01:31:23 PM PST 24
Peak memory 202440 kb
Host smart-b759da33-a2c6-486c-a6c6-6dc9ed2657d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267301265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1267301265
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.2840200729
Short name T826
Test name
Test status
Simulation time 18370681711 ps
CPU time 988.7 seconds
Started Feb 18 01:31:19 PM PST 24
Finished Feb 18 01:47:49 PM PST 24
Peak memory 379232 kb
Host smart-296bfa11-3ce5-49a7-855d-6ff86f617aa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840200729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2840200729
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.3532701045
Short name T572
Test name
Test status
Simulation time 2017370045 ps
CPU time 10.34 seconds
Started Feb 18 01:31:11 PM PST 24
Finished Feb 18 01:31:22 PM PST 24
Peak memory 202120 kb
Host smart-25cd80c7-825d-402f-bfd4-6ef36118bb59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532701045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3532701045
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.3494535514
Short name T295
Test name
Test status
Simulation time 1317793546431 ps
CPU time 5945.37 seconds
Started Feb 18 01:31:22 PM PST 24
Finished Feb 18 03:10:29 PM PST 24
Peak memory 276964 kb
Host smart-6551de49-8f81-427b-86df-2939e14ea402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494535514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.3494535514
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3981982802
Short name T479
Test name
Test status
Simulation time 12184870707 ps
CPU time 205.95 seconds
Started Feb 18 01:31:09 PM PST 24
Finished Feb 18 01:34:36 PM PST 24
Peak memory 202312 kb
Host smart-d48aa988-61e2-49be-b032-b4579e551681
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981982802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.3981982802
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3697400206
Short name T302
Test name
Test status
Simulation time 3092379788 ps
CPU time 84.55 seconds
Started Feb 18 01:31:08 PM PST 24
Finished Feb 18 01:32:34 PM PST 24
Peak memory 309180 kb
Host smart-74f3c275-83be-4396-989d-cb49e7be1629
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697400206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.3697400206
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.108814713
Short name T668
Test name
Test status
Simulation time 6542440759 ps
CPU time 1392.32 seconds
Started Feb 18 01:31:37 PM PST 24
Finished Feb 18 01:54:50 PM PST 24
Peak memory 374128 kb
Host smart-f7e06ef7-ffbf-43fa-a700-307d6a71a373
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108814713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.sram_ctrl_access_during_key_req.108814713
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2140409947
Short name T581
Test name
Test status
Simulation time 30008813 ps
CPU time 0.66 seconds
Started Feb 18 01:31:33 PM PST 24
Finished Feb 18 01:31:35 PM PST 24
Peak memory 202044 kb
Host smart-cfc3632f-7cda-4a34-a877-6e6a0f3b4cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140409947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2140409947
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.2022139065
Short name T296
Test name
Test status
Simulation time 40991592881 ps
CPU time 1073.08 seconds
Started Feb 18 01:31:24 PM PST 24
Finished Feb 18 01:49:17 PM PST 24
Peak memory 202480 kb
Host smart-4629aab3-e0f8-424a-bf36-95cb8e63ec35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022139065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection
.2022139065
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1822757074
Short name T852
Test name
Test status
Simulation time 3648807008 ps
CPU time 96.13 seconds
Started Feb 18 01:31:21 PM PST 24
Finished Feb 18 01:32:57 PM PST 24
Peak memory 367220 kb
Host smart-e47129f2-5307-4371-b32e-fe5e00ef322f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822757074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1822757074
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.420903574
Short name T233
Test name
Test status
Simulation time 5145768593 ps
CPU time 156.31 seconds
Started Feb 18 01:31:30 PM PST 24
Finished Feb 18 01:34:07 PM PST 24
Peak memory 211324 kb
Host smart-9e885edd-9a78-478d-a49c-c84737ecb67c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420903574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.sram_ctrl_mem_partial_access.420903574
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.1241795718
Short name T243
Test name
Test status
Simulation time 27593761930 ps
CPU time 144.6 seconds
Started Feb 18 01:31:29 PM PST 24
Finished Feb 18 01:33:55 PM PST 24
Peak memory 202676 kb
Host smart-feb342cb-b7bf-4f4a-be0d-1cda00d8a14f
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241795718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr
l_mem_walk.1241795718
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.2049978964
Short name T790
Test name
Test status
Simulation time 12239285518 ps
CPU time 676.1 seconds
Started Feb 18 01:31:24 PM PST 24
Finished Feb 18 01:42:41 PM PST 24
Peak memory 378224 kb
Host smart-bac6b943-bbd8-4ed7-8d47-bed655c0ac7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049978964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.2049978964
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.15870227
Short name T602
Test name
Test status
Simulation time 1431870136 ps
CPU time 23.86 seconds
Started Feb 18 01:31:21 PM PST 24
Finished Feb 18 01:31:46 PM PST 24
Peak memory 202112 kb
Host smart-d6293e1c-ff9d-420f-95e4-4b4f5e6f6599
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sr
am_ctrl_partial_access.15870227
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.3978115249
Short name T188
Test name
Test status
Simulation time 1349077362 ps
CPU time 5.89 seconds
Started Feb 18 01:31:31 PM PST 24
Finished Feb 18 01:31:38 PM PST 24
Peak memory 202464 kb
Host smart-3c394308-5afc-420b-b005-07e25f61e393
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978115249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3978115249
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.212592070
Short name T448
Test name
Test status
Simulation time 35246655843 ps
CPU time 773.7 seconds
Started Feb 18 01:31:31 PM PST 24
Finished Feb 18 01:44:26 PM PST 24
Peak memory 376068 kb
Host smart-72ea20c6-0ed1-4ec6-9e15-dce5fa9ca33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212592070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.212592070
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.2423247898
Short name T817
Test name
Test status
Simulation time 6934518473 ps
CPU time 15.13 seconds
Started Feb 18 01:31:22 PM PST 24
Finished Feb 18 01:31:38 PM PST 24
Peak memory 202248 kb
Host smart-fa315a9d-90ab-4048-b9a2-3bf28a291374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423247898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.2423247898
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.162295134
Short name T783
Test name
Test status
Simulation time 1122417112606 ps
CPU time 6186.82 seconds
Started Feb 18 01:31:30 PM PST 24
Finished Feb 18 03:14:39 PM PST 24
Peak memory 380148 kb
Host smart-d6d86266-2862-431d-b464-00dca220710c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162295134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_stress_all.162295134
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1023412595
Short name T345
Test name
Test status
Simulation time 4623889408 ps
CPU time 358.11 seconds
Started Feb 18 01:31:26 PM PST 24
Finished Feb 18 01:37:24 PM PST 24
Peak memory 202324 kb
Host smart-b214a6a7-0e49-4190-9d63-d96a1d46ac07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023412595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.1023412595
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2663568282
Short name T433
Test name
Test status
Simulation time 5722756338 ps
CPU time 91.34 seconds
Started Feb 18 01:31:23 PM PST 24
Finished Feb 18 01:32:55 PM PST 24
Peak memory 316740 kb
Host smart-d4436234-d8d6-40d4-b6a1-1af980f08657
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663568282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.2663568282
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2603780422
Short name T426
Test name
Test status
Simulation time 15474131414 ps
CPU time 869.98 seconds
Started Feb 18 01:31:44 PM PST 24
Finished Feb 18 01:46:15 PM PST 24
Peak memory 362472 kb
Host smart-b97b100a-bf50-4223-94c0-5d7191031b12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603780422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.2603780422
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.3513594973
Short name T652
Test name
Test status
Simulation time 32018094 ps
CPU time 0.64 seconds
Started Feb 18 01:31:50 PM PST 24
Finished Feb 18 01:31:51 PM PST 24
Peak memory 201744 kb
Host smart-969caff5-beb9-4fe8-ab47-811a48692a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513594973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.3513594973
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.3698413717
Short name T279
Test name
Test status
Simulation time 85265910567 ps
CPU time 1520.36 seconds
Started Feb 18 01:31:31 PM PST 24
Finished Feb 18 01:56:53 PM PST 24
Peak memory 202316 kb
Host smart-9ce61839-4fec-4a8c-9198-00701a52e41b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698413717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.3698413717
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.2708004450
Short name T738
Test name
Test status
Simulation time 53780801019 ps
CPU time 1049.73 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:49:19 PM PST 24
Peak memory 377172 kb
Host smart-42cff7e0-7117-43c2-bda9-1b68b5075f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708004450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab
le.2708004450
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.2335689472
Short name T462
Test name
Test status
Simulation time 52891273904 ps
CPU time 150.61 seconds
Started Feb 18 01:31:50 PM PST 24
Finished Feb 18 01:34:21 PM PST 24
Peak memory 210456 kb
Host smart-5e88f1bc-c14e-4edc-bf18-332af881c7d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335689472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.2335689472
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.3506927667
Short name T151
Test name
Test status
Simulation time 806541813 ps
CPU time 43.05 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:32:33 PM PST 24
Peak memory 267632 kb
Host smart-21c2e881-b508-48ae-b453-bb6fe60b50c9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506927667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.sram_ctrl_max_throughput.3506927667
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1191969157
Short name T265
Test name
Test status
Simulation time 6335441517 ps
CPU time 71.09 seconds
Started Feb 18 01:31:50 PM PST 24
Finished Feb 18 01:33:02 PM PST 24
Peak memory 211364 kb
Host smart-dda1f929-e4ad-41dc-bce5-bd546fedf716
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191969157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_mem_partial_access.1191969157
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.488666248
Short name T129
Test name
Test status
Simulation time 18388498342 ps
CPU time 274.67 seconds
Started Feb 18 01:31:53 PM PST 24
Finished Feb 18 01:36:29 PM PST 24
Peak memory 202380 kb
Host smart-f4a33418-c305-4d07-bdcf-6ef1d4c2f404
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488666248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_mem_walk.488666248
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.1853079173
Short name T282
Test name
Test status
Simulation time 8286122212 ps
CPU time 348.23 seconds
Started Feb 18 01:31:31 PM PST 24
Finished Feb 18 01:37:21 PM PST 24
Peak memory 378348 kb
Host smart-ac007a89-ae18-4aa0-a96e-e8af3f1e474c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853079173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.1853079173
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.2286199446
Short name T670
Test name
Test status
Simulation time 3252597175 ps
CPU time 56.58 seconds
Started Feb 18 01:31:48 PM PST 24
Finished Feb 18 01:32:46 PM PST 24
Peak memory 306532 kb
Host smart-c5f18b40-14a6-49b1-b978-5fbab86c578c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286199446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.2286199446
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1399960010
Short name T89
Test name
Test status
Simulation time 9555267118 ps
CPU time 199.09 seconds
Started Feb 18 01:31:50 PM PST 24
Finished Feb 18 01:35:10 PM PST 24
Peak memory 202164 kb
Host smart-53eb8eaa-d6b2-4229-bb30-eca426147e4f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399960010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.1399960010
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.2631506687
Short name T398
Test name
Test status
Simulation time 361511840 ps
CPU time 6.37 seconds
Started Feb 18 01:31:50 PM PST 24
Finished Feb 18 01:31:57 PM PST 24
Peak memory 202432 kb
Host smart-20f50888-dae3-420b-b027-71f6b7ea9d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631506687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2631506687
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.2555657604
Short name T309
Test name
Test status
Simulation time 44126904053 ps
CPU time 541.84 seconds
Started Feb 18 01:31:47 PM PST 24
Finished Feb 18 01:40:49 PM PST 24
Peak memory 373040 kb
Host smart-2d36a564-9a6d-4d01-90e1-7e5ae36977a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555657604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2555657604
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.1473156673
Short name T360
Test name
Test status
Simulation time 533754551 ps
CPU time 27.85 seconds
Started Feb 18 01:31:32 PM PST 24
Finished Feb 18 01:32:01 PM PST 24
Peak memory 202196 kb
Host smart-5f8ed79e-fdae-49e4-a9a7-59f094d13304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473156673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1473156673
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.3461578358
Short name T584
Test name
Test status
Simulation time 20985805122 ps
CPU time 350.48 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:37:41 PM PST 24
Peak memory 202312 kb
Host smart-0ef31d81-7628-4cd8-aa40-d7888bff6cd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461578358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.3461578358
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2055262045
Short name T166
Test name
Test status
Simulation time 3860908117 ps
CPU time 70.25 seconds
Started Feb 18 01:31:48 PM PST 24
Finished Feb 18 01:32:59 PM PST 24
Peak memory 300460 kb
Host smart-38233ae8-7181-43e0-aff4-c6c93e6fa09c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055262045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2055262045
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3056754404
Short name T775
Test name
Test status
Simulation time 20432200727 ps
CPU time 669.57 seconds
Started Feb 18 01:31:48 PM PST 24
Finished Feb 18 01:42:59 PM PST 24
Peak memory 377116 kb
Host smart-83436b9d-8077-4237-a627-9c2878e238ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056754404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.3056754404
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.3251475522
Short name T234
Test name
Test status
Simulation time 46019705 ps
CPU time 0.65 seconds
Started Feb 18 01:31:51 PM PST 24
Finished Feb 18 01:31:52 PM PST 24
Peak memory 202060 kb
Host smart-2a09b42a-e8c2-4c55-a7c2-75e28343f496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251475522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.3251475522
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.753442462
Short name T482
Test name
Test status
Simulation time 53684417328 ps
CPU time 1997.46 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 02:05:07 PM PST 24
Peak memory 202404 kb
Host smart-572e2dbb-44b6-4365-9f67-d1bffbc3c941
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753442462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.
753442462
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.1584284871
Short name T281
Test name
Test status
Simulation time 25116506844 ps
CPU time 1089.84 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:50:00 PM PST 24
Peak memory 378084 kb
Host smart-b059f02d-01f0-4cd7-9381-9279c89d7c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584284871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.1584284871
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.450751187
Short name T509
Test name
Test status
Simulation time 783145734 ps
CPU time 107.75 seconds
Started Feb 18 01:31:50 PM PST 24
Finished Feb 18 01:33:38 PM PST 24
Peak memory 330888 kb
Host smart-bded8b14-74f0-449f-8c7f-0a81dbac0eb4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450751187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sram_ctrl_max_throughput.450751187
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3781223958
Short name T811
Test name
Test status
Simulation time 1047919449 ps
CPU time 78.09 seconds
Started Feb 18 01:31:53 PM PST 24
Finished Feb 18 01:33:12 PM PST 24
Peak memory 211280 kb
Host smart-1f324424-c0f4-442c-b92d-aa9ca92d4d67
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781223958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.3781223958
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.3022188777
Short name T565
Test name
Test status
Simulation time 3959950915 ps
CPU time 252.03 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:36:01 PM PST 24
Peak memory 202184 kb
Host smart-e4be71d7-d3c0-4732-b386-1810092e71c3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022188777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.3022188777
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.1417511001
Short name T474
Test name
Test status
Simulation time 5882492510 ps
CPU time 917.95 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:47:08 PM PST 24
Peak memory 376140 kb
Host smart-6dc447d0-647b-40cf-86a9-6d969f6ddfd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417511001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi
ple_keys.1417511001
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.617971819
Short name T409
Test name
Test status
Simulation time 1464392575 ps
CPU time 27.87 seconds
Started Feb 18 01:31:53 PM PST 24
Finished Feb 18 01:32:21 PM PST 24
Peak memory 202092 kb
Host smart-a9073cd6-24ea-45f5-aa6e-a45ef9595d50
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617971819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.s
ram_ctrl_partial_access.617971819
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.689579175
Short name T694
Test name
Test status
Simulation time 25416163825 ps
CPU time 308.39 seconds
Started Feb 18 01:31:51 PM PST 24
Finished Feb 18 01:37:00 PM PST 24
Peak memory 202252 kb
Host smart-171a975d-4fbb-4686-af01-6a8a8c55d95a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689579175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.sram_ctrl_partial_access_b2b.689579175
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.245432693
Short name T549
Test name
Test status
Simulation time 669981386 ps
CPU time 13.69 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:32:03 PM PST 24
Peak memory 202500 kb
Host smart-81390932-ca12-454f-b6df-f4000b39f898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245432693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.245432693
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.3865179221
Short name T128
Test name
Test status
Simulation time 11898645719 ps
CPU time 1194.79 seconds
Started Feb 18 01:31:50 PM PST 24
Finished Feb 18 01:51:46 PM PST 24
Peak memory 379228 kb
Host smart-daf901d9-3a8d-4fc5-901f-70e82dc8d13c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865179221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3865179221
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.693333653
Short name T45
Test name
Test status
Simulation time 4621624098 ps
CPU time 22.35 seconds
Started Feb 18 01:31:48 PM PST 24
Finished Feb 18 01:32:12 PM PST 24
Peak memory 202288 kb
Host smart-5316b249-2efc-41d2-8049-39526961b89a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693333653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.693333653
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.3402600974
Short name T44
Test name
Test status
Simulation time 100335376396 ps
CPU time 3187.98 seconds
Started Feb 18 01:31:51 PM PST 24
Finished Feb 18 02:24:59 PM PST 24
Peak memory 381224 kb
Host smart-e65773b6-bf18-47c3-8e0a-6ffc9f81e92c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402600974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.3402600974
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1458504363
Short name T428
Test name
Test status
Simulation time 22846268362 ps
CPU time 201.31 seconds
Started Feb 18 01:31:49 PM PST 24
Finished Feb 18 01:35:11 PM PST 24
Peak memory 202216 kb
Host smart-c8b59bf2-39f8-4600-b2cb-d6ae1721e22e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458504363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.1458504363
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1366565170
Short name T370
Test name
Test status
Simulation time 794472787 ps
CPU time 94.63 seconds
Started Feb 18 01:31:44 PM PST 24
Finished Feb 18 01:33:19 PM PST 24
Peak memory 335748 kb
Host smart-2f929a66-83c7-4022-a319-01c7d0b688f0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366565170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1366565170
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2536963252
Short name T79
Test name
Test status
Simulation time 25998481429 ps
CPU time 1322.72 seconds
Started Feb 18 01:31:59 PM PST 24
Finished Feb 18 01:54:04 PM PST 24
Peak memory 373028 kb
Host smart-ba397299-b7c3-45c7-a52f-b7fe04daec55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536963252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.2536963252
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.3499706325
Short name T24
Test name
Test status
Simulation time 30684605 ps
CPU time 0.68 seconds
Started Feb 18 01:32:07 PM PST 24
Finished Feb 18 01:32:08 PM PST 24
Peak memory 202080 kb
Host smart-00630a3c-5540-43c4-bd54-ad6e391bb271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499706325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.3499706325
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.3284833539
Short name T842
Test name
Test status
Simulation time 51272268077 ps
CPU time 587.59 seconds
Started Feb 18 01:31:51 PM PST 24
Finished Feb 18 01:41:39 PM PST 24
Peak memory 202396 kb
Host smart-b5ca3d26-e9fc-4658-99f2-a77670453d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284833539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection
.3284833539
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.141556001
Short name T574
Test name
Test status
Simulation time 30386079285 ps
CPU time 1369.16 seconds
Started Feb 18 01:31:58 PM PST 24
Finished Feb 18 01:54:48 PM PST 24
Peak memory 373068 kb
Host smart-435fd238-057e-4eaa-9071-7a9a275e23c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141556001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl
e.141556001
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.1424395780
Short name T28
Test name
Test status
Simulation time 12654637148 ps
CPU time 68.23 seconds
Started Feb 18 01:32:01 PM PST 24
Finished Feb 18 01:33:12 PM PST 24
Peak memory 210476 kb
Host smart-4ed8291a-4ac0-400d-bf11-667936c528b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424395780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.1424395780
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.2212041039
Short name T522
Test name
Test status
Simulation time 712196391 ps
CPU time 37.35 seconds
Started Feb 18 01:31:53 PM PST 24
Finished Feb 18 01:32:31 PM PST 24
Peak memory 251304 kb
Host smart-35a26532-2483-4890-83d7-a4caed418356
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212041039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.sram_ctrl_max_throughput.2212041039
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3453902248
Short name T550
Test name
Test status
Simulation time 11162949576 ps
CPU time 145.2 seconds
Started Feb 18 01:32:01 PM PST 24
Finished Feb 18 01:34:28 PM PST 24
Peak memory 211304 kb
Host smart-8f68b3e6-dd56-4f7c-a714-309dc88f2e96
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453902248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_mem_partial_access.3453902248
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.1351281516
Short name T515
Test name
Test status
Simulation time 8043674429 ps
CPU time 260.93 seconds
Started Feb 18 01:32:01 PM PST 24
Finished Feb 18 01:36:24 PM PST 24
Peak memory 202356 kb
Host smart-e1ad9d92-c659-46c9-a3ec-0dc6b03e8b2a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351281516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.1351281516
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.2874505898
Short name T525
Test name
Test status
Simulation time 13762871202 ps
CPU time 1202.22 seconds
Started Feb 18 01:31:52 PM PST 24
Finished Feb 18 01:51:55 PM PST 24
Peak memory 376680 kb
Host smart-39665917-5683-46af-8010-d348d0b9adb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874505898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.2874505898
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.788465136
Short name T460
Test name
Test status
Simulation time 1761802728 ps
CPU time 7.73 seconds
Started Feb 18 01:31:53 PM PST 24
Finished Feb 18 01:32:01 PM PST 24
Peak memory 202120 kb
Host smart-94d3c9d0-116d-4ed9-b3d5-ec4b80fc2572
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788465136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.s
ram_ctrl_partial_access.788465136
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3394536549
Short name T638
Test name
Test status
Simulation time 140540741184 ps
CPU time 353.81 seconds
Started Feb 18 01:31:51 PM PST 24
Finished Feb 18 01:37:46 PM PST 24
Peak memory 202224 kb
Host smart-aaee203f-44c6-4ace-b841-a0e57601ddf4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394536549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.3394536549
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.2847250869
Short name T592
Test name
Test status
Simulation time 569156263 ps
CPU time 5.41 seconds
Started Feb 18 01:32:01 PM PST 24
Finished Feb 18 01:32:10 PM PST 24
Peak memory 202428 kb
Host smart-954723ce-e9a3-4a96-984e-1dec05766db7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847250869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2847250869
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.1237674102
Short name T839
Test name
Test status
Simulation time 5821250076 ps
CPU time 363.77 seconds
Started Feb 18 01:32:01 PM PST 24
Finished Feb 18 01:38:08 PM PST 24
Peak memory 369928 kb
Host smart-3d2e44c1-4f94-4b1c-9f31-4f5e600c33bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237674102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1237674102
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.385804707
Short name T459
Test name
Test status
Simulation time 935841501 ps
CPU time 11.43 seconds
Started Feb 18 01:31:53 PM PST 24
Finished Feb 18 01:32:05 PM PST 24
Peak memory 227820 kb
Host smart-43720cd7-fec9-4089-8aad-68edfaaec474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385804707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.385804707
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.2808846250
Short name T665
Test name
Test status
Simulation time 258816294374 ps
CPU time 3037.1 seconds
Started Feb 18 01:32:05 PM PST 24
Finished Feb 18 02:22:44 PM PST 24
Peak memory 376176 kb
Host smart-c7f7fa82-f02b-40fe-8d2e-8285fedcc4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808846250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.2808846250
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1269498888
Short name T840
Test name
Test status
Simulation time 3214093987 ps
CPU time 205.73 seconds
Started Feb 18 01:31:52 PM PST 24
Finished Feb 18 01:35:19 PM PST 24
Peak memory 202304 kb
Host smart-2730fac8-57ff-4a66-afe6-a5d26c88af31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269498888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.1269498888
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1888016350
Short name T650
Test name
Test status
Simulation time 1535189524 ps
CPU time 134.27 seconds
Started Feb 18 01:31:59 PM PST 24
Finished Feb 18 01:34:14 PM PST 24
Peak memory 364724 kb
Host smart-df9e8fb5-9ff4-4a13-a917-49e6a058c86e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888016350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1888016350
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1613152012
Short name T708
Test name
Test status
Simulation time 7635772076 ps
CPU time 916.99 seconds
Started Feb 18 01:32:06 PM PST 24
Finished Feb 18 01:47:24 PM PST 24
Peak memory 378388 kb
Host smart-6fd98b8d-1c24-4c1a-84a1-11a12f882778
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613152012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.1613152012
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.1793238899
Short name T306
Test name
Test status
Simulation time 25023621 ps
CPU time 0.64 seconds
Started Feb 18 01:32:13 PM PST 24
Finished Feb 18 01:32:14 PM PST 24
Peak memory 202048 kb
Host smart-b3493ad2-dc8a-416b-b1c5-dcf67a9b324c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793238899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.1793238899
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.3856182374
Short name T429
Test name
Test status
Simulation time 9922790844 ps
CPU time 638.84 seconds
Started Feb 18 01:32:08 PM PST 24
Finished Feb 18 01:42:48 PM PST 24
Peak memory 202300 kb
Host smart-e9633c6a-e372-48d2-8b71-87c01ad1cd4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856182374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.3856182374
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.1469630112
Short name T10
Test name
Test status
Simulation time 32218640112 ps
CPU time 919 seconds
Started Feb 18 01:32:07 PM PST 24
Finished Feb 18 01:47:27 PM PST 24
Peak memory 358672 kb
Host smart-8c5699c8-800d-46e6-a605-529c3f4e83bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469630112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab
le.1469630112
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_lc_escalation.1884915125
Short name T772
Test name
Test status
Simulation time 8716608553 ps
CPU time 96.19 seconds
Started Feb 18 01:32:07 PM PST 24
Finished Feb 18 01:33:44 PM PST 24
Peak memory 202272 kb
Host smart-b601793e-0a06-45ed-b260-5d987faaf9f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884915125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es
calation.1884915125
Directory /workspace/49.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.3295174025
Short name T759
Test name
Test status
Simulation time 1517981174 ps
CPU time 160.64 seconds
Started Feb 18 01:32:07 PM PST 24
Finished Feb 18 01:34:49 PM PST 24
Peak memory 358612 kb
Host smart-511d22b6-e711-4cda-a7b5-c64df2f29b79
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295174025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.3295174025
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3115311507
Short name T727
Test name
Test status
Simulation time 4879055888 ps
CPU time 82.27 seconds
Started Feb 18 01:32:12 PM PST 24
Finished Feb 18 01:33:35 PM PST 24
Peak memory 210792 kb
Host smart-1cd9a443-f122-4fd8-90e6-6207c1faa25c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115311507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.3115311507
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.2290759894
Short name T384
Test name
Test status
Simulation time 14062161225 ps
CPU time 298.6 seconds
Started Feb 18 01:32:07 PM PST 24
Finished Feb 18 01:37:06 PM PST 24
Peak memory 202352 kb
Host smart-6a9b2a40-4139-4df9-90d3-fcf30808f4de
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290759894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.2290759894
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.4129239259
Short name T661
Test name
Test status
Simulation time 19054757007 ps
CPU time 912.29 seconds
Started Feb 18 01:32:05 PM PST 24
Finished Feb 18 01:47:18 PM PST 24
Peak memory 376376 kb
Host smart-08e3d5ca-ed31-4d5a-8883-779cee846c94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129239259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.4129239259
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.1012135535
Short name T277
Test name
Test status
Simulation time 1037177453 ps
CPU time 11.92 seconds
Started Feb 18 01:32:07 PM PST 24
Finished Feb 18 01:32:20 PM PST 24
Peak memory 202712 kb
Host smart-410733de-9297-4b01-8abd-7e11a572ebf4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012135535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.1012135535
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1556076805
Short name T254
Test name
Test status
Simulation time 55120781811 ps
CPU time 425.31 seconds
Started Feb 18 01:32:09 PM PST 24
Finished Feb 18 01:39:15 PM PST 24
Peak memory 202292 kb
Host smart-02101c0d-2d4f-4ae0-98df-4c7ccb26aeb2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556076805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.1556076805
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.155285969
Short name T427
Test name
Test status
Simulation time 1296983718 ps
CPU time 6.74 seconds
Started Feb 18 01:32:04 PM PST 24
Finished Feb 18 01:32:12 PM PST 24
Peak memory 202424 kb
Host smart-d1fcb4c6-d9c3-4c4d-91bc-14a9664326ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155285969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.155285969
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.3185129576
Short name T412
Test name
Test status
Simulation time 14383850268 ps
CPU time 1122.26 seconds
Started Feb 18 01:32:07 PM PST 24
Finished Feb 18 01:50:50 PM PST 24
Peak memory 379136 kb
Host smart-3f3257c3-557f-457e-8e50-65c0df2d3ebb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185129576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.3185129576
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.2787434853
Short name T173
Test name
Test status
Simulation time 810071896 ps
CPU time 8.36 seconds
Started Feb 18 01:32:06 PM PST 24
Finished Feb 18 01:32:16 PM PST 24
Peak memory 202092 kb
Host smart-a299929f-a555-4355-88c5-038035ca9338
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787434853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2787434853
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.1257058110
Short name T809
Test name
Test status
Simulation time 51373510517 ps
CPU time 1071.09 seconds
Started Feb 18 01:32:13 PM PST 24
Finished Feb 18 01:50:05 PM PST 24
Peak memory 372020 kb
Host smart-83637215-1a26-4b46-8328-8f1a53bc87f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257058110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.sram_ctrl_stress_all.1257058110
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1646608812
Short name T190
Test name
Test status
Simulation time 38540865122 ps
CPU time 426.28 seconds
Started Feb 18 01:32:09 PM PST 24
Finished Feb 18 01:39:16 PM PST 24
Peak memory 202304 kb
Host smart-9ef68768-8d41-46c6-8ae8-486ebe135da4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646608812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_stress_pipeline.1646608812
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2317292626
Short name T467
Test name
Test status
Simulation time 785731950 ps
CPU time 101.43 seconds
Started Feb 18 01:32:06 PM PST 24
Finished Feb 18 01:33:48 PM PST 24
Peak memory 317724 kb
Host smart-8931bd60-161f-43f3-9829-90c763c96e43
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317292626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2317292626
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1687086543
Short name T791
Test name
Test status
Simulation time 9911293606 ps
CPU time 1083.26 seconds
Started Feb 18 01:24:27 PM PST 24
Finished Feb 18 01:42:31 PM PST 24
Peak memory 374088 kb
Host smart-8e32b040-3e95-477a-be55-14325d156e5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687086543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.1687086543
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.726622313
Short name T174
Test name
Test status
Simulation time 24851193 ps
CPU time 0.65 seconds
Started Feb 18 01:24:30 PM PST 24
Finished Feb 18 01:24:32 PM PST 24
Peak memory 201272 kb
Host smart-5a05777b-55db-4b64-828e-64b1405c403a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726622313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.726622313
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.3370261305
Short name T230
Test name
Test status
Simulation time 423270454030 ps
CPU time 1205.66 seconds
Started Feb 18 01:24:27 PM PST 24
Finished Feb 18 01:44:34 PM PST 24
Peak memory 202224 kb
Host smart-1ed3b857-1674-44c7-b9d0-bef26c4bdf94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370261305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
3370261305
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.2025531544
Short name T797
Test name
Test status
Simulation time 775796676 ps
CPU time 72.02 seconds
Started Feb 18 01:24:28 PM PST 24
Finished Feb 18 01:25:41 PM PST 24
Peak memory 319752 kb
Host smart-cebb4b1c-cb51-4d4c-afbf-643e9d7f86e6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025531544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.2025531544
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4155593348
Short name T47
Test name
Test status
Simulation time 3197031326 ps
CPU time 128.45 seconds
Started Feb 18 01:24:28 PM PST 24
Finished Feb 18 01:26:37 PM PST 24
Peak memory 211380 kb
Host smart-b6a7c2e8-5b4f-4345-a5db-2fd65505b2b9
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155593348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.4155593348
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.3709243310
Short name T558
Test name
Test status
Simulation time 28134662467 ps
CPU time 287.85 seconds
Started Feb 18 01:24:27 PM PST 24
Finished Feb 18 01:29:15 PM PST 24
Peak memory 202348 kb
Host smart-15086023-3d51-4732-ad86-c7bf472cb43a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709243310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.3709243310
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.159482086
Short name T788
Test name
Test status
Simulation time 27073882527 ps
CPU time 1679.84 seconds
Started Feb 18 01:24:28 PM PST 24
Finished Feb 18 01:52:29 PM PST 24
Peak memory 377264 kb
Host smart-78fe8956-1a87-4020-941d-03d12367dac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159482086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multipl
e_keys.159482086
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.2823200300
Short name T481
Test name
Test status
Simulation time 6361032984 ps
CPU time 53.49 seconds
Started Feb 18 01:24:23 PM PST 24
Finished Feb 18 01:25:18 PM PST 24
Peak memory 288936 kb
Host smart-0165bf3d-60c7-4ae9-99ee-1557b7e39636
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823200300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s
ram_ctrl_partial_access.2823200300
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3991540601
Short name T548
Test name
Test status
Simulation time 97303336962 ps
CPU time 552.83 seconds
Started Feb 18 01:24:29 PM PST 24
Finished Feb 18 01:33:43 PM PST 24
Peak memory 202240 kb
Host smart-592aee93-6756-4c4d-b68b-1e6388de86c7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991540601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.3991540601
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.444466206
Short name T440
Test name
Test status
Simulation time 2808131463 ps
CPU time 7.24 seconds
Started Feb 18 01:24:30 PM PST 24
Finished Feb 18 01:24:39 PM PST 24
Peak memory 202088 kb
Host smart-c900d35d-3a1c-49b6-83e9-6d6b10b2deec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444466206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.444466206
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.2779364966
Short name T631
Test name
Test status
Simulation time 2462257337 ps
CPU time 346.39 seconds
Started Feb 18 01:24:27 PM PST 24
Finished Feb 18 01:30:14 PM PST 24
Peak memory 355612 kb
Host smart-980dcf84-6eb8-42fa-a213-0138af61ba15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779364966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2779364966
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.893859206
Short name T251
Test name
Test status
Simulation time 1724688252 ps
CPU time 29.53 seconds
Started Feb 18 01:24:30 PM PST 24
Finished Feb 18 01:25:00 PM PST 24
Peak memory 202172 kb
Host smart-7f8b4ab1-feb0-4e8b-9e3d-99586f8779a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893859206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.893859206
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.392141884
Short name T782
Test name
Test status
Simulation time 154082694651 ps
CPU time 9397.02 seconds
Started Feb 18 01:24:28 PM PST 24
Finished Feb 18 04:01:07 PM PST 24
Peak memory 381216 kb
Host smart-1ad8938f-99ca-482b-82a8-2e002e50a910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392141884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_stress_all.392141884
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2794506701
Short name T569
Test name
Test status
Simulation time 8590927617 ps
CPU time 313.63 seconds
Started Feb 18 01:24:28 PM PST 24
Finished Feb 18 01:29:43 PM PST 24
Peak memory 202324 kb
Host smart-0b88ba8f-a308-448f-b453-73c9f902a64c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794506701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_stress_pipeline.2794506701
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3414053937
Short name T768
Test name
Test status
Simulation time 3560786484 ps
CPU time 125.58 seconds
Started Feb 18 01:24:23 PM PST 24
Finished Feb 18 01:26:30 PM PST 24
Peak memory 368960 kb
Host smart-f74a80b1-38cd-425a-aa99-1096e346c3e1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414053937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.3414053937
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3378503530
Short name T664
Test name
Test status
Simulation time 24696442830 ps
CPU time 1155.73 seconds
Started Feb 18 01:24:41 PM PST 24
Finished Feb 18 01:43:58 PM PST 24
Peak memory 379220 kb
Host smart-3f9213f7-0212-4243-ba5f-faa7c560da46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378503530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.3378503530
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.3941719347
Short name T575
Test name
Test status
Simulation time 17318816 ps
CPU time 0.62 seconds
Started Feb 18 01:24:38 PM PST 24
Finished Feb 18 01:24:39 PM PST 24
Peak memory 202036 kb
Host smart-90fde742-01b6-4567-8898-226d7fc46638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941719347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.3941719347
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.543046854
Short name T490
Test name
Test status
Simulation time 1892011408 ps
CPU time 27.08 seconds
Started Feb 18 01:24:40 PM PST 24
Finished Feb 18 01:25:07 PM PST 24
Peak memory 208532 kb
Host smart-b6a8bb24-3817-4078-962b-13e37761d5a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543046854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable
.543046854
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.3729912657
Short name T767
Test name
Test status
Simulation time 103100905331 ps
CPU time 75.74 seconds
Started Feb 18 01:24:39 PM PST 24
Finished Feb 18 01:25:56 PM PST 24
Peak memory 210660 kb
Host smart-1c9b9974-985c-4eb3-aa0d-218b9e83a56f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729912657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.3729912657
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.3307703419
Short name T830
Test name
Test status
Simulation time 4058020374 ps
CPU time 76.03 seconds
Started Feb 18 01:24:40 PM PST 24
Finished Feb 18 01:25:56 PM PST 24
Peak memory 310204 kb
Host smart-8d675266-14e5-4ffc-9710-83cfdcf5f48b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307703419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.3307703419
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.813603706
Short name T820
Test name
Test status
Simulation time 4562519520 ps
CPU time 146.67 seconds
Started Feb 18 01:24:39 PM PST 24
Finished Feb 18 01:27:07 PM PST 24
Peak memory 214828 kb
Host smart-95602a76-6234-4f4f-abb8-503bb37fd460
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813603706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
sram_ctrl_mem_partial_access.813603706
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.871680792
Short name T142
Test name
Test status
Simulation time 6893743796 ps
CPU time 141.23 seconds
Started Feb 18 01:24:36 PM PST 24
Finished Feb 18 01:26:59 PM PST 24
Peak memory 202368 kb
Host smart-09a34a15-717b-4179-bc0d-53450a433abd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871680792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_
mem_walk.871680792
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.4178412894
Short name T531
Test name
Test status
Simulation time 34303990554 ps
CPU time 832.6 seconds
Started Feb 18 01:24:37 PM PST 24
Finished Feb 18 01:38:31 PM PST 24
Peak memory 378124 kb
Host smart-249109a7-29f0-4315-a383-6166faa2eac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178412894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip
le_keys.4178412894
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.1688549281
Short name T373
Test name
Test status
Simulation time 1326323772 ps
CPU time 23.85 seconds
Started Feb 18 01:24:39 PM PST 24
Finished Feb 18 01:25:04 PM PST 24
Peak memory 202156 kb
Host smart-27e7bd28-04d8-4a7a-b16b-422ebddcace1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688549281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.1688549281
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2836569814
Short name T503
Test name
Test status
Simulation time 43443971406 ps
CPU time 463.27 seconds
Started Feb 18 01:24:43 PM PST 24
Finished Feb 18 01:32:28 PM PST 24
Peak memory 202244 kb
Host smart-6c02f0e3-e5bf-4543-a6d9-f61a47ccb5ad
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836569814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.2836569814
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.188870638
Short name T239
Test name
Test status
Simulation time 356314556 ps
CPU time 13.34 seconds
Started Feb 18 01:24:39 PM PST 24
Finished Feb 18 01:24:53 PM PST 24
Peak memory 202456 kb
Host smart-c3e1470e-497e-466d-8b09-e67b0b79142b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188870638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.188870638
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.2092096683
Short name T439
Test name
Test status
Simulation time 75878813835 ps
CPU time 1190.57 seconds
Started Feb 18 01:24:38 PM PST 24
Finished Feb 18 01:44:29 PM PST 24
Peak memory 367596 kb
Host smart-7757dbd7-b510-47bf-8aa7-4dc4de22c1bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092096683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2092096683
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.2123289753
Short name T544
Test name
Test status
Simulation time 3316824873 ps
CPU time 36.17 seconds
Started Feb 18 01:24:38 PM PST 24
Finished Feb 18 01:25:16 PM PST 24
Peak memory 202340 kb
Host smart-b27e3b14-601e-4371-8511-0bac2e1be978
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123289753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2123289753
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2749570693
Short name T150
Test name
Test status
Simulation time 17769346742 ps
CPU time 367.1 seconds
Started Feb 18 01:24:37 PM PST 24
Finished Feb 18 01:30:45 PM PST 24
Peak memory 202280 kb
Host smart-c310b389-2cd2-416b-b6cf-b1dbe8514e5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749570693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.2749570693
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1586141680
Short name T630
Test name
Test status
Simulation time 1574463664 ps
CPU time 49.85 seconds
Started Feb 18 01:24:39 PM PST 24
Finished Feb 18 01:25:30 PM PST 24
Peak memory 283984 kb
Host smart-a2e91613-a9bf-4ee0-964e-bad569e54157
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586141680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.1586141680
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3207909640
Short name T240
Test name
Test status
Simulation time 19897688877 ps
CPU time 823.7 seconds
Started Feb 18 01:24:52 PM PST 24
Finished Feb 18 01:38:37 PM PST 24
Peak memory 378180 kb
Host smart-9301d4de-5937-4bc2-9574-3140cd714ab4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207909640 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3207909640
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.2660189072
Short name T831
Test name
Test status
Simulation time 12294282 ps
CPU time 0.64 seconds
Started Feb 18 01:24:54 PM PST 24
Finished Feb 18 01:24:56 PM PST 24
Peak memory 202032 kb
Host smart-9a998e36-323b-4998-8fe8-7a56a0e28c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660189072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.2660189072
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.925621010
Short name T493
Test name
Test status
Simulation time 231701447010 ps
CPU time 766.43 seconds
Started Feb 18 01:24:39 PM PST 24
Finished Feb 18 01:37:26 PM PST 24
Peak memory 202364 kb
Host smart-d91134fa-a550-44b6-855c-3c02dbd69318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925621010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.925621010
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.4204097
Short name T743
Test name
Test status
Simulation time 103258202970 ps
CPU time 1043.71 seconds
Started Feb 18 01:24:46 PM PST 24
Finished Feb 18 01:42:11 PM PST 24
Peak memory 362792 kb
Host smart-c798b8e3-fa40-426c-b689-469cde91cf59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa
ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.4204097
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.1650257056
Short name T315
Test name
Test status
Simulation time 2109435638 ps
CPU time 108.8 seconds
Started Feb 18 01:24:55 PM PST 24
Finished Feb 18 01:26:45 PM PST 24
Peak memory 361744 kb
Host smart-8c7a4354-d6e4-4f52-ab45-1a6a9203f8e5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650257056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.1650257056
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1464200384
Short name T471
Test name
Test status
Simulation time 2452201858 ps
CPU time 78.11 seconds
Started Feb 18 01:24:39 PM PST 24
Finished Feb 18 01:25:58 PM PST 24
Peak memory 211692 kb
Host smart-4d479126-37ad-4bc8-aa89-a6d947e0a0c7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464200384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.1464200384
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.3381183518
Short name T411
Test name
Test status
Simulation time 18612531181 ps
CPU time 144.53 seconds
Started Feb 18 01:24:54 PM PST 24
Finished Feb 18 01:27:19 PM PST 24
Peak memory 202272 kb
Host smart-ef7e33b0-dc18-4437-9237-4805c708e934
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381183518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.3381183518
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.147478929
Short name T596
Test name
Test status
Simulation time 3409207003 ps
CPU time 484.74 seconds
Started Feb 18 01:24:41 PM PST 24
Finished Feb 18 01:32:47 PM PST 24
Peak memory 330124 kb
Host smart-2214a78e-0dcd-4eda-b71d-37425f7dd5ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147478929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multipl
e_keys.147478929
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.1739908457
Short name T476
Test name
Test status
Simulation time 5866786606 ps
CPU time 25.04 seconds
Started Feb 18 01:24:38 PM PST 24
Finished Feb 18 01:25:04 PM PST 24
Peak memory 202196 kb
Host smart-69ae0f8a-23b2-4d3b-950b-0cdeb79c7aef
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739908457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.1739908457
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2784742409
Short name T179
Test name
Test status
Simulation time 19559292361 ps
CPU time 300.58 seconds
Started Feb 18 01:24:52 PM PST 24
Finished Feb 18 01:29:53 PM PST 24
Peak memory 202312 kb
Host smart-49467ac7-2ea1-4f49-bee1-4c639db0535e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784742409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.2784742409
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3717982645
Short name T144
Test name
Test status
Simulation time 359237383 ps
CPU time 13.68 seconds
Started Feb 18 01:24:46 PM PST 24
Finished Feb 18 01:25:00 PM PST 24
Peak memory 202464 kb
Host smart-e10884d5-f4ed-4100-ad96-088ebbf59a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717982645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3717982645
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.480877743
Short name T642
Test name
Test status
Simulation time 22918490137 ps
CPU time 1496.31 seconds
Started Feb 18 01:24:53 PM PST 24
Finished Feb 18 01:49:50 PM PST 24
Peak memory 377116 kb
Host smart-205eb4c6-09cf-44e8-85b5-1a592ddbbe49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480877743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.480877743
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.318326816
Short name T793
Test name
Test status
Simulation time 1172307926 ps
CPU time 20.29 seconds
Started Feb 18 01:24:44 PM PST 24
Finished Feb 18 01:25:05 PM PST 24
Peak memory 202104 kb
Host smart-c3dfdc0e-02fe-4b82-8e9b-99db024d0369
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318326816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.318326816
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.318445913
Short name T501
Test name
Test status
Simulation time 1031437367581 ps
CPU time 8149.49 seconds
Started Feb 18 01:24:55 PM PST 24
Finished Feb 18 03:40:46 PM PST 24
Peak memory 381212 kb
Host smart-b957c9f9-1690-426c-a82f-2c7ca63995b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318445913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_stress_all.318445913
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.527380444
Short name T223
Test name
Test status
Simulation time 15180576010 ps
CPU time 291.24 seconds
Started Feb 18 01:24:36 PM PST 24
Finished Feb 18 01:29:29 PM PST 24
Peak memory 202308 kb
Host smart-4f83dc73-e74b-42a5-a07d-423421e6b695
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527380444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
sram_ctrl_stress_pipeline.527380444
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1992828505
Short name T259
Test name
Test status
Simulation time 1482724522 ps
CPU time 59.32 seconds
Started Feb 18 01:24:52 PM PST 24
Finished Feb 18 01:25:52 PM PST 24
Peak memory 292616 kb
Host smart-d57f426b-abaa-488f-a4ca-949efe313a20
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992828505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1992828505
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2556499816
Short name T734
Test name
Test status
Simulation time 19232556506 ps
CPU time 592.68 seconds
Started Feb 18 01:24:59 PM PST 24
Finished Feb 18 01:34:53 PM PST 24
Peak memory 372056 kb
Host smart-b1e37396-3d9d-4df4-a047-bdce28b88ec6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556499816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.2556499816
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.1098175601
Short name T553
Test name
Test status
Simulation time 25932297 ps
CPU time 0.71 seconds
Started Feb 18 01:25:03 PM PST 24
Finished Feb 18 01:25:06 PM PST 24
Peak memory 201748 kb
Host smart-10377431-421e-4ea8-b17e-b21503fe91ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098175601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.1098175601
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.1363060148
Short name T156
Test name
Test status
Simulation time 605330629851 ps
CPU time 2835.69 seconds
Started Feb 18 01:24:53 PM PST 24
Finished Feb 18 02:12:10 PM PST 24
Peak memory 202260 kb
Host smart-cc69e9b5-a23c-4ad6-ac5f-131ed5dc050c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363060148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
1363060148
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.3006123702
Short name T273
Test name
Test status
Simulation time 37378426653 ps
CPU time 809.64 seconds
Started Feb 18 01:25:00 PM PST 24
Finished Feb 18 01:38:30 PM PST 24
Peak memory 377160 kb
Host smart-a9adf683-6c0d-4726-a471-e946f05c2e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006123702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.3006123702
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_lc_escalation.178585064
Short name T463
Test name
Test status
Simulation time 14793729119 ps
CPU time 155.89 seconds
Started Feb 18 01:24:53 PM PST 24
Finished Feb 18 01:27:30 PM PST 24
Peak memory 213944 kb
Host smart-4ed6ea2a-3530-4872-b0fc-5aa11c8b7798
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178585064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esca
lation.178585064
Directory /workspace/8.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.4012217833
Short name T217
Test name
Test status
Simulation time 751260798 ps
CPU time 51.09 seconds
Started Feb 18 01:24:55 PM PST 24
Finished Feb 18 01:25:47 PM PST 24
Peak memory 284936 kb
Host smart-24b49fd5-4791-47ee-b997-39f222b4547f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012217833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sram_ctrl_max_throughput.4012217833
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1790587593
Short name T545
Test name
Test status
Simulation time 6209813658 ps
CPU time 128.17 seconds
Started Feb 18 01:25:00 PM PST 24
Finished Feb 18 01:27:09 PM PST 24
Peak memory 211452 kb
Host smart-db7db405-e630-4332-bb12-89595f099d09
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790587593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.1790587593
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.4225895335
Short name T194
Test name
Test status
Simulation time 41292436245 ps
CPU time 165.68 seconds
Started Feb 18 01:25:00 PM PST 24
Finished Feb 18 01:27:47 PM PST 24
Peak memory 202360 kb
Host smart-d1d19c83-0748-412c-8276-bc0ce64d073e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225895335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.4225895335
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.921446996
Short name T659
Test name
Test status
Simulation time 4154642387 ps
CPU time 233.47 seconds
Started Feb 18 01:24:51 PM PST 24
Finished Feb 18 01:28:46 PM PST 24
Peak memory 369100 kb
Host smart-352d936f-3db6-4c4c-993c-3ecde34c6061
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921446996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl
e_keys.921446996
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.3383779166
Short name T731
Test name
Test status
Simulation time 984143045 ps
CPU time 5.5 seconds
Started Feb 18 01:25:00 PM PST 24
Finished Feb 18 01:25:07 PM PST 24
Peak memory 202112 kb
Host smart-df96f5d4-696d-41e7-abd4-fc454b7b5538
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383779166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.3383779166
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4294428953
Short name T246
Test name
Test status
Simulation time 27882897738 ps
CPU time 305.07 seconds
Started Feb 18 01:24:59 PM PST 24
Finished Feb 18 01:30:04 PM PST 24
Peak memory 202284 kb
Host smart-9414bfe5-8962-4fca-8289-8c73f6070d94
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294428953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.4294428953
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.1491298108
Short name T348
Test name
Test status
Simulation time 2582139824 ps
CPU time 6.07 seconds
Started Feb 18 01:25:00 PM PST 24
Finished Feb 18 01:25:07 PM PST 24
Peak memory 202552 kb
Host smart-6a9428ef-6c54-4392-83fb-056f71d529cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491298108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1491298108
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3294324255
Short name T258
Test name
Test status
Simulation time 19997704895 ps
CPU time 261.02 seconds
Started Feb 18 01:24:59 PM PST 24
Finished Feb 18 01:29:20 PM PST 24
Peak memory 339036 kb
Host smart-dfe27749-ac80-4c73-bdf8-af9ea93fbcef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294324255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3294324255
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.3546771832
Short name T331
Test name
Test status
Simulation time 1339976034 ps
CPU time 11.04 seconds
Started Feb 18 01:24:54 PM PST 24
Finished Feb 18 01:25:06 PM PST 24
Peak memory 202100 kb
Host smart-327ea0c3-9650-4b31-8bcd-2df124827d02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546771832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.3546771832
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.1233558842
Short name T116
Test name
Test status
Simulation time 39208195436 ps
CPU time 2309.51 seconds
Started Feb 18 01:24:58 PM PST 24
Finished Feb 18 02:03:28 PM PST 24
Peak memory 364856 kb
Host smart-56ed6ca7-b035-4bd0-a635-275c9fe48ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233558842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.1233558842
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2442151321
Short name T477
Test name
Test status
Simulation time 9301150080 ps
CPU time 170.23 seconds
Started Feb 18 01:24:55 PM PST 24
Finished Feb 18 01:27:46 PM PST 24
Peak memory 202316 kb
Host smart-383b48a2-83c3-411d-9fd5-cfc5572873c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442151321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.2442151321
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2718534649
Short name T812
Test name
Test status
Simulation time 2058144838 ps
CPU time 29.59 seconds
Started Feb 18 01:25:00 PM PST 24
Finished Feb 18 01:25:30 PM PST 24
Peak memory 215580 kb
Host smart-a43c5e29-ed3d-437b-b4cf-abbc87e9d2b0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718534649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2718534649
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.964849335
Short name T218
Test name
Test status
Simulation time 4076763965 ps
CPU time 698 seconds
Started Feb 18 01:25:06 PM PST 24
Finished Feb 18 01:36:45 PM PST 24
Peak memory 371304 kb
Host smart-73cd0297-5961-4b3b-b488-d7fd2c81c7a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964849335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.sram_ctrl_access_during_key_req.964849335
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.3944714370
Short name T454
Test name
Test status
Simulation time 20352718 ps
CPU time 0.62 seconds
Started Feb 18 01:25:11 PM PST 24
Finished Feb 18 01:25:12 PM PST 24
Peak memory 202024 kb
Host smart-12d7e731-ee6e-4259-8236-e2f4b1c3c6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944714370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.3944714370
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.2204178966
Short name T643
Test name
Test status
Simulation time 28381931919 ps
CPU time 1735.95 seconds
Started Feb 18 01:25:05 PM PST 24
Finished Feb 18 01:54:03 PM PST 24
Peak memory 202320 kb
Host smart-5ec3e45c-174a-45e0-86dc-a424d8678584
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204178966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
2204178966
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.2107248408
Short name T604
Test name
Test status
Simulation time 35255837431 ps
CPU time 1024.95 seconds
Started Feb 18 01:25:01 PM PST 24
Finished Feb 18 01:42:08 PM PST 24
Peak memory 378244 kb
Host smart-7c2fc210-4005-41be-be30-289d4e14d5f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107248408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.2107248408
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.3884158368
Short name T662
Test name
Test status
Simulation time 8362067773 ps
CPU time 155.42 seconds
Started Feb 18 01:25:01 PM PST 24
Finished Feb 18 01:27:37 PM PST 24
Peak memory 210560 kb
Host smart-997d1dd8-ddb0-443c-8825-2fca029be646
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884158368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc
alation.3884158368
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.1845934285
Short name T472
Test name
Test status
Simulation time 1013022386 ps
CPU time 38.68 seconds
Started Feb 18 01:25:03 PM PST 24
Finished Feb 18 01:25:44 PM PST 24
Peak memory 261904 kb
Host smart-68863b28-772a-457f-bbd5-ea5c745ae706
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845934285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.1845934285
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4168651914
Short name T741
Test name
Test status
Simulation time 9667615394 ps
CPU time 145.18 seconds
Started Feb 18 01:25:09 PM PST 24
Finished Feb 18 01:27:35 PM PST 24
Peak memory 214592 kb
Host smart-56b940df-54e5-40ff-b5b0-53e78ae27461
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168651914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.4168651914
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.2642479335
Short name T434
Test name
Test status
Simulation time 4030475333 ps
CPU time 119.96 seconds
Started Feb 18 01:25:03 PM PST 24
Finished Feb 18 01:27:05 PM PST 24
Peak memory 202236 kb
Host smart-15ef6b72-11ff-49e2-8617-75478e2a3942
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642479335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.2642479335
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.2731436418
Short name T29
Test name
Test status
Simulation time 143858687409 ps
CPU time 949.26 seconds
Started Feb 18 01:25:06 PM PST 24
Finished Feb 18 01:40:56 PM PST 24
Peak memory 377152 kb
Host smart-ef0c8db9-6a1d-480a-b0f0-5951bbd60998
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731436418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.2731436418
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.227229369
Short name T300
Test name
Test status
Simulation time 3069647374 ps
CPU time 80.18 seconds
Started Feb 18 01:25:04 PM PST 24
Finished Feb 18 01:26:26 PM PST 24
Peak memory 318944 kb
Host smart-66e2a660-d469-4af8-a86f-36705ffbb6c2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227229369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr
am_ctrl_partial_access.227229369
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2229032339
Short name T92
Test name
Test status
Simulation time 11936467842 ps
CPU time 154.16 seconds
Started Feb 18 01:25:01 PM PST 24
Finished Feb 18 01:27:37 PM PST 24
Peak memory 202232 kb
Host smart-924199ac-693c-40da-9ee0-c3aa16714a39
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229032339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2229032339
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.3006680172
Short name T201
Test name
Test status
Simulation time 1349437590 ps
CPU time 5.46 seconds
Started Feb 18 01:25:01 PM PST 24
Finished Feb 18 01:25:08 PM PST 24
Peak memory 202432 kb
Host smart-88bfb704-c1dd-46f3-b41b-37448d6ff126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006680172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3006680172
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.2748526365
Short name T343
Test name
Test status
Simulation time 72115196204 ps
CPU time 828.18 seconds
Started Feb 18 01:25:04 PM PST 24
Finished Feb 18 01:38:54 PM PST 24
Peak memory 369968 kb
Host smart-c1a9f2f3-df27-4c8f-ab78-4e7a34f13fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748526365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2748526365
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.3325061412
Short name T143
Test name
Test status
Simulation time 720630007 ps
CPU time 36.99 seconds
Started Feb 18 01:25:02 PM PST 24
Finished Feb 18 01:25:42 PM PST 24
Peak memory 297096 kb
Host smart-ed8b3ab5-a211-46bb-9d23-d504d7afb85f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325061412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3325061412
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.853869345
Short name T90
Test name
Test status
Simulation time 5469196779 ps
CPU time 404.5 seconds
Started Feb 18 01:25:02 PM PST 24
Finished Feb 18 01:31:48 PM PST 24
Peak memory 202296 kb
Host smart-e6fb0c14-060a-44cd-89aa-4077024fb041
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853869345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
sram_ctrl_stress_pipeline.853869345
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.823620323
Short name T401
Test name
Test status
Simulation time 3337425856 ps
CPU time 27.35 seconds
Started Feb 18 01:25:01 PM PST 24
Finished Feb 18 01:25:31 PM PST 24
Peak memory 210568 kb
Host smart-9460d4a4-95f0-4deb-98c4-0c2e670d6e91
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823620323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_throughput_w_partial_write.823620323
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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