Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14904342

1

T1

725

T2

1910

T3

12

full_word

123933780

1

T1

7269

T2

428

T3

132

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	138837832	1			T1	7994		T2	2338		T3	144
auto[TlIntgErrCmd]	115	1			T34	9		T35	6		T36	2
auto[TlIntgErrData]	95	1			T34	8		T35	8		T36	4
auto[TlIntgErrBoth]	80	1			T34	3		T35	6		T36	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67210352

1

T1

3980

T2

1131

T3

75

auto[1]

71627770

1

T1

4014

T2

1207

T3

69

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7401460	1			T1	360		T2	923		T3	7
auto[TlIntgErrNone]	partial	auto[1]	7502615	1			T1	365		T2	987		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	59808771	1			T1	3620		T2	208		T3	68
auto[TlIntgErrNone]	full_word	auto[1]	64124986	1			T1	3649		T2	220		T3	64
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T34	4		T36	1		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T34	5		T35	6		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T36	1		T61	2		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T61	1		T106	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	36	1			T34	2		T35	4		T36	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T34	6		T35	4		T36	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T36	1		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T61	1		T108	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T34	2		T35	2		T36	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T34	1		T35	3		T36	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T112	1		T108	1		T115	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T35	1		T55	1		T109	1