Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	864053	1			T3	16		T5	1		T13	35396
auto[1]	10539127	1			T1	22		T3	5		T6	19381
auto[2]	667674	1			T3	15		T5	1		T13	30058
auto[3]	10327463	1			T1	22		T3	3		T6	19398

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13573871	1			T1	41		T3	33		T6	32277
auto[1]	2085613	1			T1	2		T3	2		T6	3150
auto[2]	2115906	1			T1	1		T3	3		T6	3019
auto[3]	4622927	1			T3	1		T6	333		T4	1828

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8662479

1

T1

44

T3

39

T6

38778

auto[1]

13735838

1

T6

1

T4

224207

T13

120172

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	282072	1			T3	13		T5	1		T14	2805
auto[0]	auto[0]	auto[1]	29352	1			T3	2		T13	2		T14	263
auto[0]	auto[0]	auto[2]	29445	1			T3	1		T13	1		T14	261
auto[0]	auto[0]	auto[3]	53997	1			T13	5		T14	28		T81	20
auto[0]	auto[1]	auto[0]	2774547	1			T1	22		T3	4		T6	16133
auto[0]	auto[1]	auto[1]	301504	1			T6	1517		T4	3		T12	4
auto[0]	auto[1]	auto[2]	335366	1			T6	1556		T12	3		T16	143
auto[0]	auto[1]	auto[3]	636768	1			T3	1		T6	175		T12	1
auto[0]	auto[2]	auto[0]	210837	1			T3	13		T5	1		T14	2523
auto[0]	auto[2]	auto[1]	25774	1			T13	1		T14	234		T81	115
auto[0]	auto[2]	auto[2]	19663	1			T3	2		T13	1		T14	203
auto[0]	auto[2]	auto[3]	36001	1			T13	6		T14	28		T81	25
auto[0]	auto[3]	auto[0]	2688587	1			T1	19		T3	3		T6	16143
auto[0]	auto[3]	auto[1]	321446	1			T1	2		T6	1633		T4	2
auto[0]	auto[3]	auto[2]	336366	1			T1	1		T6	1463		T4	2
auto[0]	auto[3]	auto[3]	580754	1			T6	158		T15	5		T16	3447
auto[1]	auto[0]	auto[0]	15397	1			T13	1154		T123	1140		T124	661
auto[1]	auto[0]	auto[1]	70403	1			T13	5239		T123	5132		T125	1
auto[1]	auto[0]	auto[2]	69951	1			T13	5175		T123	5112		T124	3009
auto[1]	auto[0]	auto[3]	313436	1			T13	23820		T123	23040		T124	13313
auto[1]	auto[1]	auto[0]	3796543	1			T4	92845		T13	169		T15	159
auto[1]	auto[1]	auto[1]	663660	1			T4	9291		T13	5214		T15	1926
auto[1]	auto[1]	auto[2]	620718	1			T4	9219		T13	851		T15	658
auto[1]	auto[1]	auto[3]	1410021	1			T4	905		T13	23554		T15	8742
auto[1]	auto[2]	auto[0]	13768	1			T13	1093		T7	1		T26	1
auto[1]	auto[2]	auto[1]	61585	1			T13	4889		T123	4776		T124	2728
auto[1]	auto[2]	auto[2]	54660	1			T13	4366		T123	4392		T124	2607
auto[1]	auto[2]	auto[3]	245386	1			T13	19702		T123	19282		T124	11079
auto[1]	auto[3]	auto[0]	3792120	1			T6	1		T4	92382		T13	106
auto[1]	auto[3]	auto[1]	611889	1			T4	9300		T13	377		T15	665
auto[1]	auto[3]	auto[2]	649737	1			T4	9342		T13	4384		T15	1881
auto[1]	auto[3]	auto[3]	1346564	1			T4	923		T13	20079		T15	8640