Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	939005897	6457	0	0
ctrl_regwen_rd_A	939005897	2436	0	0
exec_rd_A	939005897	2262	0	0
exec_regwen_rd_A	939005897	2214	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939005897	6457	0	0
T35	20056	2	0	0
T36	14217	1	0	0
T37	3433	472	0	0
T51	2213	58	0	0
T52	8303	299	0	0
T53	5316	110	0	0
T54	9732	294	0	0
T55	9003	1	0	0
T56	4392	166	0	0
T58	6723	1	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939005897	2436	0	0
T34	19865	113	0	0
T35	20056	75	0	0
T36	14217	21	0	0
T52	8303	31	0	0
T53	5316	17	0	0
T54	9732	38	0	0
T67	732313	70	0	0
T69	16655	464	0	0
T101	2551	6	0	0
T104	8034	115	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939005897	2262	0	0
T34	19865	81	0	0
T35	20056	81	0	0
T36	14217	24	0	0
T52	8303	29	0	0
T53	5316	26	0	0
T54	9732	16	0	0
T55	9003	39	0	0
T67	732313	86	0	0
T69	16655	407	0	0
T104	8034	134	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939005897	2214	0	0
T34	19865	71	0	0
T35	20056	85	0	0
T36	14217	11	0	0
T52	8303	24	0	0
T53	5316	2	0	0
T54	9732	11	0	0
T67	732313	49	0	0
T69	16655	436	0	0
T101	2551	2	0	0
T104	8034	109	0	0