Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14501954

1

T1

29420

T2

25549

T4

19672

full_word

128625274

1

T1

1581

T2

256179

T3

196606

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	143126878	1			T1	31001		T2	281728		T3	196606
auto[TlIntgErrCmd]	110	1			T30	5		T31	8		T32	6
auto[TlIntgErrData]	136	1			T30	8		T31	9		T32	6
auto[TlIntgErrBoth]	104	1			T30	7		T31	3		T32	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69383036

1

T1

15404

T2

140613

T3

65536

auto[1]

73744192

1

T1

15597

T2

141115

T3

131070

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7208165	1			T1	15271		T2	12663		T4	9820
auto[TlIntgErrNone]	partial	auto[1]	7293468	1			T1	14149		T2	12886		T4	9852
auto[TlIntgErrNone]	full_word	auto[0]	62174710	1			T1	133		T2	127950		T3	65536
auto[TlIntgErrNone]	full_word	auto[1]	66450535	1			T1	1448		T2	128229		T3	131070
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T30	3		T31	2		T32	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T30	2		T31	6		T32	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T32	1		T49	1		T96	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T49	1		T54	1		T55	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T30	1		T31	2		T32	4
auto[TlIntgErrData]	partial	auto[1]	66	1			T30	6		T31	6		T32	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T31	1		T50	1		T97	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T30	1		T98	1		T99	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T30	3		T31	2		T32	4
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T30	3		T31	1		T32	4
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T30	1		T55	1		T100	2