Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	803432	1			T1	4314		T6	5046		T14	1298
auto[1]	9891236	1			T1	4040		T2	117115		T4	91861
auto[2]	637602	1			T1	3330		T6	4040		T14	703
auto[3]	9725811	1			T1	3194		T2	117562		T4	91190

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	12689568	1			T1	7		T2	195775		T4	151505
auto[1]	1976166	1			T1	473		T2	18668		T4	14961
auto[2]	2001522	1			T1	420		T2	18461		T4	15078
auto[3]	4390825	1			T1	13978		T2	1773		T4	1507

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7969918

1

T1

14876

T2

36

T4

40

auto[1]

13088163

1

T1

2

T2

234641

T4

183011

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	327460	1			T6	4134		T14	1049		T7	31
auto[0]	auto[0]	auto[1]	34293	1			T1	37		T6	433		T14	109
auto[0]	auto[0]	auto[2]	34241	1			T1	45		T6	435		T14	125
auto[0]	auto[0]	auto[3]	54579	1			T1	4231		T6	44		T14	15
auto[0]	auto[1]	auto[0]	2495078	1			T1	1		T2	10		T4	14
auto[0]	auto[1]	auto[1]	278522	1			T1	27		T2	1		T4	1
auto[0]	auto[1]	auto[2]	297928	1			T1	54		T2	2		T4	3
auto[0]	auto[1]	auto[3]	562838	1			T1	3958		T10	119		T12	46
auto[0]	auto[2]	auto[0]	257639	1			T1	3		T6	3398		T14	561
auto[0]	auto[2]	auto[1]	30344	1			T1	379		T6	361		T14	47
auto[0]	auto[2]	auto[2]	23886	1			T1	30		T6	254		T14	88
auto[0]	auto[2]	auto[3]	38671	1			T1	2917		T6	27		T14	7
auto[0]	auto[3]	auto[0]	2424587	1			T1	3		T2	21		T4	18
auto[0]	auto[3]	auto[1]	286939	1			T1	30		T2	1		T4	2
auto[0]	auto[3]	auto[2]	306737	1			T1	291		T2	1		T4	2
auto[0]	auto[3]	auto[3]	516176	1			T1	2870		T10	121		T12	42
auto[1]	auto[0]	auto[0]	11564	1			T40	733		T108	566		T109	860
auto[1]	auto[0]	auto[1]	52536	1			T40	3258		T108	2426		T109	4036
auto[1]	auto[0]	auto[2]	52303	1			T40	3321		T108	2409		T109	4018
auto[1]	auto[0]	auto[3]	236456	1			T1	1		T75	2		T40	14797
auto[1]	auto[1]	auto[0]	3583608	1			T2	97755		T4	76110		T5	83115
auto[1]	auto[1]	auto[1]	644176	1			T2	8820		T4	7413		T5	8287
auto[1]	auto[1]	auto[2]	609634	1			T2	9629		T4	7563		T5	8254
auto[1]	auto[1]	auto[3]	1419452	1			T2	898		T4	757		T5	806
auto[1]	auto[2]	auto[0]	10251	1			T40	667		T108	522		T109	831
auto[1]	auto[2]	auto[1]	46195	1			T40	2938		T108	2222		T109	3659
auto[1]	auto[2]	auto[2]	41988	1			T40	2831		T108	1674		T109	2725
auto[1]	auto[2]	auto[3]	188628	1			T1	1		T40	12640		T108	7315
auto[1]	auto[3]	auto[0]	3579381	1			T2	97989		T4	75363		T5	82491
auto[1]	auto[3]	auto[1]	603161	1			T2	9846		T4	7545		T5	8297
auto[1]	auto[3]	auto[2]	634805	1			T2	8829		T4	7510		T5	8295
auto[1]	auto[3]	auto[3]	1374025	1			T2	875		T4	750		T5	795