Line Coverage for Module :
prim_sparse_fsm_flop
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 40 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
ROUTINE | 47 | 4 | 4 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
40 |
1 |
1 |
43 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
51 |
1 |
1 |
Assert Coverage for Module :
prim_sparse_fsm_flop
Assertion Details
AssertConnected_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
791 |
791 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |