Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1046520776	6468	0	0
ctrl_regwen_rd_A	1046520776	1040	0	0
exec_rd_A	1046520776	1026	0	0
exec_regwen_rd_A	1046520776	1045	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046520776	6468	0	0
T30	12963	3	0	0
T31	18897	2	0	0
T32	27032	2	0	0
T33	13298	479	0	0
T46	5745	3	0	0
T47	5514	153	0	0
T48	11527	419	0	0
T49	39632	3	0	0
T50	18448	3	0	0
T51	1550	73	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046520776	1040	0	0
T32	27032	65	0	0
T33	13298	118	0	0
T57	2406	28	0	0
T59	370431	30	0	0
T61	369941	36	0	0
T64	2084	20	0	0
T86	1539	12	0	0
T88	1041	14	0	0
T94	1967	8	0	0
T95	1612	14	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046520776	1026	0	0
T32	27032	82	0	0
T33	13298	83	0	0
T57	2406	16	0	0
T59	370431	32	0	0
T61	369941	28	0	0
T64	2084	13	0	0
T86	1539	36	0	0
T88	1041	13	0	0
T94	1967	20	0	0
T95	1612	11	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046520776	1045	0	0
T32	27032	57	0	0
T33	13298	144	0	0
T57	2406	10	0	0
T59	370431	8	0	0
T61	369941	31	0	0
T64	2084	26	0	0
T69	369488	15	0	0
T86	1539	19	0	0
T94	1967	28	0	0
T95	1612	16	0	0