Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15140430

1

T1

29874

T2

708

T3

17525

full_word

124426956

1

T1

1469

T2

7469

T3

176324

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	139567086	1			T1	31343		T2	8177		T3	193849
auto[TlIntgErrCmd]	107	1			T34	3		T35	7		T36	4
auto[TlIntgErrData]	104	1			T34	3		T35	6		T36	9
auto[TlIntgErrBoth]	89	1			T34	4		T35	7		T36	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67371877

1

T1

15549

T2

4138

T3

97207

auto[1]

72195509

1

T1

15794

T2

4039

T3

96642

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7498403	1			T1	15439		T2	362		T3	8880
auto[TlIntgErrNone]	partial	auto[1]	7641755	1			T1	14435		T2	346		T3	8645
auto[TlIntgErrNone]	full_word	auto[0]	59873333	1			T1	110		T2	3776		T3	88327
auto[TlIntgErrNone]	full_word	auto[1]	64553595	1			T1	1359		T2	3693		T3	87997
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T34	1		T35	3		T36	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T34	1		T35	3		T36	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T34	1		T35	1		T57	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T57	1		T58	1		T109	2
auto[TlIntgErrData]	partial	auto[0]	51	1			T34	2		T35	4		T36	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T34	1		T35	2		T36	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T57	1		T110	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T36	1		T111	1		T112	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T34	2		T36	3		T58	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T34	1		T35	5		T36	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T34	1		T36	1		T58	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T35	2		T36	1		T58	1