Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	850189	1			T4	16277		T14	8473		T15	31836
auto[1]	11206590	1			T1	14146		T3	49427		T4	3939
auto[2]	666095	1			T4	14564		T14	5664		T15	27290
auto[3]	11011661	1			T1	14394		T3	49420		T4	2139

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14565180	1			T1	121		T3	81985		T4	29019
auto[1]	2236800	1			T1	1337		T3	8009		T4	4079
auto[2]	2249514	1			T1	2439		T3	8046		T4	3368
auto[3]	4683041	1			T1	24643		T3	807		T4	453

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8881439

1

T1

28539

T3

98847

T4

36916

auto[1]

14853096

1

T1

1

T4

3

T13

275406

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	296056	1			T4	13309		T15	26343		T118	3166
auto[0]	auto[0]	auto[1]	31003	1			T4	1415		T14	56		T15	2595
auto[0]	auto[0]	auto[2]	31168	1			T4	1409		T14	54		T15	2622
auto[0]	auto[0]	auto[3]	100787	1			T4	142		T14	8362		T15	275
auto[0]	auto[1]	auto[0]	3015170	1			T1	11		T3	40878		T4	2280
auto[0]	auto[1]	auto[1]	318479	1			T1	88		T3	4045		T4	1280
auto[0]	auto[1]	auto[2]	333070	1			T1	1311		T3	4088		T4	235
auto[0]	auto[1]	auto[3]	441027	1			T1	12736		T3	416		T4	143
auto[0]	auto[2]	auto[0]	219587	1			T4	12315		T14	3		T15	23107
auto[0]	auto[2]	auto[1]	30220	1			T4	1266		T14	695		T15	2313
auto[0]	auto[2]	auto[2]	21976	1			T4	893		T14	37		T15	1710
auto[0]	auto[2]	auto[3]	69845	1			T4	90		T14	4928		T15	159
auto[0]	auto[3]	auto[0]	2926604	1			T1	110		T3	41107		T4	1113
auto[0]	auto[3]	auto[1]	318907	1			T1	1249		T3	3964		T4	117
auto[0]	auto[3]	auto[2]	335725	1			T1	1128		T3	3958		T4	831
auto[0]	auto[3]	auto[3]	391815	1			T1	11906		T3	391		T4	78
auto[1]	auto[0]	auto[0]	12986	1			T4	2		T15	1		T97	728
auto[1]	auto[0]	auto[1]	58405	1			T97	3154		T98	2001		T119	3518
auto[1]	auto[0]	auto[2]	58192	1			T97	3069		T98	2025		T119	3471
auto[1]	auto[0]	auto[3]	261592	1			T14	1		T97	14266		T98	9310
auto[1]	auto[1]	auto[0]	4041884	1			T13	113951		T17	102717		T18	1
auto[1]	auto[1]	auto[1]	727887	1			T4	1		T13	11065		T17	10501
auto[1]	auto[1]	auto[2]	705058	1			T13	11376		T17	10204		T75	9514
auto[1]	auto[1]	auto[3]	1624015	1			T13	1149		T17	1032		T75	875
auto[1]	auto[2]	auto[0]	11330	1			T15	1		T97	614		T98	274
auto[1]	auto[2]	auto[1]	51365	1			T97	2975		T98	1242		T119	3206
auto[1]	auto[2]	auto[2]	47553	1			T97	2109		T98	1971		T119	2909
auto[1]	auto[2]	auto[3]	214219	1			T14	1		T97	9748		T98	8778
auto[1]	auto[3]	auto[0]	4041563	1			T13	114266		T17	103245		T18	2
auto[1]	auto[3]	auto[1]	700534	1			T13	11244		T17	10316		T75	9435
auto[1]	auto[3]	auto[2]	716772	1			T13	11259		T17	10440		T18	1
auto[1]	auto[3]	auto[3]	1579741	1			T1	1		T13	1096		T17	1017