Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	986843693	8089	0	0
ctrl_regwen_rd_A	986843693	1481	0	0
exec_rd_A	986843693	1328	0	0
exec_regwen_rd_A	986843693	1497	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	986843693	8089	0	0
T34	8085	1	0	0
T35	13771	3	0	0
T36	16055	1	0	0
T37	7774	363	0	0
T52	14649	734	0	0
T53	12454	316	0	0
T54	2755	61	0	0
T55	13157	644	0	0
T56	5633	282	0	0
T57	11867	2	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	986843693	1481	0	0
T52	14649	83	0	0
T53	12454	127	0	0
T56	5633	63	0	0
T58	17856	51	0	0
T61	11983	37	0	0
T66	2190	28	0	0
T73	370099	38	0	0
T81	1417	6	0	0
T103	833	4	0	0
T104	992	5	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	986843693	1328	0	0
T52	14649	116	0	0
T53	12454	57	0	0
T56	5633	20	0	0
T58	17856	55	0	0
T61	11983	54	0	0
T63	10545	47	0	0
T66	2190	58	0	0
T73	370099	21	0	0
T81	1417	1	0	0
T104	992	6	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	986843693	1497	0	0
T52	14649	113	0	0
T53	12454	139	0	0
T56	5633	46	0	0
T58	17856	76	0	0
T61	11983	56	0	0
T63	10545	46	0	0
T66	2190	9	0	0
T73	370099	40	0	0
T81	1417	3	0	0
T104	992	7	0	0