Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	316888586	1			T1	541354		T2	9174		T3	821574
instr_valid_dis	283621422	1			T1	541310		T2	9174		T3	510564
instr_en	24732380	1			T1	44		T3	310030		T15	58812

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10460610	1			T1	123978		T3	54868		T4	89390
sram_ifetch_valid_disable	286372829	1			T1	162116		T2	9174		T3	641120
sram_ifetch_enable	20055147	1			T1	255260		T3	125586		T4	333418

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	316888586	1			T1	541354		T2	9174		T3	821574
hw_debug_en_valid_off	285933406	1			T1	220010		T2	9174		T3	592948
hw_debug_en_on	22745934	1			T1	207816		T3	194306		T4	288908

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	286372829	1			T1	162116		T2	9174		T3	641120
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	269761213	1			T1	162072		T2	9174		T3	497488
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	13624302	1			T1	44		T3	143632		T15	28034
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4735596	1			T4	31020		T15	15740		T51	71752
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2774126	1			T4	17694		T15	58		T51	71752
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1290010	1			T124	66810		T27	15366		T52	47298
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3782142	1			T1	115144		T3	54868		T4	58370
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1717212	1			T1	115144		T4	58370		T15	12714
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1501626	1			T3	54868		T52	16650		T125	42530
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10312304	1			T3	115760		T4	83788		T23	44
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2974588	1			T4	69874		T51	85174		T128	77648
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6324390	1			T3	115760		T27	20000		T52	124458

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7743110	1			T3	111530		T15	30778		T124	137014
lc_exec_en	8651488	1			T1	92672		T3	23678		T4	146750
valid_exec_dis	281486554	1			T1	355272		T2	9174		T3	517192
invalid_exec_dis	30515757	1			T1	379238		T3	180454		T4	422808