| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1706468904 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3815535588 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2570037695 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1326243672 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2861749546 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4215155316 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4197413269 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2146547121 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2181612682 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2285414685 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1094996198 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3234956586 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.51360092 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4194852117 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1954353751 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1105057909 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1710855156 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2794042114 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2225804946 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.706822727 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1654882565 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2670345961 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.131243936 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3499569707 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1595748439 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2743605451 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1069445535 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1749852794 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2910887144 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2383979221 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.311865981 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1609486459 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2408323364 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4088292125 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1131290398 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3252541558 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.878498712 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.743190185 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.525959522 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2323796348 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.994660582 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3758078136 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1503019801 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1162935931 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.4180732292 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.464186167 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.568985476 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3211333902 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2763447245 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2523043151 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3059855898 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2479550182 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1254471649 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2031897092 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4261747107 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.768048625 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3833065567 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.621027528 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.51696065 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3048001972 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.871135736 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4116476065 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3074082613 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1317187109 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2789798416 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2242000591 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.919576716 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.537112038 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1999537615 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3530398075 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1510341074 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2502350950 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2070448497 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4093359337 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.420724239 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.853698615 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3097610019 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506238289 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.970848269 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1650990928 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3328131889 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1145000885 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.630572627 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3457124959 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2839285917 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2705865276 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2360968554 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.995078237 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4234739332 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.726839337 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2607165691 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2771924580 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.962548735 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1821451309 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1203018403 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.217596133 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1752807446 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3064682067 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1030282671 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.4232357408 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.418673512 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1521634017 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1798579622 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3220587750 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4014988121 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2108961896 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.434393923 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1294980727 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1600713183 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3964972248 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.240777324 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.724390202 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1733470697 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1117956405 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3143901884 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2768683535 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2930894139 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4174305426 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2716460414 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2367596305 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.630334779 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2854539698 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.801641459 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1789284158 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.359865402 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3546916526 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3726707093 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.3623852675 |
| /workspace/coverage/default/0.sram_ctrl_bijection.2988148293 |
| /workspace/coverage/default/0.sram_ctrl_executable.2623836770 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.108121078 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3814643781 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.4262499387 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.2486685656 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.1442614172 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2222901800 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1323575632 |
| /workspace/coverage/default/0.sram_ctrl_regwen.3911934791 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.3801244234 |
| /workspace/coverage/default/0.sram_ctrl_smoke.577593859 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2661507597 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3433033122 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1770902741 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2571482783 |
| /workspace/coverage/default/1.sram_ctrl_bijection.1168174380 |
| /workspace/coverage/default/1.sram_ctrl_executable.1975672470 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.1501549356 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.323775235 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2193680787 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.1152283517 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2896880058 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.643476442 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2439397558 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.665887058 |
| /workspace/coverage/default/1.sram_ctrl_regwen.2900539962 |
| /workspace/coverage/default/1.sram_ctrl_smoke.2092095079 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.145139518 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1513539536 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1090289940 |
| /workspace/coverage/default/10.sram_ctrl_bijection.1437029094 |
| /workspace/coverage/default/10.sram_ctrl_executable.765400056 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.2464405208 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3063034735 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3064644194 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.2687414841 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1623749444 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.3257830958 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3163432202 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1054055814 |
| /workspace/coverage/default/10.sram_ctrl_regwen.1995744621 |
| /workspace/coverage/default/10.sram_ctrl_smoke.3948056342 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.651376769 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.893617356 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.529780656 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3932014159 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.3366116642 |
| /workspace/coverage/default/11.sram_ctrl_bijection.3166588497 |
| /workspace/coverage/default/11.sram_ctrl_executable.2934654507 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.1550529081 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.559530147 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.338022587 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.2052256143 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1663980856 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3006710078 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3121813244 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2269743514 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2827599894 |
| /workspace/coverage/default/11.sram_ctrl_smoke.3274384413 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2650807285 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1472237127 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3142455123 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1857912242 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.2843642895 |
| /workspace/coverage/default/12.sram_ctrl_bijection.1720465282 |
| /workspace/coverage/default/12.sram_ctrl_executable.3419423155 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3789986854 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.1412054118 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1125807734 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.3695231009 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3481966596 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.3285498866 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1391263690 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.1469537854 |
| /workspace/coverage/default/12.sram_ctrl_regwen.2286633312 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1928950959 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2114607062 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1541995369 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4225445031 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3490946944 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2382140551 |
| /workspace/coverage/default/13.sram_ctrl_executable.2752705354 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.2647171417 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.3843019882 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.4142313126 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3765673346 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1822741231 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.2485885754 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.809696867 |
| /workspace/coverage/default/13.sram_ctrl_smoke.3985334645 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.943093668 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3189168907 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.857809158 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.316588057 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.4063769063 |
| /workspace/coverage/default/14.sram_ctrl_bijection.3976726548 |
| /workspace/coverage/default/14.sram_ctrl_executable.852711929 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.3536375198 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2296452475 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3702852480 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.968809275 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.1332672562 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.407531720 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2521257131 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.385703463 |
| /workspace/coverage/default/14.sram_ctrl_regwen.3546596206 |
| /workspace/coverage/default/14.sram_ctrl_smoke.3824667194 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3319711739 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.189636687 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1135653261 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.3171769784 |
| /workspace/coverage/default/15.sram_ctrl_bijection.2261784413 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.1824571211 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.3447225696 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1025031086 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.4019671768 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.4230615517 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.1787777585 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.3378070783 |
| /workspace/coverage/default/15.sram_ctrl_regwen.823523588 |
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| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1343974866 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.912112421 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.566089068 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.191584527 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1589895018 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3934083357 |
| /workspace/coverage/default/47.sram_ctrl_regwen.2586380437 |
| /workspace/coverage/default/47.sram_ctrl_smoke.1934933199 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.331552389 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.46945603 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.163907630 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2519993022 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.2330486660 |
| /workspace/coverage/default/48.sram_ctrl_bijection.4009522511 |
| /workspace/coverage/default/48.sram_ctrl_executable.2185207394 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.1606783666 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1861001265 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3457241063 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.652907761 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2197378088 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.42168715 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1315414377 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.240523001 |
| /workspace/coverage/default/48.sram_ctrl_regwen.3532302745 |
| /workspace/coverage/default/48.sram_ctrl_smoke.545431133 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.3476649784 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2668430507 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1911455075 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2004083179 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.2057200870 |
| /workspace/coverage/default/49.sram_ctrl_bijection.3728535950 |
| /workspace/coverage/default/49.sram_ctrl_executable.2331527496 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.1403569373 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2645505483 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.933901465 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.1008001695 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.371286198 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.58295778 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3705184530 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.662442195 |
| /workspace/coverage/default/49.sram_ctrl_regwen.3727711018 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3063831322 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1179591931 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1372385609 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4104003398 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.4249290465 |
| /workspace/coverage/default/5.sram_ctrl_bijection.3929784153 |
| /workspace/coverage/default/5.sram_ctrl_executable.1160769448 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3525097002 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.124392801 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3877211504 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.223302336 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.1461071457 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.938928179 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1173602479 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1999769401 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3758910912 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2680208056 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.1168505953 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3343914612 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1726628006 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1221316259 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.4173345198 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1647960995 |
| /workspace/coverage/default/6.sram_ctrl_executable.621588077 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.1685702353 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.82212292 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.116346938 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2838660494 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3509192789 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.2801987115 |
| /workspace/coverage/default/6.sram_ctrl_regwen.1703867774 |
| /workspace/coverage/default/6.sram_ctrl_smoke.3702578740 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.20233697 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3612590782 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.505907317 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2697798119 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2032134235 |
| /workspace/coverage/default/7.sram_ctrl_executable.852405330 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.2552991242 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2976378082 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.989069174 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.2317987872 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1806770651 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.4148936233 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2266109534 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.3123206674 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3214360924 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3644496611 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.1739596241 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2992503730 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3653029492 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2018451288 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.3874168870 |
| /workspace/coverage/default/8.sram_ctrl_bijection.3533680088 |
| /workspace/coverage/default/8.sram_ctrl_executable.1445116844 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.299856649 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.263126944 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2435763867 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.210237184 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2803231196 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.615779399 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3096652408 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3125078387 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1688509875 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3580220053 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.4200790568 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1290808042 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2678447366 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2119610045 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1689720041 |
| /workspace/coverage/default/9.sram_ctrl_bijection.1066815409 |
| /workspace/coverage/default/9.sram_ctrl_executable.3243906894 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3620929187 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.1107180944 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3177169170 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.2247974786 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.2582706645 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3556478303 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4072874571 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2824358195 |
| /workspace/coverage/default/9.sram_ctrl_regwen.740429072 |
| /workspace/coverage/default/9.sram_ctrl_smoke.2064474156 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.4121525407 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3472800616 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1493260586 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2551961870 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/32.sram_ctrl_regwen.3385678660 |
|
|
Mar 05 01:26:00 PM PST 24 |
Mar 05 01:46:20 PM PST 24 |
106370739995 ps |
| T2 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1062721454 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:25:45 PM PST 24 |
4426597270 ps |
| T3 |
/workspace/coverage/default/25.sram_ctrl_stress_all.3215395192 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 01:52:53 PM PST 24 |
29662679587 ps |
| T9 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.1498717643 |
|
|
Mar 05 01:26:03 PM PST 24 |
Mar 05 01:26:07 PM PST 24 |
2805063263 ps |
| T4 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1322135052 |
|
|
Mar 05 01:24:36 PM PST 24 |
Mar 05 02:53:03 PM PST 24 |
87922638865 ps |
| T10 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1584956302 |
|
|
Mar 05 01:24:19 PM PST 24 |
Mar 05 01:24:53 PM PST 24 |
1511716221 ps |
| T11 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.136449097 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:25:06 PM PST 24 |
1354861089 ps |
| T5 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.482245513 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:25:38 PM PST 24 |
1991275085 ps |
| T6 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3496585934 |
|
|
Mar 05 01:25:48 PM PST 24 |
Mar 05 01:26:09 PM PST 24 |
3154754266 ps |
| T12 |
/workspace/coverage/default/2.sram_ctrl_bijection.1942245764 |
|
|
Mar 05 01:24:18 PM PST 24 |
Mar 05 01:35:12 PM PST 24 |
11328636169 ps |
| T19 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.898082548 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:27:44 PM PST 24 |
18194778584 ps |
| T20 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3319711739 |
|
|
Mar 05 01:25:00 PM PST 24 |
Mar 05 01:26:40 PM PST 24 |
1292297616 ps |
| T13 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3933772800 |
|
|
Mar 05 01:25:26 PM PST 24 |
Mar 05 01:28:05 PM PST 24 |
41410255845 ps |
| T21 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.432065407 |
|
|
Mar 05 01:25:48 PM PST 24 |
Mar 05 01:26:05 PM PST 24 |
744924501 ps |
| T22 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1530809916 |
|
|
Mar 05 01:27:06 PM PST 24 |
Mar 05 01:28:09 PM PST 24 |
4327509442 ps |
| T17 |
/workspace/coverage/default/4.sram_ctrl_bijection.4193895903 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:37:12 PM PST 24 |
115871152068 ps |
| T23 |
/workspace/coverage/default/6.sram_ctrl_executable.621588077 |
|
|
Mar 05 01:24:47 PM PST 24 |
Mar 05 01:25:10 PM PST 24 |
3637195426 ps |
| T66 |
/workspace/coverage/default/10.sram_ctrl_smoke.3948056342 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:24:50 PM PST 24 |
799240667 ps |
| T18 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1461071457 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:31:18 PM PST 24 |
6200618036 ps |
| T16 |
/workspace/coverage/default/29.sram_ctrl_bijection.2842396439 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 01:36:56 PM PST 24 |
832882775387 ps |
| T14 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1822741231 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:36:37 PM PST 24 |
13723144430 ps |
| T94 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.733096911 |
|
|
Mar 05 01:27:14 PM PST 24 |
Mar 05 01:28:55 PM PST 24 |
3178786712 ps |
| T85 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1791264984 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:33:37 PM PST 24 |
39284573898 ps |
| T15 |
/workspace/coverage/default/47.sram_ctrl_executable.812449930 |
|
|
Mar 05 01:27:40 PM PST 24 |
Mar 05 01:34:14 PM PST 24 |
59029961640 ps |
| T129 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.643760824 |
|
|
Mar 05 01:24:52 PM PST 24 |
Mar 05 01:25:00 PM PST 24 |
718625422 ps |
| T130 |
/workspace/coverage/default/1.sram_ctrl_bijection.1168174380 |
|
|
Mar 05 01:24:15 PM PST 24 |
Mar 05 02:02:27 PM PST 24 |
127232988714 ps |
| T29 |
/workspace/coverage/default/40.sram_ctrl_alert_test.2983692323 |
|
|
Mar 05 01:26:44 PM PST 24 |
Mar 05 01:26:45 PM PST 24 |
20965419 ps |
| T131 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.108777454 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:25:37 PM PST 24 |
725327804 ps |
| T86 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3585601441 |
|
|
Mar 05 01:25:40 PM PST 24 |
Mar 05 01:29:02 PM PST 24 |
8444453244 ps |
| T132 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2770107014 |
|
|
Mar 05 01:27:15 PM PST 24 |
Mar 05 01:29:32 PM PST 24 |
799142705 ps |
| T32 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3378070783 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:25:09 PM PST 24 |
1301694509 ps |
| T87 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2861179452 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:28:45 PM PST 24 |
2964399382 ps |
| T65 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2429709495 |
|
|
Mar 05 01:26:38 PM PST 24 |
Mar 05 01:27:52 PM PST 24 |
2359595894 ps |
| T30 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3773992099 |
|
|
Mar 05 01:26:38 PM PST 24 |
Mar 05 01:26:39 PM PST 24 |
12194727 ps |
| T7 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1824571211 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:30:55 PM PST 24 |
45004337644 ps |
| T51 |
/workspace/coverage/default/27.sram_ctrl_regwen.63413001 |
|
|
Mar 05 01:25:24 PM PST 24 |
Mar 05 01:37:08 PM PST 24 |
9217817248 ps |
| T88 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2575963321 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:32:33 PM PST 24 |
19109640635 ps |
| T133 |
/workspace/coverage/default/22.sram_ctrl_smoke.364258383 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:25:21 PM PST 24 |
554024711 ps |
| T89 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3705184530 |
|
|
Mar 05 01:27:49 PM PST 24 |
Mar 05 01:35:14 PM PST 24 |
18572319055 ps |
| T44 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1290808042 |
|
|
Mar 05 01:24:40 PM PST 24 |
Mar 05 01:25:21 PM PST 24 |
4633298598 ps |
| T134 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2486685656 |
|
|
Mar 05 01:24:15 PM PST 24 |
Mar 05 01:41:38 PM PST 24 |
62176054684 ps |
| T45 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3343914612 |
|
|
Mar 05 01:24:31 PM PST 24 |
Mar 05 01:24:39 PM PST 24 |
394966987 ps |
| T46 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1179591931 |
|
|
Mar 05 01:27:53 PM PST 24 |
Mar 05 01:28:11 PM PST 24 |
571194548 ps |
| T124 |
/workspace/coverage/default/41.sram_ctrl_executable.2823459975 |
|
|
Mar 05 01:26:55 PM PST 24 |
Mar 05 01:44:23 PM PST 24 |
8362796664 ps |
| T135 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2896880058 |
|
|
Mar 05 01:24:23 PM PST 24 |
Mar 05 01:38:59 PM PST 24 |
17530939305 ps |
| T136 |
/workspace/coverage/default/20.sram_ctrl_partial_access.4254319997 |
|
|
Mar 05 01:25:10 PM PST 24 |
Mar 05 01:27:07 PM PST 24 |
3991756989 ps |
| T27 |
/workspace/coverage/default/23.sram_ctrl_executable.1251732219 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:32:55 PM PST 24 |
20729362669 ps |
| T28 |
/workspace/coverage/default/1.sram_ctrl_regwen.2900539962 |
|
|
Mar 05 01:24:19 PM PST 24 |
Mar 05 01:24:36 PM PST 24 |
2552382350 ps |
| T137 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1195582287 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:25:52 PM PST 24 |
3201820225 ps |
| T138 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2874057014 |
|
|
Mar 05 01:26:07 PM PST 24 |
Mar 05 01:28:15 PM PST 24 |
9809445216 ps |
| T47 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1097535053 |
|
|
Mar 05 01:25:06 PM PST 24 |
Mar 05 01:26:39 PM PST 24 |
13740726806 ps |
| T139 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.2383825171 |
|
|
Mar 05 01:26:28 PM PST 24 |
Mar 05 01:28:05 PM PST 24 |
3053320001 ps |
| T52 |
/workspace/coverage/default/23.sram_ctrl_regwen.3482621699 |
|
|
Mar 05 01:25:16 PM PST 24 |
Mar 05 01:41:05 PM PST 24 |
6618022876 ps |
| T140 |
/workspace/coverage/default/20.sram_ctrl_smoke.2944790439 |
|
|
Mar 05 01:25:04 PM PST 24 |
Mar 05 01:25:08 PM PST 24 |
358511408 ps |
| T141 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1787777585 |
|
|
Mar 05 01:25:08 PM PST 24 |
Mar 05 01:25:22 PM PST 24 |
909337973 ps |
| T142 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.188573174 |
|
|
Mar 05 01:25:04 PM PST 24 |
Mar 05 01:32:59 PM PST 24 |
7013434484 ps |
| T8 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3203010569 |
|
|
Mar 05 01:26:00 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
16472523796 ps |
| T53 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.59268216 |
|
|
Mar 05 01:25:17 PM PST 24 |
Mar 05 01:33:32 PM PST 24 |
40477466323 ps |
| T90 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1565493325 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:29:23 PM PST 24 |
4996962960 ps |
| T143 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.3934083357 |
|
|
Mar 05 01:27:39 PM PST 24 |
Mar 05 01:27:42 PM PST 24 |
360811438 ps |
| T144 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2704788141 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:25:45 PM PST 24 |
1347235642 ps |
| T91 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3455005907 |
|
|
Mar 05 01:27:17 PM PST 24 |
Mar 05 01:31:40 PM PST 24 |
41785950400 ps |
| T126 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2312327079 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:30:33 PM PST 24 |
70660125207 ps |
| T145 |
/workspace/coverage/default/12.sram_ctrl_bijection.1720465282 |
|
|
Mar 05 01:24:45 PM PST 24 |
Mar 05 01:54:57 PM PST 24 |
979519604710 ps |
| T54 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3620929187 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:25:30 PM PST 24 |
6317854561 ps |
| T73 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1472822440 |
|
|
Mar 05 01:24:22 PM PST 24 |
Mar 05 01:26:56 PM PST 24 |
72266578121 ps |
| T146 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.1443753446 |
|
|
Mar 05 01:25:24 PM PST 24 |
Mar 05 01:46:47 PM PST 24 |
74743600938 ps |
| T74 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2963088783 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 01:28:22 PM PST 24 |
1599684878 ps |
| T147 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.4272729050 |
|
|
Mar 05 01:27:23 PM PST 24 |
Mar 05 01:27:30 PM PST 24 |
821740477 ps |
| T148 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1421570849 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:34:25 PM PST 24 |
11738239492 ps |
| T149 |
/workspace/coverage/default/39.sram_ctrl_bijection.3359302869 |
|
|
Mar 05 01:26:26 PM PST 24 |
Mar 05 01:43:09 PM PST 24 |
221416986079 ps |
| T150 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2947924069 |
|
|
Mar 05 01:25:19 PM PST 24 |
Mar 05 01:27:51 PM PST 24 |
36945068522 ps |
| T128 |
/workspace/coverage/default/12.sram_ctrl_regwen.2286633312 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:41:26 PM PST 24 |
3483277278 ps |
| T151 |
/workspace/coverage/default/14.sram_ctrl_partial_access.407531720 |
|
|
Mar 05 01:24:52 PM PST 24 |
Mar 05 01:25:11 PM PST 24 |
1391192458 ps |
| T152 |
/workspace/coverage/default/9.sram_ctrl_bijection.1066815409 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:33:45 PM PST 24 |
46556872217 ps |
| T153 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3080299786 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:26:32 PM PST 24 |
3127183258 ps |
| T154 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.3246138346 |
|
|
Mar 05 01:25:21 PM PST 24 |
Mar 05 01:49:06 PM PST 24 |
23530899239 ps |
| T122 |
/workspace/coverage/default/13.sram_ctrl_executable.2752705354 |
|
|
Mar 05 01:24:51 PM PST 24 |
Mar 05 01:46:49 PM PST 24 |
8160405230 ps |
| T155 |
/workspace/coverage/default/10.sram_ctrl_bijection.1437029094 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:57:30 PM PST 24 |
234640956800 ps |
| T109 |
/workspace/coverage/default/40.sram_ctrl_stress_all.273759000 |
|
|
Mar 05 01:26:46 PM PST 24 |
Mar 05 02:26:30 PM PST 24 |
64230957669 ps |
| T156 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.47817300 |
|
|
Mar 05 01:25:09 PM PST 24 |
Mar 05 01:25:31 PM PST 24 |
1697281609 ps |
| T157 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2645505483 |
|
|
Mar 05 01:27:52 PM PST 24 |
Mar 05 01:28:11 PM PST 24 |
7753133598 ps |
| T127 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2167578966 |
|
|
Mar 05 01:26:06 PM PST 24 |
Mar 05 01:31:22 PM PST 24 |
15824340996 ps |
| T75 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1255780851 |
|
|
Mar 05 01:25:55 PM PST 24 |
Mar 05 01:27:15 PM PST 24 |
2800607658 ps |
| T158 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.124392801 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:25:00 PM PST 24 |
5885539344 ps |
| T159 |
/workspace/coverage/default/49.sram_ctrl_bijection.3728535950 |
|
|
Mar 05 01:27:45 PM PST 24 |
Mar 05 02:02:17 PM PST 24 |
29537543008 ps |
| T160 |
/workspace/coverage/default/20.sram_ctrl_executable.2573661316 |
|
|
Mar 05 01:25:10 PM PST 24 |
Mar 05 01:35:05 PM PST 24 |
7470777132 ps |
| T125 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1673073244 |
|
|
Mar 05 01:25:48 PM PST 24 |
Mar 05 03:22:55 PM PST 24 |
253061216200 ps |
| T161 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.4292863065 |
|
|
Mar 05 01:27:18 PM PST 24 |
Mar 05 01:32:35 PM PST 24 |
40142536686 ps |
| T162 |
/workspace/coverage/default/3.sram_ctrl_executable.1905573619 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:45:14 PM PST 24 |
91988333449 ps |
| T48 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2710238154 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 01:25:18 PM PST 24 |
3047193983 ps |
| T76 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2992720400 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:27:04 PM PST 24 |
3338267562 ps |
| T163 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.2565670972 |
|
|
Mar 05 01:27:31 PM PST 24 |
Mar 05 01:29:33 PM PST 24 |
2042268739 ps |
| T164 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2364152634 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:26:24 PM PST 24 |
3951607350 ps |
| T107 |
/workspace/coverage/default/7.sram_ctrl_stress_all.1739596241 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 02:44:01 PM PST 24 |
1319510314337 ps |
| T165 |
/workspace/coverage/default/1.sram_ctrl_smoke.2092095079 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:24:33 PM PST 24 |
3252489930 ps |
| T166 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3717746396 |
|
|
Mar 05 01:26:03 PM PST 24 |
Mar 05 01:28:49 PM PST 24 |
13593314434 ps |
| T49 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3279588338 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:28:18 PM PST 24 |
1512388118 ps |
| T167 |
/workspace/coverage/default/30.sram_ctrl_bijection.1100014777 |
|
|
Mar 05 01:25:38 PM PST 24 |
Mar 05 01:37:54 PM PST 24 |
23609181564 ps |
| T168 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.963983518 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:25:14 PM PST 24 |
692116440 ps |
| T169 |
/workspace/coverage/default/15.sram_ctrl_smoke.2812067138 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:25:49 PM PST 24 |
1081104249 ps |
| T31 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3518939623 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:25:12 PM PST 24 |
14921664 ps |
| T170 |
/workspace/coverage/default/30.sram_ctrl_executable.431317721 |
|
|
Mar 05 01:25:48 PM PST 24 |
Mar 05 01:40:42 PM PST 24 |
35819628951 ps |
| T77 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1853432922 |
|
|
Mar 05 01:27:29 PM PST 24 |
Mar 05 01:29:51 PM PST 24 |
17451952569 ps |
| T171 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1855882677 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:29:18 PM PST 24 |
4793003590 ps |
| T50 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.893617356 |
|
|
Mar 05 01:24:38 PM PST 24 |
Mar 05 01:26:57 PM PST 24 |
1732545385 ps |
| T172 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.125659581 |
|
|
Mar 05 01:24:28 PM PST 24 |
Mar 05 01:38:44 PM PST 24 |
33882950394 ps |
| T173 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2004495589 |
|
|
Mar 05 01:25:56 PM PST 24 |
Mar 05 01:30:55 PM PST 24 |
22747588385 ps |
| T78 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.1767497265 |
|
|
Mar 05 01:25:31 PM PST 24 |
Mar 05 01:26:37 PM PST 24 |
2974122802 ps |
| T174 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.2638068687 |
|
|
Mar 05 01:26:07 PM PST 24 |
Mar 05 01:27:09 PM PST 24 |
1230035686 ps |
| T175 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.989069174 |
|
|
Mar 05 01:24:29 PM PST 24 |
Mar 05 01:25:44 PM PST 24 |
2970877279 ps |
| T176 |
/workspace/coverage/default/14.sram_ctrl_alert_test.4063769063 |
|
|
Mar 05 01:25:05 PM PST 24 |
Mar 05 01:25:06 PM PST 24 |
43130304 ps |
| T177 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2605707592 |
|
|
Mar 05 01:25:31 PM PST 24 |
Mar 05 01:30:35 PM PST 24 |
19177899736 ps |
| T178 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.3773075803 |
|
|
Mar 05 01:26:26 PM PST 24 |
Mar 05 01:26:30 PM PST 24 |
349106554 ps |
| T108 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3789986854 |
|
|
Mar 05 01:24:49 PM PST 24 |
Mar 05 01:26:16 PM PST 24 |
5618146599 ps |
| T179 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2779920120 |
|
|
Mar 05 01:25:17 PM PST 24 |
Mar 05 01:25:18 PM PST 24 |
27776077 ps |
| T180 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.698936253 |
|
|
Mar 05 01:26:32 PM PST 24 |
Mar 05 01:34:37 PM PST 24 |
16259708924 ps |
| T181 |
/workspace/coverage/default/37.sram_ctrl_bijection.1177345281 |
|
|
Mar 05 01:26:21 PM PST 24 |
Mar 05 01:55:26 PM PST 24 |
53185340699 ps |
| T182 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3893680851 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:27:39 PM PST 24 |
1540304753 ps |
| T183 |
/workspace/coverage/default/42.sram_ctrl_bijection.4223185310 |
|
|
Mar 05 01:26:55 PM PST 24 |
Mar 05 01:44:42 PM PST 24 |
184405599636 ps |
| T184 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2766999356 |
|
|
Mar 05 01:27:15 PM PST 24 |
Mar 05 01:27:18 PM PST 24 |
361959628 ps |
| T185 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4225445031 |
|
|
Mar 05 01:24:36 PM PST 24 |
Mar 05 01:24:42 PM PST 24 |
704868331 ps |
| T186 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1372385609 |
|
|
Mar 05 01:27:47 PM PST 24 |
Mar 05 01:29:37 PM PST 24 |
4314373065 ps |
| T123 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2009134845 |
|
|
Mar 05 01:24:57 PM PST 24 |
Mar 05 03:35:08 PM PST 24 |
361637236835 ps |
| T187 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3537753223 |
|
|
Mar 05 01:26:43 PM PST 24 |
Mar 05 01:30:28 PM PST 24 |
4534676106 ps |
| T188 |
/workspace/coverage/default/8.sram_ctrl_alert_test.3874168870 |
|
|
Mar 05 01:24:27 PM PST 24 |
Mar 05 01:24:28 PM PST 24 |
11036795 ps |
| T189 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3246993476 |
|
|
Mar 05 01:26:50 PM PST 24 |
Mar 05 01:29:15 PM PST 24 |
4707652858 ps |
| T190 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1173602479 |
|
|
Mar 05 01:24:46 PM PST 24 |
Mar 05 01:32:18 PM PST 24 |
77180063620 ps |
| T191 |
/workspace/coverage/default/46.sram_ctrl_regwen.1903367175 |
|
|
Mar 05 01:27:30 PM PST 24 |
Mar 05 01:36:31 PM PST 24 |
11445457645 ps |
| T192 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.612736428 |
|
|
Mar 05 01:27:31 PM PST 24 |
Mar 05 01:27:40 PM PST 24 |
494855744 ps |
| T193 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3785840089 |
|
|
Mar 05 01:25:28 PM PST 24 |
Mar 05 01:25:28 PM PST 24 |
38918137 ps |
| T194 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.143296290 |
|
|
Mar 05 01:25:47 PM PST 24 |
Mar 05 01:25:50 PM PST 24 |
1350394989 ps |
| T195 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2558386462 |
|
|
Mar 05 01:27:23 PM PST 24 |
Mar 05 01:32:05 PM PST 24 |
12810197964 ps |
| T196 |
/workspace/coverage/default/28.sram_ctrl_executable.4046116861 |
|
|
Mar 05 01:25:36 PM PST 24 |
Mar 05 01:34:51 PM PST 24 |
19884464226 ps |
| T197 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1008001695 |
|
|
Mar 05 01:27:55 PM PST 24 |
Mar 05 01:32:59 PM PST 24 |
39729271951 ps |
| T198 |
/workspace/coverage/default/27.sram_ctrl_stress_all.833531639 |
|
|
Mar 05 01:25:36 PM PST 24 |
Mar 05 01:42:53 PM PST 24 |
37078969249 ps |
| T199 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1521053535 |
|
|
Mar 05 01:26:31 PM PST 24 |
Mar 05 01:27:49 PM PST 24 |
4537438103 ps |
| T200 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1180082625 |
|
|
Mar 05 01:25:04 PM PST 24 |
Mar 05 01:27:42 PM PST 24 |
9403735314 ps |
| T201 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3006710078 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:25:12 PM PST 24 |
516569788 ps |
| T202 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1587860733 |
|
|
Mar 05 01:25:19 PM PST 24 |
Mar 05 01:35:21 PM PST 24 |
50779817622 ps |
| T203 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3541821718 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:25:17 PM PST 24 |
1397715337 ps |
| T204 |
/workspace/coverage/default/2.sram_ctrl_executable.2070079575 |
|
|
Mar 05 01:24:43 PM PST 24 |
Mar 05 01:49:23 PM PST 24 |
117667789984 ps |
| T205 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.2435763867 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:26:27 PM PST 24 |
22149272493 ps |
| T206 |
/workspace/coverage/default/31.sram_ctrl_executable.906764133 |
|
|
Mar 05 01:25:47 PM PST 24 |
Mar 05 01:36:26 PM PST 24 |
63227635165 ps |
| T207 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.764698991 |
|
|
Mar 05 01:25:22 PM PST 24 |
Mar 05 01:32:02 PM PST 24 |
298128174695 ps |
| T208 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1742090822 |
|
|
Mar 05 01:25:59 PM PST 24 |
Mar 05 01:26:20 PM PST 24 |
1898541933 ps |
| T209 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.82212292 |
|
|
Mar 05 01:24:36 PM PST 24 |
Mar 05 01:27:09 PM PST 24 |
17352562937 ps |
| T210 |
/workspace/coverage/default/7.sram_ctrl_smoke.3644496611 |
|
|
Mar 05 01:24:35 PM PST 24 |
Mar 05 01:24:50 PM PST 24 |
1939610570 ps |
| T211 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3125078387 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:24:30 PM PST 24 |
4186378999 ps |
| T98 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2338495854 |
|
|
Mar 05 01:26:36 PM PST 24 |
Mar 05 01:27:47 PM PST 24 |
1249699913 ps |
| T212 |
/workspace/coverage/default/28.sram_ctrl_smoke.2295438150 |
|
|
Mar 05 01:25:36 PM PST 24 |
Mar 05 01:28:24 PM PST 24 |
15284799751 ps |
| T213 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.176269585 |
|
|
Mar 05 01:26:55 PM PST 24 |
Mar 05 01:32:36 PM PST 24 |
6296551519 ps |
| T214 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2566651912 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:26:00 PM PST 24 |
5028816512 ps |
| T215 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3942777411 |
|
|
Mar 05 01:25:26 PM PST 24 |
Mar 05 01:31:05 PM PST 24 |
30075489127 ps |
| T216 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.134206039 |
|
|
Mar 05 01:26:59 PM PST 24 |
Mar 05 01:32:03 PM PST 24 |
9338554260 ps |
| T217 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1555784601 |
|
|
Mar 05 01:25:31 PM PST 24 |
Mar 05 01:25:42 PM PST 24 |
338916355 ps |
| T218 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1760491647 |
|
|
Mar 05 01:25:38 PM PST 24 |
Mar 05 01:29:50 PM PST 24 |
55165576535 ps |
| T219 |
/workspace/coverage/default/21.sram_ctrl_smoke.502211043 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:26:07 PM PST 24 |
1080200784 ps |
| T220 |
/workspace/coverage/default/28.sram_ctrl_bijection.4022104769 |
|
|
Mar 05 01:25:36 PM PST 24 |
Mar 05 01:52:48 PM PST 24 |
118909830092 ps |
| T221 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1075445539 |
|
|
Mar 05 01:27:15 PM PST 24 |
Mar 05 01:29:40 PM PST 24 |
6909519438 ps |
| T222 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.2357085300 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:25:54 PM PST 24 |
718536705 ps |
| T223 |
/workspace/coverage/default/5.sram_ctrl_bijection.3929784153 |
|
|
Mar 05 01:24:45 PM PST 24 |
Mar 05 02:01:54 PM PST 24 |
97643431984 ps |
| T224 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.897963004 |
|
|
Mar 05 01:27:24 PM PST 24 |
Mar 05 01:27:45 PM PST 24 |
950305469 ps |
| T225 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1105005503 |
|
|
Mar 05 01:26:58 PM PST 24 |
Mar 05 01:27:07 PM PST 24 |
895626610 ps |
| T226 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1995098916 |
|
|
Mar 05 01:27:33 PM PST 24 |
Mar 05 01:29:08 PM PST 24 |
5743075642 ps |
| T227 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.950807958 |
|
|
Mar 05 01:24:21 PM PST 24 |
Mar 05 01:24:24 PM PST 24 |
432460069 ps |
| T228 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3135207049 |
|
|
Mar 05 01:24:26 PM PST 24 |
Mar 05 01:27:56 PM PST 24 |
13412774959 ps |
| T229 |
/workspace/coverage/default/0.sram_ctrl_regwen.3911934791 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:27:31 PM PST 24 |
3854983670 ps |
| T230 |
/workspace/coverage/default/18.sram_ctrl_regwen.1709080616 |
|
|
Mar 05 01:25:03 PM PST 24 |
Mar 05 01:35:20 PM PST 24 |
11112578445 ps |
| T231 |
/workspace/coverage/default/11.sram_ctrl_executable.2934654507 |
|
|
Mar 05 01:24:45 PM PST 24 |
Mar 05 01:43:37 PM PST 24 |
66872964900 ps |
| T232 |
/workspace/coverage/default/49.sram_ctrl_executable.2331527496 |
|
|
Mar 05 01:27:53 PM PST 24 |
Mar 05 01:38:02 PM PST 24 |
21141758173 ps |
| T233 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1995550002 |
|
|
Mar 05 01:25:32 PM PST 24 |
Mar 05 01:26:33 PM PST 24 |
6282652395 ps |
| T234 |
/workspace/coverage/default/25.sram_ctrl_regwen.364746176 |
|
|
Mar 05 01:25:15 PM PST 24 |
Mar 05 01:31:26 PM PST 24 |
10934669745 ps |
| T235 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1529611393 |
|
|
Mar 05 01:25:01 PM PST 24 |
Mar 05 01:25:03 PM PST 24 |
21297414 ps |
| T236 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.4104003398 |
|
|
Mar 05 01:27:54 PM PST 24 |
Mar 05 01:28:43 PM PST 24 |
2974424540 ps |
| T237 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2679294321 |
|
|
Mar 05 01:26:42 PM PST 24 |
Mar 05 01:26:50 PM PST 24 |
2511384895 ps |
| T238 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1423659245 |
|
|
Mar 05 01:26:20 PM PST 24 |
Mar 05 01:31:43 PM PST 24 |
62914508449 ps |
| T239 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.353293065 |
|
|
Mar 05 01:24:59 PM PST 24 |
Mar 05 01:27:00 PM PST 24 |
771157624 ps |
| T240 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.931256118 |
|
|
Mar 05 01:25:30 PM PST 24 |
Mar 05 01:29:02 PM PST 24 |
3880218252 ps |
| T241 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1959736419 |
|
|
Mar 05 01:26:50 PM PST 24 |
Mar 05 01:27:18 PM PST 24 |
2829815600 ps |
| T242 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1066007060 |
|
|
Mar 05 01:25:25 PM PST 24 |
Mar 05 01:27:50 PM PST 24 |
2587085156 ps |
| T243 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3657648405 |
|
|
Mar 05 01:25:36 PM PST 24 |
Mar 05 01:25:37 PM PST 24 |
30624071 ps |
| T244 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2247443189 |
|
|
Mar 05 01:26:20 PM PST 24 |
Mar 05 01:26:36 PM PST 24 |
1069391286 ps |
| T245 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3064644194 |
|
|
Mar 05 01:24:32 PM PST 24 |
Mar 05 01:27:02 PM PST 24 |
4510931848 ps |
| T246 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.189636687 |
|
|
Mar 05 01:24:47 PM PST 24 |
Mar 05 01:27:29 PM PST 24 |
5162210057 ps |
| T247 |
/workspace/coverage/default/21.sram_ctrl_regwen.1740774737 |
|
|
Mar 05 01:25:22 PM PST 24 |
Mar 05 01:36:07 PM PST 24 |
33764040985 ps |
| T248 |
/workspace/coverage/default/47.sram_ctrl_stress_all.331552389 |
|
|
Mar 05 01:27:43 PM PST 24 |
Mar 05 03:51:29 PM PST 24 |
820294200420 ps |
| T249 |
/workspace/coverage/default/19.sram_ctrl_alert_test.2212096872 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 01:25:14 PM PST 24 |
14249397 ps |
| T250 |
/workspace/coverage/default/39.sram_ctrl_executable.961620120 |
|
|
Mar 05 01:26:38 PM PST 24 |
Mar 05 01:39:54 PM PST 24 |
22206171278 ps |
| T251 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2676348338 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:28:17 PM PST 24 |
12611238122 ps |
| T252 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2290167909 |
|
|
Mar 05 01:26:48 PM PST 24 |
Mar 05 01:26:51 PM PST 24 |
1341593719 ps |
| T253 |
/workspace/coverage/default/14.sram_ctrl_regwen.3546596206 |
|
|
Mar 05 01:25:07 PM PST 24 |
Mar 05 01:27:33 PM PST 24 |
5484945131 ps |
| T254 |
/workspace/coverage/default/27.sram_ctrl_smoke.1319993668 |
|
|
Mar 05 01:25:23 PM PST 24 |
Mar 05 01:25:47 PM PST 24 |
2856349158 ps |
| T255 |
/workspace/coverage/default/40.sram_ctrl_executable.2951767482 |
|
|
Mar 05 01:26:43 PM PST 24 |
Mar 05 01:42:16 PM PST 24 |
37899057323 ps |
| T256 |
/workspace/coverage/default/24.sram_ctrl_smoke.692894 |
|
|
Mar 05 01:25:20 PM PST 24 |
Mar 05 01:25:29 PM PST 24 |
1576874419 ps |
| T257 |
/workspace/coverage/default/21.sram_ctrl_partial_access.2387465719 |
|
|
Mar 05 01:25:12 PM PST 24 |
Mar 05 01:25:37 PM PST 24 |
1703382085 ps |
| T258 |
/workspace/coverage/default/25.sram_ctrl_smoke.3774639602 |
|
|
Mar 05 01:25:16 PM PST 24 |
Mar 05 01:26:42 PM PST 24 |
893418606 ps |
| T259 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2652563445 |
|
|
Mar 05 01:26:09 PM PST 24 |
Mar 05 01:26:42 PM PST 24 |
2332558156 ps |
| T260 |
/workspace/coverage/default/48.sram_ctrl_bijection.4009522511 |
|
|
Mar 05 01:27:41 PM PST 24 |
Mar 05 02:08:15 PM PST 24 |
106626444833 ps |
| T261 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1414387990 |
|
|
Mar 05 01:26:28 PM PST 24 |
Mar 05 01:32:49 PM PST 24 |
34612849307 ps |
| T262 |
/workspace/coverage/default/47.sram_ctrl_bijection.1725927411 |
|
|
Mar 05 01:27:33 PM PST 24 |
Mar 05 02:00:28 PM PST 24 |
99552964977 ps |
| T263 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1326141849 |
|
|
Mar 05 01:25:06 PM PST 24 |
Mar 05 01:27:21 PM PST 24 |
4300268037 ps |
| T264 |
/workspace/coverage/default/35.sram_ctrl_regwen.1960680711 |
|
|
Mar 05 01:26:09 PM PST 24 |
Mar 05 01:42:30 PM PST 24 |
65200898759 ps |
| T265 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.652907761 |
|
|
Mar 05 01:27:48 PM PST 24 |
Mar 05 01:32:52 PM PST 24 |
105979280396 ps |
| T266 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2574930362 |
|
|
Mar 05 01:25:14 PM PST 24 |
Mar 05 01:25:40 PM PST 24 |
3738701217 ps |
| T267 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2325519462 |
|
|
Mar 05 01:27:17 PM PST 24 |
Mar 05 01:33:55 PM PST 24 |
32756305220 ps |
| T99 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1223775611 |
|
|
Mar 05 01:26:29 PM PST 24 |
Mar 05 01:26:44 PM PST 24 |
590890984 ps |
| T268 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2559533952 |
|
|
Mar 05 01:24:23 PM PST 24 |
Mar 05 01:29:30 PM PST 24 |
21073813602 ps |
| T269 |
/workspace/coverage/default/24.sram_ctrl_stress_all.861821838 |
|
|
Mar 05 01:25:20 PM PST 24 |
Mar 05 01:51:41 PM PST 24 |
37548657355 ps |
| T270 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1999769401 |
|
|
Mar 05 01:24:36 PM PST 24 |
Mar 05 01:24:40 PM PST 24 |
3411073295 ps |
| T271 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3478950929 |
|
|
Mar 05 01:24:24 PM PST 24 |
Mar 05 01:28:30 PM PST 24 |
4072661938 ps |
| T272 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2317987872 |
|
|
Mar 05 01:24:37 PM PST 24 |
Mar 05 01:27:00 PM PST 24 |
13769562395 ps |
| T273 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2035572825 |
|
|
Mar 05 01:26:18 PM PST 24 |
Mar 05 01:31:45 PM PST 24 |
22345412246 ps |
| T274 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3525097002 |
|
|
Mar 05 01:24:33 PM PST 24 |
Mar 05 01:25:44 PM PST 24 |
4267507541 ps |
| T275 |
/workspace/coverage/default/15.sram_ctrl_stress_all.96339213 |
|
|
Mar 05 01:25:02 PM PST 24 |
Mar 05 03:02:42 PM PST 24 |
66997068511 ps |
| T276 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2496742966 |
|
|
Mar 05 01:26:20 PM PST 24 |
Mar 05 01:33:54 PM PST 24 |
150945486652 ps |
| T277 |
/workspace/coverage/default/20.sram_ctrl_bijection.2975434735 |
|
|
Mar 05 01:25:11 PM PST 24 |
Mar 05 01:58:18 PM PST 24 |
838545540598 ps |
| T278 |
/workspace/coverage/default/16.sram_ctrl_bijection.3731432070 |
|
|
Mar 05 01:25:08 PM PST 24 |
Mar 05 01:43:58 PM PST 24 |
66950218997 ps |
| T279 |
/workspace/coverage/default/38.sram_ctrl_regwen.102525988 |
|
|
Mar 05 01:26:28 PM PST 24 |
Mar 05 01:30:09 PM PST 24 |
4551658821 ps |
| T280 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3433033122 |
|
|
Mar 05 01:24:21 PM PST 24 |
Mar 05 01:26:50 PM PST 24 |
5738890569 ps |
| T281 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1832280524 |
|
|
Mar 05 01:26:27 PM PST 24 |
Mar 05 01:26:38 PM PST 24 |
584904468 ps |
| T282 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1125807734 |
|
|
Mar 05 01:24:55 PM PST 24 |
Mar 05 01:26:10 PM PST 24 |
7835234968 ps |
| T283 |
/workspace/coverage/default/22.sram_ctrl_stress_all.1731379170 |
|
|
Mar 05 01:25:13 PM PST 24 |
Mar 05 02:44:04 PM PST 24 |
280414554885 ps |
| T284 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3509192789 |
|
|
Mar 05 01:24:50 PM PST 24 |
Mar 05 01:27:11 PM PST 24 |
9860196061 ps |
| T285 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2943884039 |
|
|
Mar 05 01:26:53 PM PST 24 |
Mar 05 01:41:42 PM PST 24 |
51452952309 ps |
| T286 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2494498874 |
|
|
Mar 05 01:25:04 PM PST 24 |
Mar 05 01:25:13 PM PST 24 |
5174046127 ps |
| T287 |
/workspace/coverage/default/42.sram_ctrl_executable.2905560152 |
|
|
Mar 05 01:26:58 PM PST 24 |
Mar 05 01:44:44 PM PST 24 |
25822307375 ps |
| T288 |
/workspace/coverage/default/30.sram_ctrl_alert_test.2163559993 |
|
|
Mar 05 01:25:49 PM PST 24 |
Mar 05 01:25:49 PM PST 24 |
29180002 ps |
| T289 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.2729648184 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:33:27 PM PST 24 |
24224522475 ps |
| T290 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.820272475 |
|
|
Mar 05 01:25:08 PM PST 24 |
Mar 05 01:36:11 PM PST 24 |
49093686601 ps |
| T24 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3719809750 |
|
|
Mar 05 01:24:30 PM PST 24 |
Mar 05 01:24:33 PM PST 24 |
456941704 ps |
| T35 |
/workspace/coverage/default/33.sram_ctrl_regwen.3288944906 |
|
|
Mar 05 01:25:57 PM PST 24 |
Mar 05 01:37:33 PM PST 24 |
62680581989 ps |
| T36 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.4142313126 |
|
|
Mar 05 01:24:54 PM PST 24 |
Mar 05 01:27:12 PM PST 24 |
20374212472 ps |
| T37 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1883768048 |
|
|
Mar 05 01:27:16 PM PST 24 |
Mar 05 01:28:51 PM PST 24 |
6687068456 ps |
| T38 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.1326595223 |
|
|
Mar 05 01:25:58 PM PST 24 |
Mar 05 01:31:20 PM PST 24 |
86001580907 ps |
| T39 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1403569373 |
|
|
Mar 05 01:27:51 PM PST 24 |
Mar 05 01:29:06 PM PST 24 |
5326517144 ps |
| T40 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3177169170 |
|
|
Mar 05 01:24:46 PM PST 24 |
Mar 05 01:25:57 PM PST 24 |
2500344143 ps |
| T41 |
/workspace/coverage/default/10.sram_ctrl_stress_all.651376769 |
|
|
Mar 05 01:24:45 PM PST 24 |
Mar 05 02:12:41 PM PST 24 |
41995062957 ps |
| T42 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.955174317 |
|
|
Mar 05 01:27:00 PM PST 24 |
Mar 05 01:29:10 PM PST 24 |
1602287753 ps |
| T43 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1894144503 |
|
|
Mar 05 01:26:46 PM PST 24 |
Mar 05 01:27:06 PM PST 24 |
5470604082 ps |
| T291 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.88261140 |
|
|
Mar 05 01:27:16 PM PST 24 |
Mar 05 01:36:29 PM PST 24 |
27111733601 ps |
| T292 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1323575632 |
|
|
Mar 05 01:24:23 PM PST 24 |
Mar 05 01:24:26 PM PST 24 |
1409634560 ps |
| T293 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1846517769 |
|
|
Mar 05 01:27:33 PM PST 24 |
Mar 05 01:27:34 PM PST 24 |
36612660 ps |
| T294 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3910149978 |
|
|
Mar 05 01:24:11 PM PST 24 |
Mar 05 01:41:51 PM PST 24 |
103480885423 ps |
| T295 |
/workspace/coverage/default/3.sram_ctrl_regwen.1387819317 |
|
|
Mar 05 01:24:25 PM PST 24 |
Mar 05 01:31:21 PM PST 24 |
42801185554 ps |
| T296 |
/workspace/coverage/default/39.sram_ctrl_regwen.4024071467 |
|
|
Mar 05 01:26:35 PM PST 24 |
Mar 05 01:46:37 PM PST 24 |
11742833592 ps |
| T297 |
/workspace/coverage/default/34.sram_ctrl_regwen.1774369392 |
|
|
Mar 05 01:26:06 PM PST 24 |
Mar 05 01:36:33 PM PST 24 |
3727171468 ps |
| T298 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.559530147 |
|
|
Mar 05 01:24:41 PM PST 24 |
Mar 05 01:25:36 PM PST 24 |
767974204 ps |
| T299 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.4230615517 |
|
|
Mar 05 01:25:02 PM PST 24 |
Mar 05 01:52:00 PM PST 24 |
130841083603 ps |
| T300 |
/workspace/coverage/default/35.sram_ctrl_partial_access.1073227697 |
|
|
Mar 05 01:26:06 PM PST 24 |
Mar 05 01:26:21 PM PST 24 |
2027264010 ps |