Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	131440991	1			T1	109434		T2	4587		T3	281773
triple_byte_access	2593665	1			T1	2134		T3	5664		T4	5894
halfword_access	3982633	1			T1	3187		T3	8448		T4	9202
byte_access	5581842	1			T1	4399		T3	11463		T4	12019
zero_access	1703720	1			T1	1101		T3	2787		T4	3049

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72139012

1

T1

65913

T2

2237

T3

169333

auto[1]

73163839

1

T1

54342

T2

2350

T3

140802

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	65083294	1			T1	59922		T2	2237		T3	153844
auto[0]	triple_byte_access	1232908	1			T1	1149		T3	3084		T4	3091
auto[0]	halfword_access	1940929	1			T1	1786		T3	4681		T4	4777
auto[0]	byte_access	2859673	1			T1	2447		T3	6223		T4	6238
auto[0]	zero_access	1022208	1			T1	609		T3	1501		T4	1580
auto[1]	word_access	66357697	1			T1	49512		T2	2350		T3	127929
auto[1]	triple_byte_access	1360757	1			T1	985		T3	2580		T4	2803
auto[1]	halfword_access	2041704	1			T1	1401		T3	3767		T4	4425
auto[1]	byte_access	2722169	1			T1	1952		T3	5240		T4	5781
auto[1]	zero_access	681512	1			T1	492		T3	1286		T4	1469