Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15753670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152039901

1

T1

162234

T2

6006

T3

102191

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82459566	1			T1	89431		T2	2161		T3	56546
values[0x0]	41101237	1			T1	43071		T2	2009		T3	26889
values[0x1]	44232768	1			T1	46082		T2	2058		T3	29262

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8009436	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

159784135

1

T1

170386

T2

6121

T3

107477

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	568418	1			T1	718		T2	21		T3	463
valid_sources[0x01]	543478	1			T1	690		T2	19		T3	368
valid_sources[0x02]	567317	1			T1	742		T2	789		T3	363
valid_sources[0x03]	558010	1			T1	698		T2	13		T3	456
valid_sources[0x04]	1800084	1			T1	728		T2	5		T3	387
valid_sources[0x05]	587514	1			T1	691		T2	36		T3	524
valid_sources[0x06]	585169	1			T1	752		T2	2		T3	563
valid_sources[0x07]	572062	1			T1	717		T2	12		T3	415
valid_sources[0x08]	2198346	1			T1	749		T2	38		T3	331
valid_sources[0x09]	561677	1			T1	723		T2	18		T3	505
valid_sources[0x0a]	578615	1			T1	686		T2	9		T3	499
valid_sources[0x0b]	640146	1			T1	671		T2	8		T3	486
valid_sources[0x0c]	1344544	1			T1	708		T2	15		T3	426
valid_sources[0x0d]	752523	1			T1	713		T2	25		T3	347
valid_sources[0x0e]	661986	1			T1	716		T2	32		T3	459
valid_sources[0x0f]	549418	1			T1	678		T2	22		T3	398
valid_sources[0x10]	573467	1			T1	716		T2	17		T3	435
valid_sources[0x11]	541392	1			T1	719		T2	8		T3	375
valid_sources[0x12]	610390	1			T1	650		T2	23		T3	469
valid_sources[0x13]	1354200	1			T1	734		T2	3		T3	451
valid_sources[0x14]	751069	1			T1	711		T2	19		T3	419
valid_sources[0x15]	556760	1			T1	712		T2	6		T3	358
valid_sources[0x16]	573241	1			T1	703		T2	21		T3	446
valid_sources[0x17]	605734	1			T1	687		T2	16		T3	327
valid_sources[0x18]	575710	1			T1	722		T2	241		T3	540
valid_sources[0x19]	599978	1			T1	746		T2	5		T3	508
valid_sources[0x1a]	573442	1			T1	713		T2	17		T3	406
valid_sources[0x1b]	558555	1			T1	662		T2	14		T3	418
valid_sources[0x1c]	563265	1			T1	694		T2	16		T3	461
valid_sources[0x1d]	545962	1			T1	696		T2	11		T3	443
valid_sources[0x1e]	593001	1			T1	612		T2	6		T3	383
valid_sources[0x1f]	565723	1			T1	697		T2	29		T3	443
valid_sources[0x20]	1540881	1			T1	684		T2	27		T3	502
valid_sources[0x21]	566091	1			T1	682		T2	29		T3	446
valid_sources[0x22]	537646	1			T1	675		T2	15		T3	536
valid_sources[0x23]	783768	1			T1	649		T2	25		T3	486
valid_sources[0x24]	777489	1			T1	677		T2	4		T3	456
valid_sources[0x25]	639260	1			T1	699		T2	15		T3	462
valid_sources[0x26]	576405	1			T1	723		T2	12		T3	437
valid_sources[0x27]	543991	1			T1	712		T2	21		T3	499
valid_sources[0x28]	554637	1			T1	709		T2	10		T3	388
valid_sources[0x29]	539545	1			T1	685		T2	11		T3	389
valid_sources[0x2a]	578502	1			T1	771		T2	19		T3	434
valid_sources[0x2b]	619063	1			T1	697		T2	33		T3	367
valid_sources[0x2c]	600657	1			T1	691		T2	12		T3	472
valid_sources[0x2d]	597236	1			T1	716		T2	17		T3	376
valid_sources[0x2e]	571372	1			T1	751		T2	30		T3	507
valid_sources[0x2f]	592013	1			T1	721		T2	27		T3	447
valid_sources[0x30]	582683	1			T1	677		T2	22		T3	338
valid_sources[0x31]	583557	1			T1	715		T2	29		T3	347
valid_sources[0x32]	556457	1			T1	722		T2	7		T3	420
valid_sources[0x33]	548135	1			T1	709		T2	2		T3	396
valid_sources[0x34]	612255	1			T1	687		T2	12		T3	350
valid_sources[0x35]	577658	1			T1	703		T2	11		T3	436
valid_sources[0x36]	631659	1			T1	741		T2	20		T3	482
valid_sources[0x37]	558026	1			T1	659		T2	29		T3	381
valid_sources[0x38]	603082	1			T1	679		T2	14		T3	437
valid_sources[0x39]	595631	1			T1	690		T2	27		T3	475
valid_sources[0x3a]	573729	1			T1	723		T2	7		T3	473
valid_sources[0x3b]	638696	1			T1	643		T2	4		T3	461
valid_sources[0x3c]	545411	1			T1	659		T2	30		T3	368
valid_sources[0x3d]	569707	1			T1	672		T2	15		T3	455
valid_sources[0x3e]	546246	1			T1	671		T2	25		T3	445
valid_sources[0x3f]	581593	1			T1	721		T2	27		T3	475
valid_sources[0x40]	573763	1			T1	649		T2	25		T3	371
valid_sources[0x41]	601208	1			T1	665		T2	16		T3	425
valid_sources[0x42]	1941317	1			T1	670		T2	5		T3	442
valid_sources[0x43]	547453	1			T1	687		T2	15		T3	407
valid_sources[0x44]	539781	1			T1	705		T2	10		T3	367
valid_sources[0x45]	551926	1			T1	699		T2	7		T3	481
valid_sources[0x46]	573305	1			T1	715		T2	12		T3	437
valid_sources[0x47]	564200	1			T1	662		T2	20		T3	538
valid_sources[0x48]	539542	1			T1	698		T2	7		T3	500
valid_sources[0x49]	544474	1			T1	687		T2	17		T3	379
valid_sources[0x4a]	545705	1			T1	754		T2	14		T3	384
valid_sources[0x4b]	560064	1			T1	669		T2	20		T3	454
valid_sources[0x4c]	540701	1			T1	656		T2	14		T3	464
valid_sources[0x4d]	575598	1			T1	736		T2	18		T3	416
valid_sources[0x4e]	559413	1			T1	682		T2	8		T3	388
valid_sources[0x4f]	754287	1			T1	735		T2	15		T3	402
valid_sources[0x50]	543079	1			T1	680		T2	1		T3	498
valid_sources[0x51]	550395	1			T1	702		T2	16		T3	472
valid_sources[0x52]	560034	1			T1	811		T2	916		T3	427
valid_sources[0x53]	591777	1			T1	673		T2	7		T3	443
valid_sources[0x54]	645855	1			T1	719		T2	21		T3	413
valid_sources[0x55]	558575	1			T1	703		T2	16		T3	407
valid_sources[0x56]	547839	1			T1	711		T2	9		T3	489
valid_sources[0x57]	548203	1			T1	677		T2	9		T3	471
valid_sources[0x58]	539634	1			T1	730		T2	24		T3	388
valid_sources[0x59]	542117	1			T1	672		T2	14		T3	459
valid_sources[0x5a]	539529	1			T1	703		T2	45		T3	464
valid_sources[0x5b]	574842	1			T1	659		T2	21		T3	466
valid_sources[0x5c]	584886	1			T1	666		T2	10		T3	357
valid_sources[0x5d]	554662	1			T1	681		T2	9		T3	466
valid_sources[0x5e]	561012	1			T1	717		T2	30		T3	461
valid_sources[0x5f]	564557	1			T1	704		T2	17		T3	372
valid_sources[0x60]	621333	1			T1	672		T2	3		T3	478
valid_sources[0x61]	546101	1			T1	686		T2	12		T3	375
valid_sources[0x62]	591576	1			T1	651		T2	35		T3	537
valid_sources[0x63]	634630	1			T1	744		T2	13		T3	419
valid_sources[0x64]	580380	1			T1	716		T2	19		T3	356
valid_sources[0x65]	543701	1			T1	706		T2	16		T3	419
valid_sources[0x66]	580354	1			T1	713		T2	21		T3	445
valid_sources[0x67]	583409	1			T1	680		T2	6		T3	557
valid_sources[0x68]	561095	1			T1	757		T2	22		T3	343
valid_sources[0x69]	573378	1			T1	695		T2	38		T3	418
valid_sources[0x6a]	597266	1			T1	725		T2	2		T3	470
valid_sources[0x6b]	598522	1			T1	678		T2	6		T3	415
valid_sources[0x6c]	547158	1			T1	708		T2	6		T3	463
valid_sources[0x6d]	565658	1			T1	700		T2	30		T3	518
valid_sources[0x6e]	547647	1			T1	766		T2	19		T3	393
valid_sources[0x6f]	541567	1			T1	705		T2	12		T3	386
valid_sources[0x70]	573482	1			T1	679		T2	17		T3	481
valid_sources[0x71]	564545	1			T1	653		T2	7		T3	361
valid_sources[0x72]	540999	1			T1	666		T2	5		T3	409
valid_sources[0x73]	600120	1			T1	747		T2	2		T3	529
valid_sources[0x74]	552241	1			T1	739		T2	34		T3	371
valid_sources[0x75]	560312	1			T1	704		T2	19		T3	413
valid_sources[0x76]	754287	1			T1	690		T2	33		T3	444
valid_sources[0x77]	634864	1			T1	686		T2	7		T3	461
valid_sources[0x78]	552741	1			T1	725		T2	16		T3	406
valid_sources[0x79]	539556	1			T1	698		T2	14		T3	381
valid_sources[0x7a]	1908461	1			T1	695		T2	7		T3	392
valid_sources[0x7b]	668561	1			T1	751		T2	18		T3	427
valid_sources[0x7c]	542105	1			T1	634		T2	8		T3	356
valid_sources[0x7d]	544160	1			T1	676		T2	7		T3	490
valid_sources[0x7e]	543767	1			T1	672		T2	25		T3	571
valid_sources[0x7f]	606745	1			T1	701		T2	15		T3	596
valid_sources[0x80]	1963298	1			T1	726		T2	17		T3	288

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74545334

1

T1

81219

T2

2054

T3

51271

values[0x0]

all_enables

biggest_size

38748454

1

T1

40542

T2

1981

T3

25349

values[0x1]

all_enables

biggest_size

38746113

1

T1

40473

T2

1971

T3

25571

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33953	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

169467

1

T1

8

T2

2009

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58730	1			T2	630		T4	61		T28	318
values[0x0]	69996	1			T1	16		T2	756		T3	5
values[0x1]	74694	1			T1	15		T2	754		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25312	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

178108

1

T1

10

T2

2076

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	773	1			T59	2		T28	9		T27	1
valid_sources[0x01]	881	1			T17	1		T75	1		T29	4
valid_sources[0x02]	739	1			T29	4		T26	8		T130	1
valid_sources[0x03]	862	1			T16	1		T29	1		T53	1
valid_sources[0x04]	729	1			T58	1		T29	13		T45	24
valid_sources[0x05]	807	1			T28	11		T27	1		T29	3
valid_sources[0x06]	1009	1			T15	1		T93	1		T29	7
valid_sources[0x07]	979	1			T28	8		T16	2		T6	1
valid_sources[0x08]	677	1			T131	8		T29	1		T45	22
valid_sources[0x09]	593	1			T1	1		T58	1		T29	7
valid_sources[0x0a]	1106	1			T59	2		T6	2		T29	3
valid_sources[0x0b]	904	1			T29	3		T53	1		T45	20
valid_sources[0x0c]	701	1			T15	1		T17	1		T28	2
valid_sources[0x0d]	939	1			T2	146		T29	8		T132	1
valid_sources[0x0e]	745	1			T133	1		T29	1		T55	1
valid_sources[0x0f]	827	1			T15	1		T16	1		T5	2
valid_sources[0x10]	698	1			T15	1		T16	1		T29	5
valid_sources[0x11]	624	1			T1	1		T28	1		T29	4
valid_sources[0x12]	660	1			T58	1		T29	1		T53	1
valid_sources[0x13]	592	1			T1	1		T6	1		T27	1
valid_sources[0x14]	1108	1			T75	1		T76	1		T29	2
valid_sources[0x15]	786	1			T59	2		T5	1		T75	1
valid_sources[0x16]	600	1			T14	34		T15	1		T76	1
valid_sources[0x17]	708	1			T5	1		T6	9		T18	4
valid_sources[0x18]	937	1			T1	1		T29	4		T77	1
valid_sources[0x19]	953	1			T8	5		T15	1		T28	101
valid_sources[0x1a]	756	1			T15	1		T29	2		T53	1
valid_sources[0x1b]	695	1			T58	1		T6	2		T75	1
valid_sources[0x1c]	617	1			T58	3		T24	1		T27	2
valid_sources[0x1d]	666	1			T75	1		T29	5		T45	20
valid_sources[0x1e]	1105	1			T2	3		T6	12		T134	1
valid_sources[0x1f]	845	1			T29	5		T53	1		T130	1
valid_sources[0x20]	646	1			T28	2		T29	4		T132	1
valid_sources[0x21]	841	1			T16	1		T6	4		T29	4
valid_sources[0x22]	711	1			T28	1		T16	1		T29	6
valid_sources[0x23]	666	1			T1	1		T28	27		T29	6
valid_sources[0x24]	612	1			T28	2		T29	2		T55	2
valid_sources[0x25]	1102	1			T2	162		T59	1		T5	1
valid_sources[0x26]	780	1			T28	1		T29	1		T26	2
valid_sources[0x27]	1190	1			T5	1		T75	1		T29	2
valid_sources[0x28]	1055	1			T28	82		T75	2		T29	6
valid_sources[0x29]	904	1			T58	1		T29	6		T53	2
valid_sources[0x2a]	595	1			T27	1		T75	1		T29	4
valid_sources[0x2b]	979	1			T2	112		T28	1		T29	3
valid_sources[0x2c]	587	1			T29	4		T53	2		T26	5
valid_sources[0x2d]	986	1			T13	1		T29	4		T112	9
valid_sources[0x2e]	590	1			T24	1		T5	1		T75	1
valid_sources[0x2f]	869	1			T29	6		T132	2		T45	30
valid_sources[0x30]	636	1			T58	1		T5	1		T29	10
valid_sources[0x31]	843	1			T5	1		T29	1		T130	1
valid_sources[0x32]	561	1			T11	2		T29	1		T26	2
valid_sources[0x33]	521	1			T1	1		T75	1		T29	4
valid_sources[0x34]	599	1			T15	1		T5	1		T135	14
valid_sources[0x35]	775	1			T107	32		T5	1		T27	1
valid_sources[0x36]	921	1			T1	1		T58	1		T28	1
valid_sources[0x37]	744	1			T59	1		T27	1		T75	1
valid_sources[0x38]	939	1			T2	1		T24	1		T25	55
valid_sources[0x39]	957	1			T27	1		T29	6		T112	2
valid_sources[0x3a]	697	1			T58	1		T6	3		T29	4
valid_sources[0x3b]	816	1			T1	2		T5	2		T27	1
valid_sources[0x3c]	1059	1			T2	34		T29	4		T26	1
valid_sources[0x3d]	685	1			T2	3		T16	1		T5	1
valid_sources[0x3e]	608	1			T5	1		T27	2		T29	3
valid_sources[0x3f]	877	1			T28	10		T29	4		T53	1
valid_sources[0x40]	1189	1			T2	145		T24	4		T28	18
valid_sources[0x41]	667	1			T6	11		T29	3		T55	1
valid_sources[0x42]	628	1			T58	1		T6	4		T29	6
valid_sources[0x43]	795	1			T1	1		T58	2		T59	2
valid_sources[0x44]	535	1			T15	1		T59	1		T44	1
valid_sources[0x45]	1123	1			T12	1		T27	4		T29	9
valid_sources[0x46]	635	1			T28	13		T29	6		T132	1
valid_sources[0x47]	1212	1			T59	3		T29	5		T53	1
valid_sources[0x48]	723	1			T8	7		T29	1		T45	20
valid_sources[0x49]	692	1			T28	2		T29	6		T26	2
valid_sources[0x4a]	758	1			T2	94		T5	1		T29	2
valid_sources[0x4b]	781	1			T15	3		T59	2		T29	3
valid_sources[0x4c]	815	1			T27	1		T29	4		T77	1
valid_sources[0x4d]	728	1			T29	5		T45	21		T136	13
valid_sources[0x4e]	747	1			T6	6		T27	1		T29	2
valid_sources[0x4f]	1063	1			T5	1		T75	1		T29	2
valid_sources[0x50]	943	1			T15	2		T58	1		T135	2
valid_sources[0x51]	930	1			T93	1		T27	2		T29	5
valid_sources[0x52]	734	1			T28	1		T6	1		T29	5
valid_sources[0x53]	730	1			T6	1		T76	1		T53	1
valid_sources[0x54]	855	1			T15	1		T44	1		T27	1
valid_sources[0x55]	923	1			T28	15		T5	2		T76	1
valid_sources[0x56]	855	1			T27	1		T29	4		T53	1
valid_sources[0x57]	1004	1			T57	2		T27	2		T29	7
valid_sources[0x58]	680	1			T5	1		T6	13		T27	1
valid_sources[0x59]	1371	1			T1	1		T2	50		T5	1
valid_sources[0x5a]	579	1			T58	1		T27	3		T29	4
valid_sources[0x5b]	1046	1			T52	2		T27	1		T135	3
valid_sources[0x5c]	636	1			T28	19		T29	5		T112	14
valid_sources[0x5d]	615	1			T16	1		T29	2		T53	1
valid_sources[0x5e]	706	1			T58	1		T27	2		T29	3
valid_sources[0x5f]	847	1			T17	1		T29	3		T77	3
valid_sources[0x60]	939	1			T29	7		T55	2		T45	21
valid_sources[0x61]	948	1			T28	35		T27	2		T29	4
valid_sources[0x62]	1101	1			T28	2		T29	6		T130	2
valid_sources[0x63]	883	1			T58	1		T5	1		T27	1
valid_sources[0x64]	888	1			T2	13		T6	4		T27	1
valid_sources[0x65]	562	1			T15	1		T29	4		T55	3
valid_sources[0x66]	952	1			T15	2		T59	1		T5	1
valid_sources[0x67]	813	1			T2	21		T76	1		T29	3
valid_sources[0x68]	845	1			T29	3		T130	5		T132	3
valid_sources[0x69]	885	1			T6	4		T29	4		T26	1
valid_sources[0x6a]	907	1			T15	1		T75	1		T29	3
valid_sources[0x6b]	1155	1			T15	1		T28	3		T92	1
valid_sources[0x6c]	616	1			T75	1		T29	3		T55	1
valid_sources[0x6d]	911	1			T1	1		T16	1		T29	4
valid_sources[0x6e]	1095	1			T2	142		T59	1		T29	6
valid_sources[0x6f]	717	1			T15	1		T28	14		T53	2
valid_sources[0x70]	935	1			T2	77		T15	1		T29	1
valid_sources[0x71]	907	1			T76	1		T29	7		T53	2
valid_sources[0x72]	955	1			T28	1		T29	3		T26	5
valid_sources[0x73]	847	1			T59	2		T24	1		T29	6
valid_sources[0x74]	495	1			T29	6		T53	1		T45	11
valid_sources[0x75]	688	1			T15	1		T27	3		T29	1
valid_sources[0x76]	815	1			T2	3		T24	1		T29	11
valid_sources[0x77]	710	1			T1	2		T27	3		T75	1
valid_sources[0x78]	681	1			T1	1		T24	1		T5	1
valid_sources[0x79]	776	1			T28	3		T29	5		T77	1
valid_sources[0x7a]	1029	1			T8	24		T6	8		T29	1
valid_sources[0x7b]	726	1			T6	2		T29	3		T45	15
valid_sources[0x7c]	843	1			T2	194		T15	1		T29	3
valid_sources[0x7d]	1002	1			T28	1		T6	2		T29	7
valid_sources[0x7e]	956	1			T24	1		T76	1		T29	4
valid_sources[0x7f]	656	1			T1	1		T28	32		T6	2
valid_sources[0x80]	728	1			T29	4		T26	5		T45	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46137

1

T2

588

T4

28

T28

292

values[0x0]

all_enables

biggest_size

62578

1

T1

7

T2

751

T3

3

values[0x1]

all_enables

biggest_size

60752

1

T1

1

T2

670

T3

3