Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15752033

1

T1

16350

T2

2920

T3

10506

full_word

149531492

1

T1

162234

T2

6335

T3

102191

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	165283225	1			T1	178584		T2	9255		T3	112697
auto[TlIntgErrCmd]	104	1			T98	10		T99	10		T100	5
auto[TlIntgErrData]	97	1			T98	3		T99	6		T100	7
auto[TlIntgErrBoth]	99	1			T98	7		T99	4		T100	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79806040

1

T1

89431

T2

2757

T3

56546

auto[1]

85477485

1

T1

89153

T2

6498

T3

56151

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7718183	1			T1	8212		T2	631		T3	5275
auto[TlIntgErrNone]	partial	auto[1]	8033577	1			T1	8138		T2	2289		T3	5231
auto[TlIntgErrNone]	full_word	auto[0]	72087712	1			T1	81219		T2	2126		T3	51271
auto[TlIntgErrNone]	full_word	auto[1]	77443753	1			T1	81015		T2	4209		T3	50920
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T98	3		T99	7		T100	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T98	5		T99	1		T100	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T98	1		T119	1		T114	3
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T98	1		T99	2		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T98	1		T99	2		T100	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T98	2		T99	3		T100	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T119	1		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T99	1		T119	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T98	4		T100	5		T119	3
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T98	3		T99	3		T100	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T99	1		T113	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T113	1		T114	1		T121	1