Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	817970	1			T2	5		T3	9535		T8	41775
auto[1]	10734494	1			T1	45939		T3	2188		T7	3583
auto[2]	625756	1			T2	3		T3	8666		T8	36296
auto[3]	10467365	1			T1	45724		T3	1285		T7	3649

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14179467	1			T1	76458		T2	8		T3	16710
auto[1]	2086547	1			T1	7159		T3	2364		T8	9935
auto[2]	2117780	1			T1	7335		T3	2297		T8	9588
auto[3]	4261791	1			T1	711		T3	303		T8	1278

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9662957

1

T1

91662

T2

8

T3

21674

auto[1]

12982628

1

T1

1

T8

3

T13

156866

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	328789	1			T2	5		T3	7832		T8	34472
auto[0]	auto[0]	auto[1]	33667	1			T3	789		T8	3481		T14	440
auto[0]	auto[0]	auto[2]	33701	1			T3	830		T8	3469		T14	426
auto[0]	auto[0]	auto[3]	50390	1			T3	84		T8	352		T14	36
auto[0]	auto[1]	auto[0]	3285263	1			T1	38293		T3	1167		T7	3583
auto[0]	auto[1]	auto[1]	349651	1			T1	3378		T3	816		T8	3297
auto[0]	auto[1]	auto[2]	372678	1			T1	3909		T3	131		T8	511
auto[0]	auto[1]	auto[3]	533659	1			T1	359		T3	74		T8	332
auto[0]	auto[2]	auto[0]	238877	1			T2	3		T3	7193		T8	30187
auto[0]	auto[2]	auto[1]	27814	1			T3	713		T8	2945		T14	226
auto[0]	auto[2]	auto[2]	23496	1			T3	690		T8	2869		T14	138
auto[0]	auto[2]	auto[3]	35164	1			T3	70		T8	294		T14	15
auto[0]	auto[3]	auto[0]	3135640	1			T1	38164		T3	518		T7	3649
auto[0]	auto[3]	auto[1]	353508	1			T1	3781		T3	46		T8	212
auto[0]	auto[3]	auto[2]	370860	1			T1	3426		T3	646		T8	2738
auto[0]	auto[3]	auto[3]	489800	1			T1	352		T3	75		T8	300
auto[1]	auto[0]	auto[0]	12230	1			T8	1		T110	1		T111	1
auto[1]	auto[0]	auto[1]	55404	1			T125	2393		T126	1		T127	1
auto[1]	auto[0]	auto[2]	55367	1			T125	2323		T126	1		T128	4956
auto[1]	auto[0]	auto[3]	248422	1			T123	3		T124	2		T125	10617
auto[1]	auto[1]	auto[0]	3587985	1			T13	65758		T15	2		T44	82975
auto[1]	auto[1]	auto[1]	630956	1			T13	5855		T15	1		T44	7740
auto[1]	auto[1]	auto[2]	598161	1			T13	6528		T44	8342		T92	11877
auto[1]	auto[1]	auto[3]	1376141	1			T13	588		T44	774		T92	53434
auto[1]	auto[2]	auto[0]	10291	1			T8	1		T125	479		T128	963
auto[1]	auto[2]	auto[1]	47008	1			T125	2230		T128	4566		T129	2636
auto[1]	auto[2]	auto[2]	44126	1			T125	1543		T128	3376		T129	1911
auto[1]	auto[2]	auto[3]	198980	1			T125	7377		T128	14965		T129	8813
auto[1]	auto[3]	auto[0]	3580392	1			T1	1		T13	65321		T15	4
auto[1]	auto[3]	auto[1]	588539	1			T13	6470		T44	8423		T16	1
auto[1]	auto[3]	auto[2]	619391	1			T8	1		T13	5766		T44	7518
auto[1]	auto[3]	auto[3]	1329235	1			T13	580		T44	796		T92	53568