Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1111491121	166505	0	0
ctrl_regwen_rd_A	1111491121	8314	0	0
exec_rd_A	1111491121	7366	0	0
exec_regwen_rd_A	1111491121	7895	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111491121	166505	0	0
T2	86356	2099	0	0
T3	134581	0	0	0
T7	75212	0	0	0
T8	247874	0	0	0
T9	235749	0	0	0
T10	437814	0	0	0
T11	76464	0	0	0
T12	137301	0	0	0
T13	451912	0	0	0
T14	210214	0	0	0
T28	0	1091	0	0
T29	0	338	0	0
T45	0	4291	0	0
T46	0	3001	0	0
T47	0	2986	0	0
T48	0	3113	0	0
T49	0	1228	0	0
T50	0	1548	0	0
T51	0	4267	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111491121	8314	0	0
T5	121272	0	0	0
T6	417719	0	0	0
T16	993204	0	0	0
T20	1133	0	0	0
T25	837687	0	0	0
T28	35259	300	0	0
T29	0	74	0	0
T47	0	623	0	0
T48	0	747	0	0
T92	460908	0	0	0
T93	293513	0	0	0
T101	0	659	0	0
T102	0	682	0	0
T103	0	463	0	0
T104	0	440	0	0
T105	0	421	0	0
T106	0	540	0	0
T107	209669	0	0	0
T108	137691	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111491121	7366	0	0
T5	121272	0	0	0
T6	417719	0	0	0
T16	993204	0	0	0
T20	1133	0	0	0
T25	837687	0	0	0
T28	35259	288	0	0
T29	0	108	0	0
T47	0	454	0	0
T48	0	545	0	0
T92	460908	0	0	0
T93	293513	0	0	0
T101	0	483	0	0
T102	0	548	0	0
T103	0	419	0	0
T104	0	431	0	0
T105	0	302	0	0
T106	0	529	0	0
T107	209669	0	0	0
T108	137691	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1111491121	7895	0	0
T5	121272	0	0	0
T6	417719	0	0	0
T16	993204	0	0	0
T20	1133	0	0	0
T25	837687	0	0	0
T28	35259	275	0	0
T29	0	127	0	0
T47	0	658	0	0
T48	0	580	0	0
T92	460908	0	0	0
T93	293513	0	0	0
T101	0	549	0	0
T102	0	682	0	0
T103	0	388	0	0
T104	0	396	0	0
T105	0	404	0	0
T106	0	440	0	0
T107	209669	0	0	0
T108	137691	0	0	0