Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16280322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152186561

1

T2

1603

T3

163840

T4

891

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82857452	1			T2	4459		T3	819200		T4	2340
values[0x0]	41181827	1			T2	1458		T3	409644		T4	799
values[0x1]	44427604	1			T2	3090		T3	409556		T4	1437

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8274152	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160192731

1

T2

5412

T3

163840

T4

2724

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	564126	1			T2	35		T3	6377		T4	22
valid_sources[0x01]	573102	1			T2	32		T3	6506		T4	12
valid_sources[0x02]	567401	1			T2	29		T3	6311		T4	20
valid_sources[0x03]	588228	1			T2	37		T3	7154		T4	17
valid_sources[0x04]	572455	1			T2	36		T3	6532		T4	17
valid_sources[0x05]	565830	1			T2	39		T3	6743		T4	38
valid_sources[0x06]	555347	1			T2	50		T3	6383		T4	11
valid_sources[0x07]	540846	1			T2	32		T3	5782		T4	10
valid_sources[0x08]	570243	1			T2	35		T3	6153		T4	22
valid_sources[0x09]	584431	1			T2	37		T3	6489		T4	17
valid_sources[0x0a]	544084	1			T2	31		T3	6571		T4	18
valid_sources[0x0b]	596871	1			T2	33		T3	6592		T4	21
valid_sources[0x0c]	564424	1			T2	23		T3	6221		T4	28
valid_sources[0x0d]	1748388	1			T2	41		T3	6137		T4	14
valid_sources[0x0e]	657256	1			T2	46		T3	6685		T4	11
valid_sources[0x0f]	585903	1			T2	34		T3	6767		T4	11
valid_sources[0x10]	564047	1			T2	30		T3	6218		T4	24
valid_sources[0x11]	549058	1			T2	41		T3	6360		T4	18
valid_sources[0x12]	550255	1			T2	36		T3	6299		T4	10
valid_sources[0x13]	633367	1			T2	34		T3	6387		T4	16
valid_sources[0x14]	540194	1			T2	45		T3	6416		T4	16
valid_sources[0x15]	613422	1			T2	37		T3	6538		T4	30
valid_sources[0x16]	535722	1			T2	31		T3	6171		T4	17
valid_sources[0x17]	618558	1			T2	22		T3	6343		T4	27
valid_sources[0x18]	635459	1			T2	27		T3	6343		T4	7
valid_sources[0x19]	617247	1			T2	30		T3	6541		T4	37
valid_sources[0x1a]	551778	1			T2	29		T3	6651		T4	4
valid_sources[0x1b]	538269	1			T2	38		T3	6894		T4	14
valid_sources[0x1c]	619561	1			T2	31		T3	5989		T4	10
valid_sources[0x1d]	562196	1			T2	30		T3	6523		T4	7
valid_sources[0x1e]	765188	1			T2	35		T3	6681		T4	39
valid_sources[0x1f]	582577	1			T2	31		T3	6296		T4	25
valid_sources[0x20]	560030	1			T2	31		T3	6309		T4	22
valid_sources[0x21]	582979	1			T2	32		T3	6334		T4	33
valid_sources[0x22]	545824	1			T2	38		T3	6087		T4	23
valid_sources[0x23]	549692	1			T2	41		T3	6306		T4	7
valid_sources[0x24]	585239	1			T2	39		T3	6615		T4	25
valid_sources[0x25]	554437	1			T2	50		T3	6495		T4	15
valid_sources[0x26]	547522	1			T2	26		T3	6908		T4	15
valid_sources[0x27]	568205	1			T2	33		T3	6517		T4	28
valid_sources[0x28]	570543	1			T2	31		T3	6342		T4	10
valid_sources[0x29]	555415	1			T2	37		T3	6622		T4	15
valid_sources[0x2a]	586297	1			T2	37		T3	6083		T4	19
valid_sources[0x2b]	657010	1			T2	29		T3	7155		T4	19
valid_sources[0x2c]	587688	1			T2	37		T3	6636		T4	18
valid_sources[0x2d]	562772	1			T2	48		T3	6433		T4	15
valid_sources[0x2e]	631061	1			T2	40		T3	6004		T4	16
valid_sources[0x2f]	572669	1			T2	32		T3	6317		T4	29
valid_sources[0x30]	632290	1			T2	38		T3	6477		T4	13
valid_sources[0x31]	579689	1			T2	31		T3	6705		T4	10
valid_sources[0x32]	542052	1			T2	34		T3	6725		T4	20
valid_sources[0x33]	605489	1			T2	30		T3	6787		T4	16
valid_sources[0x34]	629584	1			T2	30		T3	6193		T4	15
valid_sources[0x35]	572748	1			T2	38		T3	6448		T4	10
valid_sources[0x36]	616777	1			T2	40		T3	6383		T4	15
valid_sources[0x37]	559656	1			T2	35		T3	6399		T4	11
valid_sources[0x38]	538589	1			T2	32		T3	6516		T4	15
valid_sources[0x39]	537600	1			T2	29		T3	6197		T4	20
valid_sources[0x3a]	628199	1			T2	39		T3	6059		T4	16
valid_sources[0x3b]	763443	1			T2	30		T3	6410		T4	18
valid_sources[0x3c]	548215	1			T2	37		T3	6327		T4	30
valid_sources[0x3d]	566660	1			T2	34		T3	6580		T4	9
valid_sources[0x3e]	546647	1			T2	42		T3	6344		T4	17
valid_sources[0x3f]	568479	1			T2	38		T3	6049		T4	21
valid_sources[0x40]	561499	1			T2	31		T3	6199		T4	12
valid_sources[0x41]	661630	1			T2	16		T3	6564		T4	27
valid_sources[0x42]	568058	1			T2	25		T3	6276		T4	25
valid_sources[0x43]	547509	1			T2	43		T3	6260		T4	30
valid_sources[0x44]	586917	1			T2	40		T3	6339		T4	13
valid_sources[0x45]	562910	1			T2	34		T3	6223		T4	29
valid_sources[0x46]	808092	1			T2	41		T3	6087		T4	18
valid_sources[0x47]	562952	1			T2	43		T3	6160		T4	17
valid_sources[0x48]	681992	1			T2	38		T3	7180		T4	20
valid_sources[0x49]	565491	1			T2	36		T3	6259		T4	30
valid_sources[0x4a]	595789	1			T2	40		T3	6327		T4	12
valid_sources[0x4b]	594282	1			T2	38		T3	6300		T4	6
valid_sources[0x4c]	563570	1			T2	41		T3	6515		T4	10
valid_sources[0x4d]	543305	1			T2	32		T3	6642		T4	15
valid_sources[0x4e]	569271	1			T2	28		T3	6392		T4	7
valid_sources[0x4f]	2193303	1			T2	32		T3	6680		T4	11
valid_sources[0x50]	541589	1			T2	34		T3	6653		T4	17
valid_sources[0x51]	597750	1			T2	39		T3	6562		T4	13
valid_sources[0x52]	542913	1			T2	31		T3	6513		T4	4
valid_sources[0x53]	569993	1			T2	31		T3	6120		T4	3
valid_sources[0x54]	544084	1			T2	36		T3	6762		T4	18
valid_sources[0x55]	558797	1			T2	34		T3	6477		T4	14
valid_sources[0x56]	1750889	1			T2	31		T3	6020		T4	13
valid_sources[0x57]	554160	1			T2	32		T3	6898		T4	15
valid_sources[0x58]	550351	1			T2	31		T3	6713		T4	9
valid_sources[0x59]	599907	1			T2	37		T3	5926		T4	16
valid_sources[0x5a]	564680	1			T2	40		T3	6369		T4	26
valid_sources[0x5b]	547759	1			T2	35		T3	6181		T4	24
valid_sources[0x5c]	549937	1			T2	33		T3	6288		T4	34
valid_sources[0x5d]	558757	1			T2	40		T3	6502		T4	21
valid_sources[0x5e]	564576	1			T2	38		T3	6155		T4	14
valid_sources[0x5f]	584603	1			T2	42		T3	6365		T4	25
valid_sources[0x60]	598726	1			T2	27		T3	6200		T4	36
valid_sources[0x61]	561990	1			T2	30		T3	6415		T4	13
valid_sources[0x62]	573728	1			T2	30		T3	6497		T4	27
valid_sources[0x63]	598387	1			T2	32		T3	6237		T4	11
valid_sources[0x64]	558418	1			T2	31		T3	6538		T4	13
valid_sources[0x65]	558687	1			T2	34		T3	6657		T4	17
valid_sources[0x66]	566277	1			T2	39		T3	6488		T4	27
valid_sources[0x67]	603370	1			T2	33		T3	6102		T4	22
valid_sources[0x68]	582290	1			T2	29		T3	6579		T4	7
valid_sources[0x69]	533956	1			T2	38		T3	6234		T4	21
valid_sources[0x6a]	1728717	1			T2	37		T3	6783		T4	16
valid_sources[0x6b]	556108	1			T2	31		T3	6653		T4	25
valid_sources[0x6c]	648459	1			T2	46		T3	6393		T4	17
valid_sources[0x6d]	540664	1			T2	27		T3	5959		T4	24
valid_sources[0x6e]	543027	1			T2	33		T3	6556		T4	20
valid_sources[0x6f]	548226	1			T2	34		T3	6667		T4	8
valid_sources[0x70]	608201	1			T2	27		T3	6414		T4	28
valid_sources[0x71]	2702587	1			T2	29		T3	6390		T4	35
valid_sources[0x72]	575863	1			T2	38		T3	6475		T4	11
valid_sources[0x73]	541474	1			T2	32		T3	6464		T4	14
valid_sources[0x74]	548277	1			T2	40		T3	6139		T4	10
valid_sources[0x75]	608722	1			T2	36		T3	6689		T4	17
valid_sources[0x76]	595975	1			T2	36		T3	6804		T4	19
valid_sources[0x77]	544829	1			T2	33		T3	6532		T4	24
valid_sources[0x78]	676311	1			T2	39		T3	6529		T4	14
valid_sources[0x79]	646928	1			T2	37		T3	6268		T4	9
valid_sources[0x7a]	585003	1			T2	45		T3	6818		T4	25
valid_sources[0x7b]	606205	1			T2	35		T3	6203		T4	13
valid_sources[0x7c]	552825	1			T2	40		T3	6185		T4	11
valid_sources[0x7d]	555991	1			T2	40		T3	5927		T4	25
valid_sources[0x7e]	569749	1			T2	38		T3	5915		T4	16
valid_sources[0x7f]	588197	1			T2	29		T3	6401		T4	19
valid_sources[0x80]	616640	1			T2	31		T3	6547		T4	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74677480

1

T2

805

T3

819200

T4

453

values[0x0]

all_enables

biggest_size

38751662

1

T2

392

T3

409644

T4

216

values[0x1]

all_enables

biggest_size

38757419

1

T2

406

T3

409556

T4

222

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32324	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153978

1

T3

8

T5

41

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53237	1			T5	56		T19	8		T20	21
values[0x0]	64171	1			T1	1		T2	1		T3	13
values[0x1]	68894	1			T3	12		T4	1		T5	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162191

1

T3

10

T5

55

T8

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	618	1			T33	4		T6	1		T7	2
valid_sources[0x01]	623	1			T21	1		T33	12		T47	1
valid_sources[0x02]	743	1			T33	7		T138	1		T48	1
valid_sources[0x03]	761	1			T20	3		T139	1		T33	12
valid_sources[0x04]	1033	1			T5	1		T20	1		T140	2
valid_sources[0x05]	614	1			T21	1		T61	3		T26	1
valid_sources[0x06]	704	1			T20	1		T21	1		T33	23
valid_sources[0x07]	531	1			T33	7		T48	9		T49	6
valid_sources[0x08]	690	1			T20	1		T61	2		T33	7
valid_sources[0x09]	626	1			T5	3		T33	9		T30	1
valid_sources[0x0a]	804	1			T25	1		T33	15		T130	28
valid_sources[0x0b]	635	1			T33	4		T6	1		T47	1
valid_sources[0x0c]	1187	1			T33	5		T6	1		T30	1
valid_sources[0x0d]	515	1			T33	7		T6	1		T47	1
valid_sources[0x0e]	1004	1			T5	1		T78	1		T21	1
valid_sources[0x0f]	510	1			T61	5		T33	8		T7	4
valid_sources[0x10]	571	1			T5	2		T20	1		T33	8
valid_sources[0x11]	562	1			T25	1		T98	1		T33	5
valid_sources[0x12]	700	1			T25	3		T33	5		T7	7
valid_sources[0x13]	1299	1			T20	2		T33	6		T30	2
valid_sources[0x14]	504	1			T26	1		T33	7		T6	1
valid_sources[0x15]	740	1			T5	2		T17	1		T33	4
valid_sources[0x16]	771	1			T5	1		T24	16		T13	1
valid_sources[0x17]	603	1			T141	5		T33	7		T6	1
valid_sources[0x18]	655	1			T5	1		T61	4		T33	11
valid_sources[0x19]	643	1			T5	1		T81	2		T33	5
valid_sources[0x1a]	554	1			T18	1		T21	2		T33	16
valid_sources[0x1b]	609	1			T33	6		T47	2		T142	1
valid_sources[0x1c]	467	1			T83	1		T33	9		T6	2
valid_sources[0x1d]	690	1			T20	1		T33	1		T143	1
valid_sources[0x1e]	563	1			T20	1		T21	1		T33	4
valid_sources[0x1f]	717	1			T26	1		T139	1		T33	11
valid_sources[0x20]	695	1			T5	3		T33	8		T62	2
valid_sources[0x21]	716	1			T20	1		T33	6		T62	1
valid_sources[0x22]	750	1			T33	12		T47	1		T144	2
valid_sources[0x23]	564	1			T33	6		T63	1		T145	2
valid_sources[0x24]	1396	1			T5	1		T18	1		T61	4
valid_sources[0x25]	726	1			T20	1		T33	9		T48	16
valid_sources[0x26]	715	1			T146	2		T33	6		T30	2
valid_sources[0x27]	738	1			T18	1		T92	1		T33	14
valid_sources[0x28]	590	1			T5	1		T20	2		T33	7
valid_sources[0x29]	976	1			T33	13		T48	4		T49	10
valid_sources[0x2a]	654	1			T20	1		T147	8		T33	7
valid_sources[0x2b]	628	1			T5	1		T25	3		T33	5
valid_sources[0x2c]	436	1			T18	1		T33	5		T62	2
valid_sources[0x2d]	597	1			T10	5		T20	2		T61	1
valid_sources[0x2e]	875	1			T5	1		T18	1		T21	2
valid_sources[0x2f]	592	1			T5	2		T74	1		T78	1
valid_sources[0x30]	761	1			T21	1		T22	3		T33	11
valid_sources[0x31]	1071	1			T5	3		T98	1		T20	1
valid_sources[0x32]	650	1			T33	12		T47	1		T48	21
valid_sources[0x33]	861	1			T5	1		T20	2		T33	7
valid_sources[0x34]	682	1			T33	16		T30	1		T47	2
valid_sources[0x35]	743	1			T33	6		T47	1		T48	4
valid_sources[0x36]	816	1			T33	7		T30	1		T47	1
valid_sources[0x37]	649	1			T4	1		T5	1		T20	3
valid_sources[0x38]	531	1			T33	7		T48	2		T49	7
valid_sources[0x39]	646	1			T18	1		T20	1		T33	15
valid_sources[0x3a]	660	1			T5	1		T33	1		T47	1
valid_sources[0x3b]	787	1			T5	1		T26	1		T33	13
valid_sources[0x3c]	726	1			T18	1		T98	1		T33	10
valid_sources[0x3d]	746	1			T5	1		T33	5		T62	1
valid_sources[0x3e]	930	1			T33	7		T6	2		T62	1
valid_sources[0x3f]	533	1			T33	6		T7	4		T47	1
valid_sources[0x40]	594	1			T5	1		T33	8		T143	1
valid_sources[0x41]	708	1			T33	4		T148	1		T149	1
valid_sources[0x42]	683	1			T18	1		T80	4		T26	1
valid_sources[0x43]	734	1			T33	8		T30	3		T150	2
valid_sources[0x44]	740	1			T33	5		T6	1		T47	1
valid_sources[0x45]	614	1			T5	1		T33	7		T6	5
valid_sources[0x46]	859	1			T20	1		T141	3		T137	3
valid_sources[0x47]	1007	1			T97	1		T33	1		T6	3
valid_sources[0x48]	985	1			T20	2		T22	2		T33	6
valid_sources[0x49]	674	1			T141	1		T33	6		T47	1
valid_sources[0x4a]	710	1			T33	4		T6	2		T47	1
valid_sources[0x4b]	590	1			T20	1		T33	6		T6	1
valid_sources[0x4c]	848	1			T18	1		T33	15		T6	1
valid_sources[0x4d]	559	1			T5	2		T33	6		T6	1
valid_sources[0x4e]	924	1			T18	1		T61	1		T151	1
valid_sources[0x4f]	726	1			T77	2		T33	2		T7	2
valid_sources[0x50]	706	1			T33	16		T47	1		T34	1
valid_sources[0x51]	665	1			T33	5		T47	1		T63	1
valid_sources[0x52]	870	1			T33	5		T62	1		T145	1
valid_sources[0x53]	1071	1			T20	2		T33	12		T47	1
valid_sources[0x54]	673	1			T5	1		T33	8		T6	2
valid_sources[0x55]	718	1			T5	1		T97	1		T33	12
valid_sources[0x56]	1079	1			T5	6		T20	3		T33	8
valid_sources[0x57]	887	1			T20	1		T33	8		T35	4
valid_sources[0x58]	628	1			T33	11		T30	1		T48	2
valid_sources[0x59]	782	1			T5	2		T152	1		T33	7
valid_sources[0x5a]	843	1			T21	1		T33	10		T7	4
valid_sources[0x5b]	579	1			T18	1		T33	9		T7	1
valid_sources[0x5c]	1076	1			T5	1		T20	1		T21	1
valid_sources[0x5d]	719	1			T139	1		T22	1		T33	10
valid_sources[0x5e]	629	1			T33	6		T62	2		T47	1
valid_sources[0x5f]	1139	1			T18	1		T98	1		T61	2
valid_sources[0x60]	557	1			T5	1		T11	7		T20	1
valid_sources[0x61]	561	1			T20	1		T33	5		T6	2
valid_sources[0x62]	547	1			T20	1		T33	6		T47	2
valid_sources[0x63]	602	1			T5	1		T25	2		T33	8
valid_sources[0x64]	648	1			T5	1		T61	1		T26	1
valid_sources[0x65]	494	1			T20	1		T61	2		T152	1
valid_sources[0x66]	567	1			T5	1		T98	2		T33	9
valid_sources[0x67]	670	1			T18	1		T33	11		T153	1
valid_sources[0x68]	817	1			T5	2		T33	7		T30	2
valid_sources[0x69]	752	1			T5	4		T20	3		T33	1
valid_sources[0x6a]	556	1			T5	2		T33	8		T30	5
valid_sources[0x6b]	576	1			T20	4		T33	4		T47	2
valid_sources[0x6c]	803	1			T14	4		T61	1		T33	12
valid_sources[0x6d]	644	1			T5	1		T12	1		T21	1
valid_sources[0x6e]	547	1			T5	1		T33	7		T6	1
valid_sources[0x6f]	639	1			T2	1		T33	4		T47	1
valid_sources[0x70]	474	1			T5	1		T33	5		T47	1
valid_sources[0x71]	663	1			T33	9		T6	1		T62	1
valid_sources[0x72]	727	1			T97	1		T20	1		T134	1
valid_sources[0x73]	808	1			T91	1		T33	5		T47	1
valid_sources[0x74]	688	1			T141	1		T137	2		T33	9
valid_sources[0x75]	888	1			T5	3		T33	11		T59	2
valid_sources[0x76]	873	1			T33	6		T6	2		T47	1
valid_sources[0x77]	1217	1			T18	1		T20	3		T61	1
valid_sources[0x78]	645	1			T5	1		T33	12		T6	1
valid_sources[0x79]	457	1			T5	3		T151	1		T33	3
valid_sources[0x7a]	687	1			T140	12		T33	7		T6	1
valid_sources[0x7b]	739	1			T5	1		T16	2		T20	2
valid_sources[0x7c]	553	1			T1	1		T19	37		T33	8
valid_sources[0x7d]	738	1			T33	6		T62	2		T47	2
valid_sources[0x7e]	564	1			T33	10		T145	1		T138	1
valid_sources[0x7f]	508	1			T154	1		T33	8		T47	2
valid_sources[0x80]	676	1			T33	11		T32	1		T34	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41667

1

T5

31

T19

6

T20

9

values[0x0]

all_enables

biggest_size

56888

1

T3

5

T5

8

T8

1

values[0x1]

all_enables

biggest_size

55423

1

T3

3

T5

2

T11

1