Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16238701

1

T2

7404

T4

3685

T5

13231

full_word

149535157

1

T2

1603

T3

163840

T4

891

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	165773598	1			T2	9007		T3	163840		T4	4576
auto[TlIntgErrCmd]	78	1			T108	1		T109	2		T110	4
auto[TlIntgErrData]	89	1			T108	6		T109	2		T110	1
auto[TlIntgErrBoth]	93	1			T108	3		T109	6		T110	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80061916

1

T2

4459

T3

819200

T4

2340

auto[1]

85711942

1

T2

4548

T3

819200

T4

2236

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7966810	1			T2	3654		T4	1887		T5	6579
auto[TlIntgErrNone]	partial	auto[1]	8271651	1			T2	3750		T4	1798		T5	6652
auto[TlIntgErrNone]	full_word	auto[0]	72094988	1			T2	805		T3	819200		T4	453
auto[TlIntgErrNone]	full_word	auto[1]	77440149	1			T2	798		T3	819200		T4	438
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T109	1		T110	1		T115	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T108	1		T109	1		T110	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T124	1		T126	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T119	1		T125	1		-	-
auto[TlIntgErrData]	partial	auto[0]	47	1			T108	3		T109	1		T124	4
auto[TlIntgErrData]	partial	auto[1]	36	1			T108	2		T109	1		T110	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T125	1		T120	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T108	1		T119	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T109	4		T110	1		T124	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T108	3		T109	2		T110	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T127	1		T120	1		T128	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T129	1		T118	2		-	-