Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	999858	1			T2	7		T10	11832		T13	4276
auto[1]	10187074	1			T2	4		T4	268		T5	33550
auto[2]	787952	1			T2	3		T5	2		T10	11983
auto[3]	9956833	1			T2	6		T4	257		T5	33359

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13842035	1			T4	10		T5	55872		T8	48964
auto[1]	1986185	1			T2	1		T4	65		T5	5281
auto[2]	2023868	1			T4	56		T5	5286		T8	4990
auto[3]	4079629	1			T2	19		T4	394		T5	472

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9274396

1

T2

20

T4

525

T5

66911

auto[1]

12657321

1

T8

59311

T10

49721

T11

160985

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	389250	1			T20	4548		T134	2		T135	6
auto[0]	auto[0]	auto[1]	39647	1			T2	1		T10	1		T13	39
auto[0]	auto[0]	auto[2]	39746	1			T13	24		T20	482		T134	5
auto[0]	auto[0]	auto[3]	80786	1			T2	6		T13	4212		T20	41
auto[0]	auto[1]	auto[0]	2964786	1			T4	9		T5	28004		T8	12
auto[0]	auto[1]	auto[1]	329534	1			T4	47		T5	2497		T8	2
auto[0]	auto[1]	auto[2]	350493	1			T4	7		T5	2815		T8	2
auto[0]	auto[1]	auto[3]	596536	1			T2	4		T4	205		T5	234
auto[0]	auto[2]	auto[0]	291610	1			T5	2		T13	1		T20	2864
auto[0]	auto[2]	auto[1]	35254	1			T13	338		T20	285		T134	5
auto[0]	auto[2]	auto[2]	27173	1			T10	2		T13	34		T20	257
auto[0]	auto[2]	auto[3]	57809	1			T2	3		T10	3		T13	2946
auto[0]	auto[3]	auto[0]	2839225	1			T4	1		T5	27866		T8	17
auto[0]	auto[3]	auto[1]	332636	1			T4	18		T5	2784		T8	1
auto[0]	auto[3]	auto[2]	356246	1			T4	49		T5	2471		T8	1
auto[0]	auto[3]	auto[3]	543665	1			T2	6		T4	189		T5	238
auto[1]	auto[0]	auto[0]	14937	1			T10	405		T80	698		T136	349
auto[1]	auto[0]	auto[1]	66845	1			T10	1822		T80	2970		T136	1401
auto[1]	auto[0]	auto[2]	66701	1			T10	1760		T80	2921		T136	1418
auto[1]	auto[0]	auto[3]	301946	1			T10	7844		T13	1		T80	13192
auto[1]	auto[1]	auto[0]	3663557	1			T8	24426		T10	244		T11	67043
auto[1]	auto[1]	auto[1]	590239	1			T8	2450		T10	2023		T11	6035
auto[1]	auto[1]	auto[2]	547325	1			T8	2474		T10	1133		T11	6636
auto[1]	auto[1]	auto[3]	1144604	1			T8	232		T10	9305		T11	635
auto[1]	auto[2]	auto[0]	12434	1			T10	237		T80	359		T136	181
auto[1]	auto[2]	auto[1]	55436	1			T10	1077		T80	1769		T136	836
auto[1]	auto[2]	auto[2]	55963	1			T10	1952		T80	3106		T136	1389
auto[1]	auto[2]	auto[3]	252273	1			T10	8712		T80	14257		T136	6191
auto[1]	auto[3]	auto[0]	3666236	1			T8	24509		T10	87		T11	67502
auto[1]	auto[3]	auto[1]	536594	1			T8	2469		T10	404		T11	6612
auto[1]	auto[3]	auto[2]	580221	1			T8	2513		T10	2297		T11	5939
auto[1]	auto[3]	auto[3]	1102010	1			T8	238		T10	10419		T11	583