Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1170845445	148758	0	0
ctrl_regwen_rd_A	1170845445	10853	0	0
exec_rd_A	1170845445	9818	0	0
exec_regwen_rd_A	1170845445	11622	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170845445	148758	0	0
T6	121899	0	0	0
T7	145424	0	0	0
T30	813305	0	0	0
T33	51024	1234	0	0
T34	0	292	0	0
T35	0	2284	0	0
T48	0	1479	0	0
T49	0	2390	0	0
T50	0	1789	0	0
T51	0	2388	0	0
T52	0	3816	0	0
T53	0	1416	0	0
T54	0	1249	0	0
T55	760903	0	0	0
T56	41916	0	0	0
T57	639311	0	0	0
T58	206406	0	0	0
T59	75551	0	0	0
T60	75781	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170845445	10853	0	0
T6	121899	0	0	0
T7	145424	0	0	0
T30	813305	0	0	0
T33	51024	416	0	0
T34	0	228	0	0
T35	0	424	0	0
T44	0	992	0	0
T51	0	643	0	0
T52	0	747	0	0
T53	0	233	0	0
T55	760903	0	0	0
T56	41916	0	0	0
T57	639311	0	0	0
T58	206406	0	0	0
T59	75551	0	0	0
T60	75781	0	0	0
T112	0	1482	0	0
T113	0	193	0	0
T114	0	306	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170845445	9818	0	0
T6	121899	0	0	0
T7	145424	0	0	0
T30	813305	0	0	0
T33	51024	370	0	0
T34	0	188	0	0
T35	0	360	0	0
T44	0	1122	0	0
T51	0	485	0	0
T52	0	601	0	0
T53	0	155	0	0
T55	760903	0	0	0
T56	41916	0	0	0
T57	639311	0	0	0
T58	206406	0	0	0
T59	75551	0	0	0
T60	75781	0	0	0
T112	0	1602	0	0
T113	0	176	0	0
T114	0	307	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170845445	11622	0	0
T6	121899	0	0	0
T7	145424	0	0	0
T30	813305	0	0	0
T33	51024	477	0	0
T34	0	204	0	0
T35	0	387	0	0
T44	0	987	0	0
T51	0	572	0	0
T52	0	802	0	0
T53	0	190	0	0
T55	760903	0	0	0
T56	41916	0	0	0
T57	639311	0	0	0
T58	206406	0	0	0
T59	75551	0	0	0
T60	75781	0	0	0
T112	0	1631	0	0
T113	0	197	0	0
T114	0	291	0	0