| T795 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.4254676168 |
|
|
Mar 10 02:05:42 PM PDT 24 |
Mar 10 02:06:40 PM PDT 24 |
779105503 ps |
| T796 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2322148194 |
|
|
Mar 10 02:00:42 PM PDT 24 |
Mar 10 02:07:39 PM PDT 24 |
6007866149 ps |
| T797 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.704361481 |
|
|
Mar 10 02:01:42 PM PDT 24 |
Mar 10 02:06:36 PM PDT 24 |
17242348637 ps |
| T798 |
/workspace/coverage/default/20.sram_ctrl_executable.284722827 |
|
|
Mar 10 02:01:57 PM PDT 24 |
Mar 10 02:27:54 PM PDT 24 |
95872609308 ps |
| T799 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1474932964 |
|
|
Mar 10 02:00:51 PM PDT 24 |
Mar 10 02:01:58 PM PDT 24 |
1523003163 ps |
| T800 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1250162421 |
|
|
Mar 10 02:02:45 PM PDT 24 |
Mar 10 02:02:56 PM PDT 24 |
4543607124 ps |
| T801 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1088177355 |
|
|
Mar 10 02:00:52 PM PDT 24 |
Mar 10 03:43:26 PM PDT 24 |
76826084464 ps |
| T802 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.1935807364 |
|
|
Mar 10 02:04:16 PM PDT 24 |
Mar 10 02:04:20 PM PDT 24 |
1407248994 ps |
| T803 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1927875228 |
|
|
Mar 10 02:02:34 PM PDT 24 |
Mar 10 02:06:35 PM PDT 24 |
15762827665 ps |
| T804 |
/workspace/coverage/default/46.sram_ctrl_executable.3051257135 |
|
|
Mar 10 02:05:54 PM PDT 24 |
Mar 10 02:21:52 PM PDT 24 |
28532067939 ps |
| T805 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1492812187 |
|
|
Mar 10 02:00:48 PM PDT 24 |
Mar 10 02:11:04 PM PDT 24 |
23901627891 ps |
| T806 |
/workspace/coverage/default/48.sram_ctrl_partial_access.776265458 |
|
|
Mar 10 02:06:14 PM PDT 24 |
Mar 10 02:07:37 PM PDT 24 |
1981209826 ps |
| T807 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.3592637156 |
|
|
Mar 10 02:04:10 PM PDT 24 |
Mar 10 02:29:06 PM PDT 24 |
12437256762 ps |
| T808 |
/workspace/coverage/default/10.sram_ctrl_bijection.3585460436 |
|
|
Mar 10 02:00:51 PM PDT 24 |
Mar 10 02:41:22 PM PDT 24 |
537261980747 ps |
| T809 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.2082172254 |
|
|
Mar 10 02:02:01 PM PDT 24 |
Mar 10 02:04:00 PM PDT 24 |
1502144436 ps |
| T810 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1881804417 |
|
|
Mar 10 02:02:59 PM PDT 24 |
Mar 10 02:03:20 PM PDT 24 |
1137209940 ps |
| T811 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1976428113 |
|
|
Mar 10 02:03:41 PM PDT 24 |
Mar 10 02:04:06 PM PDT 24 |
1648053764 ps |
| T812 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3983992726 |
|
|
Mar 10 02:01:35 PM PDT 24 |
Mar 10 02:05:13 PM PDT 24 |
6763961506 ps |
| T813 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1999468397 |
|
|
Mar 10 02:03:56 PM PDT 24 |
Mar 10 02:06:11 PM PDT 24 |
21930177260 ps |
| T814 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1119005045 |
|
|
Mar 10 02:02:07 PM PDT 24 |
Mar 10 02:02:43 PM PDT 24 |
5333199961 ps |
| T815 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.1412080674 |
|
|
Mar 10 02:02:03 PM PDT 24 |
Mar 10 02:23:57 PM PDT 24 |
84331947262 ps |
| T816 |
/workspace/coverage/default/44.sram_ctrl_smoke.714279676 |
|
|
Mar 10 02:05:30 PM PDT 24 |
Mar 10 02:07:01 PM PDT 24 |
1281455757 ps |
| T817 |
/workspace/coverage/default/1.sram_ctrl_alert_test.1230597932 |
|
|
Mar 10 02:00:33 PM PDT 24 |
Mar 10 02:00:34 PM PDT 24 |
24726748 ps |
| T818 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.905307704 |
|
|
Mar 10 02:00:26 PM PDT 24 |
Mar 10 02:14:00 PM PDT 24 |
35727484395 ps |
| T819 |
/workspace/coverage/default/22.sram_ctrl_smoke.4144891592 |
|
|
Mar 10 02:02:08 PM PDT 24 |
Mar 10 02:02:22 PM PDT 24 |
872861998 ps |
| T820 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.1896283331 |
|
|
Mar 10 02:05:59 PM PDT 24 |
Mar 10 02:11:13 PM PDT 24 |
41340117189 ps |
| T821 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.143285060 |
|
|
Mar 10 02:00:45 PM PDT 24 |
Mar 10 02:01:21 PM PDT 24 |
1822752676 ps |
| T822 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1513879540 |
|
|
Mar 10 02:00:49 PM PDT 24 |
Mar 10 02:04:39 PM PDT 24 |
8001814546 ps |
| T823 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.3034589107 |
|
|
Mar 10 02:01:38 PM PDT 24 |
Mar 10 02:12:59 PM PDT 24 |
7918618163 ps |
| T824 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3800868758 |
|
|
Mar 10 02:05:03 PM PDT 24 |
Mar 10 02:06:28 PM PDT 24 |
819443192 ps |
| T825 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2312645351 |
|
|
Mar 10 02:06:21 PM PDT 24 |
Mar 10 02:08:59 PM PDT 24 |
27542382400 ps |
| T826 |
/workspace/coverage/default/34.sram_ctrl_smoke.2492747185 |
|
|
Mar 10 02:03:46 PM PDT 24 |
Mar 10 02:04:44 PM PDT 24 |
2939682273 ps |
| T827 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1605940319 |
|
|
Mar 10 02:02:28 PM PDT 24 |
Mar 10 02:13:33 PM PDT 24 |
18446548852 ps |
| T828 |
/workspace/coverage/default/2.sram_ctrl_smoke.1126993570 |
|
|
Mar 10 02:00:37 PM PDT 24 |
Mar 10 02:01:59 PM PDT 24 |
1000470403 ps |
| T829 |
/workspace/coverage/default/38.sram_ctrl_alert_test.2391131018 |
|
|
Mar 10 02:04:37 PM PDT 24 |
Mar 10 02:04:38 PM PDT 24 |
41703163 ps |
| T830 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3813134546 |
|
|
Mar 10 02:01:22 PM PDT 24 |
Mar 10 02:01:23 PM PDT 24 |
23719439 ps |
| T831 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1695612470 |
|
|
Mar 10 02:01:25 PM PDT 24 |
Mar 10 02:01:35 PM PDT 24 |
1480906506 ps |
| T832 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1047699777 |
|
|
Mar 10 02:01:57 PM PDT 24 |
Mar 10 02:02:01 PM PDT 24 |
3351646027 ps |
| T833 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.287312121 |
|
|
Mar 10 02:03:41 PM PDT 24 |
Mar 10 02:13:40 PM PDT 24 |
48539316363 ps |
| T834 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3280716261 |
|
|
Mar 10 02:03:37 PM PDT 24 |
Mar 10 02:03:41 PM PDT 24 |
1540170395 ps |
| T835 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.4078490720 |
|
|
Mar 10 02:05:56 PM PDT 24 |
Mar 10 02:13:37 PM PDT 24 |
134082117359 ps |
| T836 |
/workspace/coverage/default/4.sram_ctrl_regwen.4121493634 |
|
|
Mar 10 02:00:47 PM PDT 24 |
Mar 10 02:36:49 PM PDT 24 |
300861473132 ps |
| T837 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3037015106 |
|
|
Mar 10 02:04:26 PM PDT 24 |
Mar 10 02:06:26 PM PDT 24 |
1907773916 ps |
| T838 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.774646307 |
|
|
Mar 10 02:00:30 PM PDT 24 |
Mar 10 02:06:27 PM PDT 24 |
21754513527 ps |
| T839 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2600501989 |
|
|
Mar 10 02:00:44 PM PDT 24 |
Mar 10 02:00:50 PM PDT 24 |
2502735689 ps |
| T840 |
/workspace/coverage/default/15.sram_ctrl_bijection.1527620988 |
|
|
Mar 10 02:01:20 PM PDT 24 |
Mar 10 02:14:34 PM PDT 24 |
51123213008 ps |
| T841 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.580989772 |
|
|
Mar 10 02:05:38 PM PDT 24 |
Mar 10 02:12:46 PM PDT 24 |
48861011180 ps |
| T842 |
/workspace/coverage/default/19.sram_ctrl_alert_test.514286110 |
|
|
Mar 10 02:01:51 PM PDT 24 |
Mar 10 02:01:52 PM PDT 24 |
69725072 ps |
| T843 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3611367510 |
|
|
Mar 10 02:03:36 PM PDT 24 |
Mar 10 02:21:58 PM PDT 24 |
15817548000 ps |
| T844 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3208439999 |
|
|
Mar 10 02:00:32 PM PDT 24 |
Mar 10 02:01:08 PM PDT 24 |
3899617064 ps |
| T845 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.4002101624 |
|
|
Mar 10 02:03:42 PM PDT 24 |
Mar 10 02:05:50 PM PDT 24 |
2959912382 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_partial_access.215511749 |
|
|
Mar 10 02:01:33 PM PDT 24 |
Mar 10 02:01:44 PM PDT 24 |
912497667 ps |
| T847 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1204523236 |
|
|
Mar 10 02:01:47 PM PDT 24 |
Mar 10 02:06:27 PM PDT 24 |
13816678018 ps |
| T848 |
/workspace/coverage/default/8.sram_ctrl_executable.4178396570 |
|
|
Mar 10 02:00:45 PM PDT 24 |
Mar 10 02:08:46 PM PDT 24 |
35332576119 ps |
| T849 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.2121379471 |
|
|
Mar 10 02:01:47 PM PDT 24 |
Mar 10 02:03:09 PM PDT 24 |
4270794121 ps |
| T850 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.930510431 |
|
|
Mar 10 02:03:02 PM PDT 24 |
Mar 10 02:14:02 PM PDT 24 |
14906535508 ps |
| T851 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3167233833 |
|
|
Mar 10 02:01:55 PM PDT 24 |
Mar 10 03:54:50 PM PDT 24 |
125706203788 ps |
| T852 |
/workspace/coverage/default/17.sram_ctrl_executable.3548797046 |
|
|
Mar 10 02:01:38 PM PDT 24 |
Mar 10 02:16:42 PM PDT 24 |
5871124040 ps |
| T853 |
/workspace/coverage/default/17.sram_ctrl_regwen.3201733604 |
|
|
Mar 10 02:01:35 PM PDT 24 |
Mar 10 02:10:38 PM PDT 24 |
8449756030 ps |
| T854 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.792872714 |
|
|
Mar 10 02:04:56 PM PDT 24 |
Mar 10 02:05:13 PM PDT 24 |
4023604056 ps |
| T855 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1078861783 |
|
|
Mar 10 02:05:16 PM PDT 24 |
Mar 10 02:07:05 PM PDT 24 |
1041666921 ps |
| T856 |
/workspace/coverage/default/4.sram_ctrl_stress_all.2556960388 |
|
|
Mar 10 02:00:43 PM PDT 24 |
Mar 10 04:02:21 PM PDT 24 |
260689808374 ps |
| T857 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1180008549 |
|
|
Mar 10 02:05:02 PM PDT 24 |
Mar 10 02:05:05 PM PDT 24 |
360360719 ps |
| T858 |
/workspace/coverage/default/11.sram_ctrl_partial_access.1051547552 |
|
|
Mar 10 02:00:58 PM PDT 24 |
Mar 10 02:03:13 PM PDT 24 |
2097182327 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3181690852 |
|
|
Mar 10 02:05:14 PM PDT 24 |
Mar 10 03:57:04 PM PDT 24 |
329869901352 ps |
| T860 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1011476162 |
|
|
Mar 10 02:01:20 PM PDT 24 |
Mar 10 02:04:27 PM PDT 24 |
11093945346 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2467574016 |
|
|
Mar 10 02:04:10 PM PDT 24 |
Mar 10 02:06:41 PM PDT 24 |
3259918626 ps |
| T862 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.4216698906 |
|
|
Mar 10 02:00:49 PM PDT 24 |
Mar 10 02:05:12 PM PDT 24 |
16413098749 ps |
| T863 |
/workspace/coverage/default/48.sram_ctrl_executable.1924189342 |
|
|
Mar 10 02:06:23 PM PDT 24 |
Mar 10 02:17:28 PM PDT 24 |
62847818801 ps |
| T864 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.4125969688 |
|
|
Mar 10 02:04:57 PM PDT 24 |
Mar 10 02:05:02 PM PDT 24 |
3364661598 ps |
| T865 |
/workspace/coverage/default/41.sram_ctrl_smoke.1354543012 |
|
|
Mar 10 02:04:58 PM PDT 24 |
Mar 10 02:05:10 PM PDT 24 |
1948507446 ps |
| T866 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.903208354 |
|
|
Mar 10 02:00:54 PM PDT 24 |
Mar 10 02:09:30 PM PDT 24 |
23747046963 ps |
| T867 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.555913270 |
|
|
Mar 10 02:02:36 PM PDT 24 |
Mar 10 02:25:58 PM PDT 24 |
22777328467 ps |
| T868 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1026872210 |
|
|
Mar 10 02:02:55 PM PDT 24 |
Mar 10 02:29:52 PM PDT 24 |
22034262968 ps |
| T869 |
/workspace/coverage/default/22.sram_ctrl_alert_test.4141510625 |
|
|
Mar 10 02:02:18 PM PDT 24 |
Mar 10 02:02:19 PM PDT 24 |
28091858 ps |
| T870 |
/workspace/coverage/default/23.sram_ctrl_executable.3573493673 |
|
|
Mar 10 02:02:24 PM PDT 24 |
Mar 10 02:04:35 PM PDT 24 |
20351940689 ps |
| T871 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2290997531 |
|
|
Mar 10 02:01:21 PM PDT 24 |
Mar 10 02:02:01 PM PDT 24 |
1332645790 ps |
| T872 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.3960024618 |
|
|
Mar 10 02:03:47 PM PDT 24 |
Mar 10 02:08:43 PM PDT 24 |
57347327261 ps |
| T873 |
/workspace/coverage/default/30.sram_ctrl_regwen.2837274592 |
|
|
Mar 10 02:03:19 PM PDT 24 |
Mar 10 02:13:24 PM PDT 24 |
3852705700 ps |
| T874 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.889650 |
|
|
Mar 10 02:03:10 PM PDT 24 |
Mar 10 02:05:11 PM PDT 24 |
6252234871 ps |
| T875 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.943619685 |
|
|
Mar 10 02:02:31 PM PDT 24 |
Mar 10 02:10:17 PM PDT 24 |
69303502018 ps |
| T876 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2616023281 |
|
|
Mar 10 02:00:36 PM PDT 24 |
Mar 10 02:01:51 PM PDT 24 |
2471428206 ps |
| T877 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.501960884 |
|
|
Mar 10 02:03:15 PM PDT 24 |
Mar 10 02:20:07 PM PDT 24 |
48454534830 ps |
| T878 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2801611826 |
|
|
Mar 10 02:01:42 PM PDT 24 |
Mar 10 02:03:09 PM PDT 24 |
1287746125 ps |
| T879 |
/workspace/coverage/default/34.sram_ctrl_regwen.347380979 |
|
|
Mar 10 02:03:52 PM PDT 24 |
Mar 10 02:19:27 PM PDT 24 |
21108168820 ps |
| T880 |
/workspace/coverage/default/35.sram_ctrl_smoke.65465655 |
|
|
Mar 10 02:03:57 PM PDT 24 |
Mar 10 02:04:10 PM PDT 24 |
466312923 ps |
| T881 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.3102890361 |
|
|
Mar 10 02:01:40 PM PDT 24 |
Mar 10 02:02:21 PM PDT 24 |
3016589181 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_alert_test.2997499499 |
|
|
Mar 10 02:04:15 PM PDT 24 |
Mar 10 02:04:16 PM PDT 24 |
33707633 ps |
| T883 |
/workspace/coverage/default/17.sram_ctrl_bijection.2842753549 |
|
|
Mar 10 02:01:33 PM PDT 24 |
Mar 10 02:11:00 PM PDT 24 |
36210104791 ps |
| T884 |
/workspace/coverage/default/45.sram_ctrl_smoke.2267900817 |
|
|
Mar 10 02:05:37 PM PDT 24 |
Mar 10 02:05:50 PM PDT 24 |
1888499833 ps |
| T885 |
/workspace/coverage/default/35.sram_ctrl_regwen.923927856 |
|
|
Mar 10 02:04:08 PM PDT 24 |
Mar 10 02:06:11 PM PDT 24 |
1552683812 ps |
| T886 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1601420904 |
|
|
Mar 10 02:01:20 PM PDT 24 |
Mar 10 02:01:23 PM PDT 24 |
362303134 ps |
| T887 |
/workspace/coverage/default/45.sram_ctrl_regwen.3251222659 |
|
|
Mar 10 02:05:50 PM PDT 24 |
Mar 10 02:25:13 PM PDT 24 |
33488404899 ps |
| T888 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1988806168 |
|
|
Mar 10 02:03:32 PM PDT 24 |
Mar 10 02:09:06 PM PDT 24 |
11007836622 ps |
| T889 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3298908513 |
|
|
Mar 10 02:05:17 PM PDT 24 |
Mar 10 02:28:42 PM PDT 24 |
18866826687 ps |
| T890 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.442316045 |
|
|
Mar 10 02:03:55 PM PDT 24 |
Mar 10 02:04:11 PM PDT 24 |
509324708 ps |
| T891 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2177441838 |
|
|
Mar 10 02:02:01 PM PDT 24 |
Mar 10 04:06:45 PM PDT 24 |
1169961417233 ps |
| T892 |
/workspace/coverage/default/11.sram_ctrl_regwen.3862253266 |
|
|
Mar 10 02:01:01 PM PDT 24 |
Mar 10 02:19:43 PM PDT 24 |
13631848696 ps |
| T893 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1281306471 |
|
|
Mar 10 02:00:34 PM PDT 24 |
Mar 10 02:05:21 PM PDT 24 |
17620009220 ps |
| T894 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2149514866 |
|
|
Mar 10 02:03:14 PM PDT 24 |
Mar 10 02:03:41 PM PDT 24 |
2856194600 ps |
| T895 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.1285651561 |
|
|
Mar 10 02:01:26 PM PDT 24 |
Mar 10 02:10:42 PM PDT 24 |
146053842731 ps |
| T896 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1225283783 |
|
|
Mar 10 02:05:37 PM PDT 24 |
Mar 10 02:12:25 PM PDT 24 |
32376069833 ps |
| T897 |
/workspace/coverage/default/25.sram_ctrl_executable.4175788702 |
|
|
Mar 10 02:02:36 PM PDT 24 |
Mar 10 02:18:03 PM PDT 24 |
12629724663 ps |
| T898 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2318852197 |
|
|
Mar 10 02:02:27 PM PDT 24 |
Mar 10 02:04:35 PM PDT 24 |
5717902249 ps |
| T899 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.4053245085 |
|
|
Mar 10 02:00:52 PM PDT 24 |
Mar 10 02:02:44 PM PDT 24 |
5596297428 ps |
| T900 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1745354385 |
|
|
Mar 10 02:04:25 PM PDT 24 |
Mar 10 03:13:29 PM PDT 24 |
259562459484 ps |
| T901 |
/workspace/coverage/default/24.sram_ctrl_regwen.1272058133 |
|
|
Mar 10 02:02:37 PM PDT 24 |
Mar 10 02:04:53 PM PDT 24 |
6209727849 ps |
| T902 |
/workspace/coverage/default/34.sram_ctrl_executable.3953748649 |
|
|
Mar 10 02:03:50 PM PDT 24 |
Mar 10 02:30:47 PM PDT 24 |
19243936040 ps |
| T903 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.2943656908 |
|
|
Mar 10 02:04:39 PM PDT 24 |
Mar 10 02:05:45 PM PDT 24 |
971229425 ps |
| T904 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2992423629 |
|
|
Mar 10 02:02:55 PM PDT 24 |
Mar 10 02:04:25 PM PDT 24 |
6289710592 ps |
| T905 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.234860969 |
|
|
Mar 10 02:02:01 PM PDT 24 |
Mar 10 02:07:17 PM PDT 24 |
24696434432 ps |
| T906 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.4038899315 |
|
|
Mar 10 02:02:37 PM PDT 24 |
Mar 10 02:22:03 PM PDT 24 |
98158362440 ps |
| T907 |
/workspace/coverage/default/30.sram_ctrl_stress_all.957378929 |
|
|
Mar 10 02:03:25 PM PDT 24 |
Mar 10 03:10:04 PM PDT 24 |
50192417318 ps |
| T908 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.622102774 |
|
|
Mar 10 02:04:15 PM PDT 24 |
Mar 10 02:08:12 PM PDT 24 |
9762573840 ps |
| T909 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2458330108 |
|
|
Mar 10 02:00:50 PM PDT 24 |
Mar 10 02:01:08 PM PDT 24 |
1157373176 ps |
| T910 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3277904214 |
|
|
Mar 10 02:03:24 PM PDT 24 |
Mar 10 02:03:44 PM PDT 24 |
8730206781 ps |
| T911 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.1645508487 |
|
|
Mar 10 02:03:02 PM PDT 24 |
Mar 10 02:05:55 PM PDT 24 |
7411764460 ps |
| T912 |
/workspace/coverage/default/38.sram_ctrl_regwen.3349008605 |
|
|
Mar 10 02:04:34 PM PDT 24 |
Mar 10 02:18:50 PM PDT 24 |
51261810040 ps |
| T913 |
/workspace/coverage/default/38.sram_ctrl_smoke.76855922 |
|
|
Mar 10 02:04:25 PM PDT 24 |
Mar 10 02:04:35 PM PDT 24 |
450089347 ps |
| T914 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2955698430 |
|
|
Mar 10 02:00:59 PM PDT 24 |
Mar 10 02:20:39 PM PDT 24 |
119670286384 ps |
| T915 |
/workspace/coverage/default/43.sram_ctrl_bijection.2557440752 |
|
|
Mar 10 02:05:17 PM PDT 24 |
Mar 10 02:14:27 PM PDT 24 |
97111855363 ps |
| T916 |
/workspace/coverage/default/6.sram_ctrl_regwen.2366927203 |
|
|
Mar 10 02:00:50 PM PDT 24 |
Mar 10 02:06:56 PM PDT 24 |
5799482451 ps |
| T917 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.1417252736 |
|
|
Mar 10 02:00:54 PM PDT 24 |
Mar 10 02:19:16 PM PDT 24 |
23755638283 ps |
| T918 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2545651362 |
|
|
Mar 10 02:04:38 PM PDT 24 |
Mar 10 04:11:54 PM PDT 24 |
173515561543 ps |
| T919 |
/workspace/coverage/default/18.sram_ctrl_bijection.2892150574 |
|
|
Mar 10 02:01:43 PM PDT 24 |
Mar 10 02:35:10 PM PDT 24 |
91133673545 ps |
| T920 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3714278268 |
|
|
Mar 10 02:05:38 PM PDT 24 |
Mar 10 02:07:45 PM PDT 24 |
13163318734 ps |
| T921 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1016655456 |
|
|
Mar 10 02:00:44 PM PDT 24 |
Mar 10 02:01:20 PM PDT 24 |
1323448584 ps |
| T922 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1298302476 |
|
|
Mar 10 02:06:31 PM PDT 24 |
Mar 10 02:22:43 PM PDT 24 |
15212064213 ps |
| T923 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1809861341 |
|
|
Mar 10 02:00:44 PM PDT 24 |
Mar 10 02:00:46 PM PDT 24 |
13179678 ps |
| T924 |
/workspace/coverage/default/0.sram_ctrl_bijection.286311557 |
|
|
Mar 10 02:00:28 PM PDT 24 |
Mar 10 02:22:49 PM PDT 24 |
950690445993 ps |
| T925 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3584395354 |
|
|
Mar 10 02:01:42 PM PDT 24 |
Mar 10 02:04:10 PM PDT 24 |
86045205501 ps |
| T926 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.915881328 |
|
|
Mar 10 02:06:10 PM PDT 24 |
Mar 10 02:08:12 PM PDT 24 |
2041419413 ps |
| T927 |
/workspace/coverage/default/1.sram_ctrl_stress_all.905442214 |
|
|
Mar 10 02:00:36 PM PDT 24 |
Mar 10 03:30:37 PM PDT 24 |
148776626938 ps |
| T928 |
/workspace/coverage/default/4.sram_ctrl_alert_test.345717297 |
|
|
Mar 10 02:00:45 PM PDT 24 |
Mar 10 02:00:47 PM PDT 24 |
14334475 ps |
| T929 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3705619652 |
|
|
Mar 10 02:03:02 PM PDT 24 |
Mar 10 02:06:58 PM PDT 24 |
4936390504 ps |
| T930 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.523990003 |
|
|
Mar 10 02:03:51 PM PDT 24 |
Mar 10 02:05:39 PM PDT 24 |
7534892255 ps |
| T931 |
/workspace/coverage/default/40.sram_ctrl_smoke.2504398736 |
|
|
Mar 10 02:04:47 PM PDT 24 |
Mar 10 02:05:12 PM PDT 24 |
1741735307 ps |
| T932 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1632009348 |
|
|
Mar 10 02:03:50 PM PDT 24 |
Mar 10 02:05:32 PM PDT 24 |
3175973502 ps |
| T933 |
/workspace/coverage/default/3.sram_ctrl_executable.2187925707 |
|
|
Mar 10 02:00:47 PM PDT 24 |
Mar 10 02:04:18 PM PDT 24 |
4551014155 ps |
| T934 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.990301471 |
|
|
Mar 10 02:00:27 PM PDT 24 |
Mar 10 02:00:55 PM PDT 24 |
2279624769 ps |
| T935 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.4098772261 |
|
|
Mar 10 02:06:20 PM PDT 24 |
Mar 10 02:08:02 PM PDT 24 |
1591484073 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3221935298 |
|
|
Mar 10 01:11:25 PM PDT 24 |
Mar 10 01:11:27 PM PDT 24 |
90991979 ps |
| T111 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3714428641 |
|
|
Mar 10 01:11:21 PM PDT 24 |
Mar 10 01:11:22 PM PDT 24 |
37625269 ps |
| T107 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3699138583 |
|
|
Mar 10 01:11:24 PM PDT 24 |
Mar 10 01:11:26 PM PDT 24 |
30426560 ps |
| T936 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1185657786 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:37 PM PDT 24 |
361987037 ps |
| T937 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1424799653 |
|
|
Mar 10 01:11:34 PM PDT 24 |
Mar 10 01:11:38 PM PDT 24 |
156351295 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3786433022 |
|
|
Mar 10 01:11:20 PM PDT 24 |
Mar 10 01:11:22 PM PDT 24 |
348763156 ps |
| T65 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2124080511 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:12:11 PM PDT 24 |
61611005993 ps |
| T66 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2654238946 |
|
|
Mar 10 01:11:43 PM PDT 24 |
Mar 10 01:12:11 PM PDT 24 |
15401518517 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2203383688 |
|
|
Mar 10 01:11:25 PM PDT 24 |
Mar 10 01:11:26 PM PDT 24 |
13963863 ps |
| T103 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3531987612 |
|
|
Mar 10 01:11:38 PM PDT 24 |
Mar 10 01:11:39 PM PDT 24 |
16044933 ps |
| T109 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2586409870 |
|
|
Mar 10 01:11:37 PM PDT 24 |
Mar 10 01:11:39 PM PDT 24 |
546826411 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4242395386 |
|
|
Mar 10 01:11:22 PM PDT 24 |
Mar 10 01:11:24 PM PDT 24 |
168490229 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.882447787 |
|
|
Mar 10 01:11:34 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
12860356 ps |
| T938 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2684678402 |
|
|
Mar 10 01:11:33 PM PDT 24 |
Mar 10 01:11:37 PM PDT 24 |
117112066 ps |
| T939 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3293197459 |
|
|
Mar 10 01:11:27 PM PDT 24 |
Mar 10 01:11:32 PM PDT 24 |
124470080 ps |
| T940 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4091736825 |
|
|
Mar 10 01:11:27 PM PDT 24 |
Mar 10 01:11:32 PM PDT 24 |
359475869 ps |
| T941 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3441139962 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:11:26 PM PDT 24 |
1409871522 ps |
| T69 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1574131568 |
|
|
Mar 10 01:11:29 PM PDT 24 |
Mar 10 01:11:30 PM PDT 24 |
13394958 ps |
| T942 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.73101871 |
|
|
Mar 10 01:11:40 PM PDT 24 |
Mar 10 01:11:44 PM PDT 24 |
365754046 ps |
| T943 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3334106761 |
|
|
Mar 10 01:11:21 PM PDT 24 |
Mar 10 01:11:25 PM PDT 24 |
1367884191 ps |
| T70 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.328043064 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:12:01 PM PDT 24 |
14244621153 ps |
| T104 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1329664400 |
|
|
Mar 10 01:11:36 PM PDT 24 |
Mar 10 01:11:37 PM PDT 24 |
14050861 ps |
| T71 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4073162964 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:12:05 PM PDT 24 |
36914714051 ps |
| T72 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2978143337 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:33 PM PDT 24 |
21185645 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2682484237 |
|
|
Mar 10 01:11:21 PM PDT 24 |
Mar 10 01:11:22 PM PDT 24 |
63988023 ps |
| T944 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2016854934 |
|
|
Mar 10 01:11:29 PM PDT 24 |
Mar 10 01:11:32 PM PDT 24 |
23878591 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.439993482 |
|
|
Mar 10 01:11:21 PM PDT 24 |
Mar 10 01:11:22 PM PDT 24 |
13251877 ps |
| T945 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2740242099 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:35 PM PDT 24 |
12901355 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4070385786 |
|
|
Mar 10 01:11:19 PM PDT 24 |
Mar 10 01:12:08 PM PDT 24 |
14163334372 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1485067956 |
|
|
Mar 10 01:11:37 PM PDT 24 |
Mar 10 01:11:41 PM PDT 24 |
694808205 ps |
| T947 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.54672562 |
|
|
Mar 10 01:11:33 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
29501808 ps |
| T948 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2929776005 |
|
|
Mar 10 01:11:38 PM PDT 24 |
Mar 10 01:11:42 PM PDT 24 |
33311522 ps |
| T949 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.616718354 |
|
|
Mar 10 01:11:27 PM PDT 24 |
Mar 10 01:11:30 PM PDT 24 |
82396933 ps |
| T124 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1609803935 |
|
|
Mar 10 01:11:25 PM PDT 24 |
Mar 10 01:11:26 PM PDT 24 |
293499582 ps |
| T115 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3032964372 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:11:25 PM PDT 24 |
286289640 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1569672138 |
|
|
Mar 10 01:11:28 PM PDT 24 |
Mar 10 01:11:29 PM PDT 24 |
19384756 ps |
| T119 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2374790514 |
|
|
Mar 10 01:11:40 PM PDT 24 |
Mar 10 01:11:42 PM PDT 24 |
272165299 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2453827104 |
|
|
Mar 10 01:11:25 PM PDT 24 |
Mar 10 01:11:30 PM PDT 24 |
851292395 ps |
| T952 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.310049359 |
|
|
Mar 10 01:11:43 PM PDT 24 |
Mar 10 01:11:46 PM PDT 24 |
356764872 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1541175887 |
|
|
Mar 10 01:11:39 PM PDT 24 |
Mar 10 01:12:29 PM PDT 24 |
28368365902 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2952191359 |
|
|
Mar 10 01:11:26 PM PDT 24 |
Mar 10 01:11:29 PM PDT 24 |
354657072 ps |
| T955 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4214576605 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:40 PM PDT 24 |
5918950770 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1451994086 |
|
|
Mar 10 01:11:39 PM PDT 24 |
Mar 10 01:11:42 PM PDT 24 |
111401168 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2177059867 |
|
|
Mar 10 01:11:35 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
57579329 ps |
| T126 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2427931968 |
|
|
Mar 10 01:11:41 PM PDT 24 |
Mar 10 01:11:42 PM PDT 24 |
298986026 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2149591588 |
|
|
Mar 10 01:11:17 PM PDT 24 |
Mar 10 01:11:17 PM PDT 24 |
29600767 ps |
| T959 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2529317352 |
|
|
Mar 10 01:11:33 PM PDT 24 |
Mar 10 01:11:35 PM PDT 24 |
13801956 ps |
| T960 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1189755502 |
|
|
Mar 10 01:11:17 PM PDT 24 |
Mar 10 01:11:20 PM PDT 24 |
37637580 ps |
| T84 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2685981644 |
|
|
Mar 10 01:11:33 PM PDT 24 |
Mar 10 01:12:00 PM PDT 24 |
8577155629 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4055752156 |
|
|
Mar 10 01:11:40 PM PDT 24 |
Mar 10 01:11:43 PM PDT 24 |
107220645 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3660287576 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:11:23 PM PDT 24 |
14521612 ps |
| T121 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1434943921 |
|
|
Mar 10 01:11:34 PM PDT 24 |
Mar 10 01:11:37 PM PDT 24 |
352819851 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.461309102 |
|
|
Mar 10 01:11:41 PM PDT 24 |
Mar 10 01:11:45 PM PDT 24 |
1396902918 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2362257431 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:11:25 PM PDT 24 |
138331834 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2891548637 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:12:09 PM PDT 24 |
7248547443 ps |
| T86 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2411165485 |
|
|
Mar 10 01:11:34 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
27829549 ps |
| T125 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2698377659 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
429860850 ps |
| T965 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4008518717 |
|
|
Mar 10 01:11:21 PM PDT 24 |
Mar 10 01:11:22 PM PDT 24 |
36689807 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2788231084 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:38 PM PDT 24 |
1422388880 ps |
| T967 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.4160912285 |
|
|
Mar 10 01:11:39 PM PDT 24 |
Mar 10 01:11:40 PM PDT 24 |
17480669 ps |
| T127 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3084265542 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:34 PM PDT 24 |
428889766 ps |
| T120 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1470575058 |
|
|
Mar 10 01:11:34 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
251288609 ps |
| T968 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3108549326 |
|
|
Mar 10 01:11:37 PM PDT 24 |
Mar 10 01:11:38 PM PDT 24 |
22646419 ps |
| T87 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1494547042 |
|
|
Mar 10 01:11:38 PM PDT 24 |
Mar 10 01:11:39 PM PDT 24 |
35691379 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1735249602 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:33 PM PDT 24 |
370255772 ps |
| T122 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2699363354 |
|
|
Mar 10 01:11:40 PM PDT 24 |
Mar 10 01:11:43 PM PDT 24 |
489668933 ps |
| T116 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2233931958 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:34 PM PDT 24 |
223908496 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3302207612 |
|
|
Mar 10 01:11:28 PM PDT 24 |
Mar 10 01:11:34 PM PDT 24 |
3876301140 ps |
| T88 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.995099264 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:58 PM PDT 24 |
16140450508 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.336637236 |
|
|
Mar 10 01:11:20 PM PDT 24 |
Mar 10 01:11:21 PM PDT 24 |
89092267 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2710329835 |
|
|
Mar 10 01:11:21 PM PDT 24 |
Mar 10 01:11:22 PM PDT 24 |
99859853 ps |
| T973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3769280010 |
|
|
Mar 10 01:11:41 PM PDT 24 |
Mar 10 01:11:42 PM PDT 24 |
25119391 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4165898639 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:34 PM PDT 24 |
16123597 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.12842144 |
|
|
Mar 10 01:11:30 PM PDT 24 |
Mar 10 01:12:20 PM PDT 24 |
7249987058 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.439918496 |
|
|
Mar 10 01:11:22 PM PDT 24 |
Mar 10 01:11:26 PM PDT 24 |
1765091383 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3112508359 |
|
|
Mar 10 01:11:29 PM PDT 24 |
Mar 10 01:12:20 PM PDT 24 |
29432357144 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2533086215 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
208241901 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2698117038 |
|
|
Mar 10 01:11:34 PM PDT 24 |
Mar 10 01:11:36 PM PDT 24 |
28170060 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.493167032 |
|
|
Mar 10 01:11:30 PM PDT 24 |
Mar 10 01:11:33 PM PDT 24 |
364417410 ps |
| T99 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3332867410 |
|
|
Mar 10 01:11:40 PM PDT 24 |
Mar 10 01:12:26 PM PDT 24 |
7455900816 ps |
| T95 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3488698853 |
|
|
Mar 10 01:11:26 PM PDT 24 |
Mar 10 01:11:54 PM PDT 24 |
3703633993 ps |
| T980 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1113231088 |
|
|
Mar 10 01:11:22 PM PDT 24 |
Mar 10 01:11:23 PM PDT 24 |
54680935 ps |
| T981 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3867847372 |
|
|
Mar 10 01:11:40 PM PDT 24 |
Mar 10 01:11:44 PM PDT 24 |
286654897 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1925974743 |
|
|
Mar 10 01:11:40 PM PDT 24 |
Mar 10 01:11:41 PM PDT 24 |
30714829 ps |
| T100 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3314622935 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:12:04 PM PDT 24 |
16808494484 ps |
| T983 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2654317415 |
|
|
Mar 10 01:11:33 PM PDT 24 |
Mar 10 01:11:35 PM PDT 24 |
44381370 ps |
| T96 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2778148504 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:11:52 PM PDT 24 |
15402811260 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3167849785 |
|
|
Mar 10 01:11:29 PM PDT 24 |
Mar 10 01:11:30 PM PDT 24 |
78720742 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.238839566 |
|
|
Mar 10 01:11:44 PM PDT 24 |
Mar 10 01:11:49 PM PDT 24 |
700498505 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.622110151 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:37 PM PDT 24 |
89655235 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.856745660 |
|
|
Mar 10 01:11:17 PM PDT 24 |
Mar 10 01:11:19 PM PDT 24 |
112949050 ps |
| T117 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1538307807 |
|
|
Mar 10 01:11:37 PM PDT 24 |
Mar 10 01:11:40 PM PDT 24 |
268145520 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3610916439 |
|
|
Mar 10 01:11:29 PM PDT 24 |
Mar 10 01:11:34 PM PDT 24 |
536105251 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.832152166 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:11:26 PM PDT 24 |
54457018 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3435924711 |
|
|
Mar 10 01:11:41 PM PDT 24 |
Mar 10 01:12:35 PM PDT 24 |
7130308350 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.940915592 |
|
|
Mar 10 01:11:24 PM PDT 24 |
Mar 10 01:11:25 PM PDT 24 |
15309222 ps |
| T992 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2260479513 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:34 PM PDT 24 |
700144633 ps |
| T993 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3245438829 |
|
|
Mar 10 01:11:29 PM PDT 24 |
Mar 10 01:11:30 PM PDT 24 |
35519459 ps |
| T994 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4155458385 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:35 PM PDT 24 |
16603605 ps |
| T128 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3409950165 |
|
|
Mar 10 01:11:34 PM PDT 24 |
Mar 10 01:11:37 PM PDT 24 |
112276678 ps |
| T129 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2345379424 |
|
|
Mar 10 01:11:31 PM PDT 24 |
Mar 10 01:11:34 PM PDT 24 |
98991754 ps |
| T995 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3893160045 |
|
|
Mar 10 01:11:32 PM PDT 24 |
Mar 10 01:11:37 PM PDT 24 |
356346493 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.115267485 |
|
|
Mar 10 01:11:23 PM PDT 24 |
Mar 10 01:11:24 PM PDT 24 |
15902660 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3229631711 |
|
|
Mar 10 01:11:25 PM PDT 24 |
Mar 10 01:12:16 PM PDT 24 |
7061705251 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.323437339 |
|
|
Mar 10 01:11:21 PM PDT 24 |
Mar 10 01:11:22 PM PDT 24 |
14095301 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1199609224 |
|
|
Mar 10 01:11:22 PM PDT 24 |
Mar 10 01:11:24 PM PDT 24 |
93164557 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3754571179 |
|
|
Mar 10 01:11:22 PM PDT 24 |
Mar 10 01:11:26 PM PDT 24 |
343995416 ps |
| T1001 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2367038980 |
|
|
Mar 10 01:11:42 PM PDT 24 |
Mar 10 01:11:47 PM PDT 24 |
135245577 ps |
| T123 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3450757195 |
|
|
Mar 10 01:11:38 PM PDT 24 |
Mar 10 01:11:40 PM PDT 24 |
305131814 ps |