Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15894708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148244726

1

T1

137625

T2

114563

T3

963629

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80687231	1			T1	688128		T2	63295		T3	529722
values[0x0]	40143412	1			T1	343904		T2	30139		T3	255941
values[0x1]	43308791	1			T1	344224		T2	32622		T3	274292

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8085809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156053625

1

T1

137625

T2

120231

T3

101185

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	513684	1			T2	511		T3	3861		T10	808
valid_sources[0x01]	581717	1			T2	518		T3	3457		T10	681
valid_sources[0x02]	517938	1			T2	488		T3	3514		T10	698
valid_sources[0x03]	604187	1			T2	455		T3	4131		T10	764
valid_sources[0x04]	533073	1			T2	477		T3	4292		T10	748
valid_sources[0x05]	530015	1			T2	497		T3	3859		T10	717
valid_sources[0x06]	519574	1			T2	496		T3	4525		T10	795
valid_sources[0x07]	504163	1			T2	519		T3	4465		T10	822
valid_sources[0x08]	1171473	1			T2	499		T3	4106		T10	799
valid_sources[0x09]	573342	1			T2	516		T3	4812		T4	18145
valid_sources[0x0a]	511229	1			T2	497		T3	4240		T10	767
valid_sources[0x0b]	543197	1			T2	507		T3	4321		T10	752
valid_sources[0x0c]	521788	1			T2	481		T3	4350		T10	811
valid_sources[0x0d]	553310	1			T2	474		T3	4141		T10	684
valid_sources[0x0e]	539631	1			T2	532		T3	4131		T10	776
valid_sources[0x0f]	512474	1			T2	510		T3	3689		T10	876
valid_sources[0x10]	564847	1			T2	521		T3	4702		T10	726
valid_sources[0x11]	716788	1			T2	493		T3	4600		T10	755
valid_sources[0x12]	565952	1			T2	537		T3	4553		T10	794
valid_sources[0x13]	1122455	1			T2	527		T3	4061		T10	768
valid_sources[0x14]	525497	1			T2	520		T3	4232		T10	770
valid_sources[0x15]	553263	1			T2	475		T3	5359		T10	800
valid_sources[0x16]	520669	1			T2	452		T3	3690		T10	814
valid_sources[0x17]	556180	1			T2	482		T3	3797		T10	743
valid_sources[0x18]	540716	1			T2	499		T3	4344		T10	778
valid_sources[0x19]	536421	1			T2	486		T3	4322		T10	781
valid_sources[0x1a]	520171	1			T2	514		T3	4852		T10	797
valid_sources[0x1b]	524190	1			T2	453		T3	3574		T10	771
valid_sources[0x1c]	1883222	1			T2	505		T3	4325		T10	736
valid_sources[0x1d]	537970	1			T2	511		T3	3940		T10	652
valid_sources[0x1e]	504109	1			T2	495		T3	3964		T10	750
valid_sources[0x1f]	506975	1			T2	470		T3	3815		T10	804
valid_sources[0x20]	534993	1			T2	506		T3	4933		T10	766
valid_sources[0x21]	507283	1			T2	509		T3	4101		T10	689
valid_sources[0x22]	562339	1			T2	486		T3	5389		T10	713
valid_sources[0x23]	518790	1			T2	487		T3	4300		T10	779
valid_sources[0x24]	539135	1			T2	470		T3	4091		T10	829
valid_sources[0x25]	513192	1			T2	516		T3	4541		T10	754
valid_sources[0x26]	559091	1			T2	454		T3	3966		T10	768
valid_sources[0x27]	562960	1			T2	503		T3	4260		T10	809
valid_sources[0x28]	519972	1			T2	446		T3	4009		T10	716
valid_sources[0x29]	539701	1			T2	536		T3	4101		T10	855
valid_sources[0x2a]	641552	1			T2	433		T3	3487		T10	736
valid_sources[0x2b]	535861	1			T2	496		T3	5243		T10	842
valid_sources[0x2c]	546519	1			T2	487		T3	4156		T10	795
valid_sources[0x2d]	533705	1			T2	464		T3	4608		T10	623
valid_sources[0x2e]	509458	1			T2	516		T3	3873		T10	716
valid_sources[0x2f]	522203	1			T2	526		T3	5536		T10	840
valid_sources[0x30]	506822	1			T2	489		T3	4973		T10	743
valid_sources[0x31]	651071	1			T2	460		T3	5039		T10	772
valid_sources[0x32]	598410	1			T2	500		T3	3516		T10	751
valid_sources[0x33]	561103	1			T2	517		T3	3189		T10	712
valid_sources[0x34]	521107	1			T2	445		T3	4181		T10	704
valid_sources[0x35]	509329	1			T2	501		T3	3500		T10	829
valid_sources[0x36]	585489	1			T2	523		T3	4273		T10	691
valid_sources[0x37]	537327	1			T2	512		T3	4765		T10	685
valid_sources[0x38]	543479	1			T2	470		T3	3712		T10	592
valid_sources[0x39]	559061	1			T2	478		T3	3107		T10	791
valid_sources[0x3a]	526706	1			T2	533		T3	2823		T10	752
valid_sources[0x3b]	580806	1			T2	441		T3	3831		T10	803
valid_sources[0x3c]	542636	1			T2	544		T3	4061		T10	778
valid_sources[0x3d]	1394952	1			T2	501		T3	5720		T10	751
valid_sources[0x3e]	520634	1			T2	450		T3	3916		T10	749
valid_sources[0x3f]	552184	1			T2	500		T3	3262		T10	785
valid_sources[0x40]	527463	1			T2	493		T3	3776		T10	682
valid_sources[0x41]	553156	1			T2	518		T3	4493		T10	717
valid_sources[0x42]	526529	1			T2	494		T3	3583		T10	775
valid_sources[0x43]	592912	1			T2	540		T3	3716		T10	817
valid_sources[0x44]	534346	1			T2	517		T3	3107		T10	848
valid_sources[0x45]	558891	1			T2	541		T3	4286		T10	688
valid_sources[0x46]	1415248	1			T2	519		T3	3574		T10	828
valid_sources[0x47]	578063	1			T2	494		T3	5039		T10	768
valid_sources[0x48]	612489	1			T2	469		T3	3934		T10	657
valid_sources[0x49]	583130	1			T2	529		T3	3757		T10	761
valid_sources[0x4a]	523204	1			T2	524		T3	5212		T10	749
valid_sources[0x4b]	545320	1			T2	445		T3	4252		T10	843
valid_sources[0x4c]	530532	1			T2	525		T3	3468		T10	749
valid_sources[0x4d]	501243	1			T2	523		T3	3896		T10	791
valid_sources[0x4e]	504690	1			T2	485		T3	3182		T10	745
valid_sources[0x4f]	522860	1			T2	488		T3	4337		T10	844
valid_sources[0x50]	703625	1			T2	522		T3	3813		T10	788
valid_sources[0x51]	543644	1			T2	520		T3	3616		T10	769
valid_sources[0x52]	1955052	1			T2	515		T3	3649		T10	788
valid_sources[0x53]	521010	1			T2	489		T3	3601		T10	733
valid_sources[0x54]	541630	1			T2	507		T3	4644		T10	727
valid_sources[0x55]	564587	1			T2	444		T3	4242		T10	752
valid_sources[0x56]	514747	1			T2	494		T3	3990		T10	751
valid_sources[0x57]	528432	1			T2	485		T3	4308		T10	696
valid_sources[0x58]	566626	1			T2	483		T3	3783		T10	849
valid_sources[0x59]	519160	1			T2	480		T3	3756		T10	744
valid_sources[0x5a]	515161	1			T2	476		T3	4513		T10	720
valid_sources[0x5b]	534332	1			T2	473		T3	4228		T10	802
valid_sources[0x5c]	624031	1			T2	493		T3	3935		T10	824
valid_sources[0x5d]	534753	1			T2	489		T3	3997		T10	773
valid_sources[0x5e]	510281	1			T2	505		T3	4189		T10	794
valid_sources[0x5f]	561233	1			T2	489		T3	4034		T10	823
valid_sources[0x60]	562379	1			T2	496		T3	3910		T10	705
valid_sources[0x61]	552712	1			T2	463		T3	3878		T10	815
valid_sources[0x62]	525770	1			T2	468		T3	4038		T10	866
valid_sources[0x63]	519814	1			T2	526		T3	4355		T10	680
valid_sources[0x64]	539622	1			T2	466		T3	3861		T10	683
valid_sources[0x65]	604678	1			T2	461		T3	3462		T10	773
valid_sources[0x66]	532640	1			T2	519		T3	2721		T10	781
valid_sources[0x67]	661867	1			T2	555		T3	3728		T10	678
valid_sources[0x68]	533130	1			T2	503		T3	4790		T4	4055
valid_sources[0x69]	550068	1			T2	473		T3	3838		T10	784
valid_sources[0x6a]	515344	1			T2	479		T3	4033		T10	802
valid_sources[0x6b]	542465	1			T2	541		T3	4644		T4	4543
valid_sources[0x6c]	511249	1			T2	517		T3	3732		T10	760
valid_sources[0x6d]	578829	1			T2	492		T3	4750		T10	767
valid_sources[0x6e]	523143	1			T2	460		T3	3823		T10	745
valid_sources[0x6f]	1249875	1			T2	488		T3	3733		T10	793
valid_sources[0x70]	574142	1			T2	495		T3	4137		T10	855
valid_sources[0x71]	530218	1			T2	464		T3	3536		T10	826
valid_sources[0x72]	558423	1			T2	466		T3	3697		T10	709
valid_sources[0x73]	580325	1			T2	510		T3	4909		T10	792
valid_sources[0x74]	554873	1			T2	460		T3	3974		T10	862
valid_sources[0x75]	529779	1			T2	461		T3	4570		T10	772
valid_sources[0x76]	569416	1			T2	486		T3	4450		T10	744
valid_sources[0x77]	567496	1			T2	485		T3	5345		T10	727
valid_sources[0x78]	1705188	1			T2	485		T3	4597		T10	782
valid_sources[0x79]	2101784	1			T2	521		T3	4209		T10	768
valid_sources[0x7a]	545844	1			T2	515		T3	4265		T10	747
valid_sources[0x7b]	1012719	1			T2	546		T3	4382		T10	823
valid_sources[0x7c]	550259	1			T2	469		T3	5016		T10	812
valid_sources[0x7d]	524641	1			T2	504		T3	4073		T10	737
valid_sources[0x7e]	609515	1			T2	491		T3	3462		T10	818
valid_sources[0x7f]	1324902	1			T2	473		T3	3776		T10	744
valid_sources[0x80]	519281	1			T2	497		T3	3644		T10	799

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72694223

1

T1

688128

T2

57518

T3

481766

values[0x0]

all_enables

biggest_size

37773133

1

T1

343904

T2

28389

T3

241134

values[0x1]

all_enables

biggest_size

37777370

1

T1

344224

T2

28656

T3

240729

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

143059

1

T1

4

T2

5

T3

113

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50809	1			T3	70		T19	6		T8	80
values[0x0]	60582	1			T1	9		T2	15		T3	174
values[0x1]	64658	1			T1	12		T2	5		T3	163

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151266

1

T1

6

T2

5

T3

153

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	534	1			T2	1		T15	2		T8	1
valid_sources[0x01]	660	1			T12	20		T83	1		T35	10
valid_sources[0x02]	890	1			T3	5		T34	15		T26	1
valid_sources[0x03]	584	1			T4	1		T34	12		T35	10
valid_sources[0x04]	580	1			T3	7		T34	2		T35	10
valid_sources[0x05]	612	1			T4	1		T34	3		T35	9
valid_sources[0x06]	585	1			T35	7		T36	29		T47	4
valid_sources[0x07]	644	1			T3	2		T8	1		T34	3
valid_sources[0x08]	707	1			T3	1		T55	2		T35	7
valid_sources[0x09]	870	1			T34	14		T83	1		T35	7
valid_sources[0x0a]	485	1			T3	1		T11	1		T35	6
valid_sources[0x0b]	755	1			T35	6		T130	5		T36	21
valid_sources[0x0c]	509	1			T3	4		T4	1		T34	15
valid_sources[0x0d]	582	1			T1	1		T3	2		T34	5
valid_sources[0x0e]	726	1			T34	7		T35	5		T36	23
valid_sources[0x0f]	889	1			T3	2		T34	29		T5	1
valid_sources[0x10]	871	1			T34	21		T35	6		T36	25
valid_sources[0x11]	554	1			T2	6		T4	1		T34	4
valid_sources[0x12]	912	1			T3	3		T15	1		T34	7
valid_sources[0x13]	535	1			T3	4		T15	2		T34	2
valid_sources[0x14]	960	1			T34	10		T44	4		T35	3
valid_sources[0x15]	625	1			T3	2		T4	1		T34	13
valid_sources[0x16]	616	1			T34	8		T35	2		T36	28
valid_sources[0x17]	659	1			T4	1		T34	15		T83	1
valid_sources[0x18]	691	1			T19	1		T8	1		T34	10
valid_sources[0x19]	552	1			T3	5		T34	8		T26	1
valid_sources[0x1a]	826	1			T1	2		T3	2		T14	32
valid_sources[0x1b]	612	1			T3	1		T4	1		T35	7
valid_sources[0x1c]	521	1			T15	1		T8	1		T34	15
valid_sources[0x1d]	755	1			T34	16		T35	7		T36	28
valid_sources[0x1e]	685	1			T4	1		T15	4		T34	11
valid_sources[0x1f]	663	1			T3	3		T15	1		T34	11
valid_sources[0x20]	547	1			T3	1		T35	11		T36	23
valid_sources[0x21]	673	1			T34	13		T5	1		T35	9
valid_sources[0x22]	587	1			T3	2		T34	9		T44	4
valid_sources[0x23]	540	1			T3	1		T34	21		T44	7
valid_sources[0x24]	712	1			T3	3		T34	1		T35	10
valid_sources[0x25]	677	1			T34	29		T35	6		T45	2
valid_sources[0x26]	856	1			T3	3		T8	2		T34	3
valid_sources[0x27]	522	1			T3	1		T34	26		T83	1
valid_sources[0x28]	767	1			T34	5		T24	14		T5	1
valid_sources[0x29]	794	1			T34	2		T44	5		T35	11
valid_sources[0x2a]	777	1			T34	9		T44	2		T35	3
valid_sources[0x2b]	653	1			T3	6		T34	31		T35	3
valid_sources[0x2c]	745	1			T3	3		T34	7		T5	1
valid_sources[0x2d]	788	1			T34	3		T26	1		T35	4
valid_sources[0x2e]	699	1			T3	3		T21	2		T34	1
valid_sources[0x2f]	643	1			T34	30		T42	3		T35	8
valid_sources[0x30]	577	1			T34	15		T35	10		T36	34
valid_sources[0x31]	671	1			T3	2		T4	1		T34	6
valid_sources[0x32]	868	1			T3	3		T8	1		T34	3
valid_sources[0x33]	750	1			T3	1		T34	11		T83	1
valid_sources[0x34]	537	1			T3	3		T34	23		T35	6
valid_sources[0x35]	746	1			T4	1		T34	28		T35	7
valid_sources[0x36]	814	1			T2	5		T8	3		T34	8
valid_sources[0x37]	456	1			T3	2		T34	2		T35	4
valid_sources[0x38]	698	1			T3	1		T15	1		T8	1
valid_sources[0x39]	725	1			T2	2		T3	2		T34	6
valid_sources[0x3a]	478	1			T34	6		T5	3		T35	6
valid_sources[0x3b]	505	1			T4	1		T34	6		T90	1
valid_sources[0x3c]	522	1			T3	8		T34	8		T35	8
valid_sources[0x3d]	670	1			T19	1		T34	17		T44	10
valid_sources[0x3e]	508	1			T3	1		T34	35		T35	8
valid_sources[0x3f]	683	1			T2	1		T3	2		T4	1
valid_sources[0x40]	538	1			T3	6		T34	15		T35	6
valid_sources[0x41]	958	1			T3	1		T19	2		T34	13
valid_sources[0x42]	501	1			T3	4		T8	1		T34	11
valid_sources[0x43]	782	1			T8	1		T34	10		T83	2
valid_sources[0x44]	763	1			T3	1		T34	15		T35	7
valid_sources[0x45]	858	1			T3	2		T19	2		T34	11
valid_sources[0x46]	798	1			T3	2		T4	1		T34	2
valid_sources[0x47]	512	1			T3	1		T8	2		T34	12
valid_sources[0x48]	649	1			T3	2		T8	1		T34	35
valid_sources[0x49]	631	1			T4	1		T34	7		T83	1
valid_sources[0x4a]	643	1			T34	1		T44	10		T35	4
valid_sources[0x4b]	530	1			T3	5		T34	28		T35	4
valid_sources[0x4c]	695	1			T3	1		T4	1		T34	22
valid_sources[0x4d]	1548	1			T34	7		T35	2		T36	23
valid_sources[0x4e]	658	1			T3	2		T34	12		T5	1
valid_sources[0x4f]	1273	1			T4	1		T8	2		T34	9
valid_sources[0x50]	700	1			T3	3		T34	13		T44	5
valid_sources[0x51]	647	1			T3	3		T8	1		T34	12
valid_sources[0x52]	467	1			T34	5		T35	9		T36	24
valid_sources[0x53]	1150	1			T3	3		T34	4		T24	1
valid_sources[0x54]	492	1			T3	3		T34	7		T35	3
valid_sources[0x55]	605	1			T3	3		T4	1		T34	2
valid_sources[0x56]	836	1			T35	4		T36	26		T131	1
valid_sources[0x57]	700	1			T34	8		T44	3		T35	5
valid_sources[0x58]	497	1			T15	2		T34	2		T35	7
valid_sources[0x59]	736	1			T3	1		T8	2		T35	3
valid_sources[0x5a]	784	1			T3	2		T8	1		T34	17
valid_sources[0x5b]	690	1			T3	5		T35	7		T36	22
valid_sources[0x5c]	533	1			T3	1		T34	2		T35	5
valid_sources[0x5d]	461	1			T3	3		T34	8		T23	1
valid_sources[0x5e]	657	1			T2	3		T3	6		T5	1
valid_sources[0x5f]	692	1			T3	1		T8	1		T34	8
valid_sources[0x60]	1035	1			T3	3		T34	6		T35	4
valid_sources[0x61]	908	1			T3	1		T34	1		T5	1
valid_sources[0x62]	493	1			T3	1		T34	24		T35	4
valid_sources[0x63]	551	1			T3	4		T34	3		T35	6
valid_sources[0x64]	491	1			T8	2		T34	6		T26	1
valid_sources[0x65]	729	1			T3	3		T34	5		T5	2
valid_sources[0x66]	563	1			T1	2		T34	13		T35	10
valid_sources[0x67]	811	1			T3	3		T34	7		T35	6
valid_sources[0x68]	1163	1			T1	1		T34	2		T83	1
valid_sources[0x69]	539	1			T34	7		T35	13		T36	13
valid_sources[0x6a]	541	1			T3	2		T34	1		T5	1
valid_sources[0x6b]	572	1			T3	2		T34	10		T35	7
valid_sources[0x6c]	647	1			T3	1		T34	13		T35	4
valid_sources[0x6d]	521	1			T3	1		T34	15		T83	1
valid_sources[0x6e]	493	1			T3	1		T34	4		T35	12
valid_sources[0x6f]	653	1			T3	2		T34	13		T35	12
valid_sources[0x70]	892	1			T3	3		T34	13		T84	2
valid_sources[0x71]	564	1			T3	2		T34	17		T44	3
valid_sources[0x72]	1051	1			T1	1		T3	3		T34	7
valid_sources[0x73]	600	1			T3	2		T34	16		T35	5
valid_sources[0x74]	634	1			T3	1		T4	1		T19	3
valid_sources[0x75]	755	1			T3	1		T34	1		T35	1
valid_sources[0x76]	751	1			T3	1		T8	2		T34	12
valid_sources[0x77]	579	1			T34	45		T83	1		T35	4
valid_sources[0x78]	559	1			T5	1		T44	4		T35	8
valid_sources[0x79]	635	1			T3	1		T34	3		T54	1
valid_sources[0x7a]	650	1			T34	4		T5	1		T35	7
valid_sources[0x7b]	855	1			T3	3		T34	10		T35	8
valid_sources[0x7c]	647	1			T3	4		T83	1		T35	4
valid_sources[0x7d]	551	1			T15	2		T8	2		T34	4
valid_sources[0x7e]	511	1			T15	1		T8	1		T34	2
valid_sources[0x7f]	593	1			T34	2		T35	7		T36	19
valid_sources[0x80]	608	1			T3	3		T34	5		T35	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38986

1

T3

33

T19

3

T34

685

values[0x0]

all_enables

biggest_size

52992

1

T1

4

T2

4

T3

55

values[0x1]

all_enables

biggest_size

51081

1

T2

1

T3

25

T4

3