Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15806161

1

T2

11493

T3

83860

T4

18099

full_word

145252389

1

T1

137625

T2

114563

T3

839375

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	161058260	1			T1	137625		T2	126056		T3	923235
auto[TlIntgErrCmd]	98	1			T103	6		T104	4		T105	4
auto[TlIntgErrData]	99	1			T103	1		T104	5		T105	2
auto[TlIntgErrBoth]	93	1			T103	3		T104	11		T105	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77516180

1

T1

688128

T2

63295

T3

393002

auto[1]

83542370

1

T1

688128

T2

62761

T3

530233

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7742801	1			T2	5777		T3	35490		T4	8392
auto[TlIntgErrNone]	partial	auto[1]	8063096	1			T2	5716		T3	48370		T4	9707
auto[TlIntgErrNone]	full_word	auto[0]	69773252	1			T1	688128		T2	57518		T3	357512
auto[TlIntgErrNone]	full_word	auto[1]	75479111	1			T1	688128		T2	57045		T3	481863
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T103	2		T104	2		T105	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T103	4		T104	2		T105	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T123	2		T124	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T117	1		T125	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T103	1		T104	2		T105	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T104	3		T117	5		T119	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T125	1		T127	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T105	1		T118	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T103	1		T104	6		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T103	1		T104	5		T105	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T128	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T103	1		T125	1		T121	1