Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	888717	1			T16	13200		T17	30149		T5	6
auto[1]	10693006	1			T2	45350		T3	62567		T4	11946
auto[2]	679238	1			T16	9461		T17	21538		T5	13
auto[3]	10392064	1			T2	44771		T3	54485		T4	6679

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13948102	1			T2	75123		T3	97489		T4	15536
auto[1]	2149248	1			T2	7193		T3	9381		T4	1491
auto[2]	2151178	1			T2	7144		T3	9311		T4	1469
auto[3]	4404497	1			T2	661		T3	871		T4	129

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9165006

1

T2

90119

T3

117043

T4

18625

auto[1]

13488019

1

T2

2

T3

9

T16

41485

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	356588	1			T5	5		T44	9302		T86	1702
auto[0]	auto[0]	auto[1]	37115	1			T17	2		T44	940		T86	186
auto[0]	auto[0]	auto[2]	37250	1			T16	3		T5	1		T44	917
auto[0]	auto[0]	auto[3]	78072	1			T16	3		T17	4		T44	104
auto[0]	auto[1]	auto[0]	3146772	1			T2	37819		T3	52135		T4	9891
auto[0]	auto[1]	auto[1]	340872	1			T2	3436		T3	4764		T4	982
auto[0]	auto[1]	auto[2]	345227	1			T2	3761		T3	5199		T4	991
auto[0]	auto[1]	auto[3]	416609	1			T2	334		T3	463		T4	82
auto[0]	auto[2]	auto[0]	266455	1			T5	11		T44	5338		T86	1021
auto[0]	auto[2]	auto[1]	32695	1			T17	3		T5	2		T44	530
auto[0]	auto[2]	auto[2]	23810	1			T17	2		T44	464		T86	167
auto[0]	auto[2]	auto[3]	53795	1			T16	1		T17	2		T44	43
auto[0]	auto[3]	auto[0]	2986369	1			T2	37302		T3	45346		T4	5645
auto[0]	auto[3]	auto[1]	323737	1			T2	3757		T3	4616		T4	509
auto[0]	auto[3]	auto[2]	345336	1			T2	3383		T3	4112		T4	478
auto[0]	auto[3]	auto[3]	374304	1			T2	327		T3	408		T4	47
auto[1]	auto[0]	auto[0]	12423	1			T16	439		T17	959		T95	756
auto[1]	auto[0]	auto[1]	56402	1			T16	1969		T17	4456		T95	3323
auto[1]	auto[0]	auto[2]	56636	1			T16	1929		T17	4470		T95	3356
auto[1]	auto[0]	auto[3]	254231	1			T16	8857		T17	20258		T95	14585
auto[1]	auto[1]	auto[0]	3586512	1			T3	5		T16	73		T17	165
auto[1]	auto[1]	auto[1]	673674	1			T3	1		T16	1962		T17	4666
auto[1]	auto[1]	auto[2]	640018	1			T16	338		T17	731		T90	856
auto[1]	auto[1]	auto[3]	1543322	1			T16	8850		T17	20002		T90	11414
auto[1]	auto[2]	auto[0]	11297	1			T16	375		T17	923		T44	1
auto[1]	auto[2]	auto[1]	50721	1			T16	1833		T17	4203		T95	3037
auto[1]	auto[2]	auto[2]	43854	1			T16	1295		T17	3047		T95	2171
auto[1]	auto[2]	auto[3]	196611	1			T16	5957		T17	13358		T95	9835
auto[1]	auto[3]	auto[0]	3581686	1			T2	2		T3	3		T16	50
auto[1]	auto[3]	auto[1]	634032	1			T16	193		T17	385		T90	835
auto[1]	auto[3]	auto[2]	659047	1			T16	1302		T17	3125		T90	2553
auto[1]	auto[3]	auto[3]	1487553	1			T16	6063		T17	13626		T90	11443