Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1220374806	137851	0	0
ctrl_regwen_rd_A	1220374806	7641	0	0
exec_rd_A	1220374806	7020	0	0
exec_regwen_rd_A	1220374806	7626	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220374806	137851	0	0
T16	105555	0	0	0
T17	221753	0	0	0
T18	179153	0	0	0
T23	105995	0	0	0
T26	1456	0	0	0
T34	63675	2586	0	0
T35	0	1364	0	0
T36	0	7870	0	0
T42	347466	0	0	0
T43	173380	0	0	0
T47	0	1697	0	0
T48	0	3307	0	0
T49	0	1273	0	0
T50	0	2502	0	0
T51	0	1787	0	0
T52	0	4033	0	0
T53	0	2863	0	0
T54	50356	0	0	0
T55	69115	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220374806	7641	0	0
T6	872368	0	0	0
T9	265829	0	0	0
T25	101886	0	0	0
T39	34173	0	0	0
T47	73933	356	0	0
T51	0	356	0	0
T56	121234	0	0	0
T98	523406	0	0	0
T106	0	995	0	0
T107	0	219	0	0
T108	0	222	0	0
T109	0	465	0	0
T110	0	240	0	0
T111	0	113	0	0
T112	0	584	0	0
T113	0	469	0	0
T114	206450	0	0	0
T115	111659	0	0	0
T116	126050	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220374806	7020	0	0
T6	872368	0	0	0
T9	265829	0	0	0
T25	101886	0	0	0
T39	34173	0	0	0
T47	73933	347	0	0
T51	0	309	0	0
T56	121234	0	0	0
T98	523406	0	0	0
T106	0	781	0	0
T107	0	199	0	0
T108	0	172	0	0
T109	0	423	0	0
T110	0	234	0	0
T111	0	86	0	0
T112	0	360	0	0
T113	0	447	0	0
T114	206450	0	0	0
T115	111659	0	0	0
T116	126050	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220374806	7626	0	0
T6	872368	0	0	0
T9	265829	0	0	0
T25	101886	0	0	0
T39	34173	0	0	0
T47	73933	369	0	0
T51	0	435	0	0
T56	121234	0	0	0
T98	523406	0	0	0
T106	0	972	0	0
T107	0	274	0	0
T108	0	150	0	0
T109	0	505	0	0
T110	0	283	0	0
T111	0	112	0	0
T112	0	369	0	0
T113	0	359	0	0
T114	206450	0	0	0
T115	111659	0	0	0
T116	126050	0	0	0