Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.41 100.00 97.91 100.00 100.00 99.72 99.70 98.52


Total test records in report: 1022
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T295 /workspace/coverage/default/10.sram_ctrl_max_throughput.4018625836 Mar 12 02:19:09 PM PDT 24 Mar 12 02:20:18 PM PDT 24 1513689631 ps
T296 /workspace/coverage/default/2.sram_ctrl_partial_access.858642114 Mar 12 02:15:22 PM PDT 24 Mar 12 02:17:59 PM PDT 24 4420402429 ps
T297 /workspace/coverage/default/22.sram_ctrl_stress_all.1796848562 Mar 12 02:23:27 PM PDT 24 Mar 12 04:04:17 PM PDT 24 742926001961 ps
T298 /workspace/coverage/default/3.sram_ctrl_executable.3259563709 Mar 12 02:15:58 PM PDT 24 Mar 12 02:17:45 PM PDT 24 2754934341 ps
T299 /workspace/coverage/default/8.sram_ctrl_max_throughput.900366905 Mar 12 02:18:21 PM PDT 24 Mar 12 02:18:46 PM PDT 24 775051803 ps
T300 /workspace/coverage/default/0.sram_ctrl_ram_cfg.3643973719 Mar 12 02:14:37 PM PDT 24 Mar 12 02:14:41 PM PDT 24 1247351075 ps
T301 /workspace/coverage/default/18.sram_ctrl_alert_test.1177980219 Mar 12 02:22:07 PM PDT 24 Mar 12 02:22:07 PM PDT 24 37985546 ps
T302 /workspace/coverage/default/10.sram_ctrl_alert_test.838370127 Mar 12 02:19:20 PM PDT 24 Mar 12 02:19:21 PM PDT 24 58276268 ps
T303 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.719575092 Mar 12 02:20:24 PM PDT 24 Mar 12 02:21:47 PM PDT 24 30229418010 ps
T304 /workspace/coverage/default/15.sram_ctrl_regwen.2243176792 Mar 12 02:21:12 PM PDT 24 Mar 12 02:47:18 PM PDT 24 21029386719 ps
T305 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2330068283 Mar 12 02:14:30 PM PDT 24 Mar 12 02:14:44 PM PDT 24 2160180300 ps
T306 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3817327287 Mar 12 02:24:31 PM PDT 24 Mar 12 02:25:34 PM PDT 24 1481668236 ps
T307 /workspace/coverage/default/4.sram_ctrl_partial_access.647690531 Mar 12 02:16:22 PM PDT 24 Mar 12 02:17:15 PM PDT 24 787891746 ps
T308 /workspace/coverage/default/26.sram_ctrl_partial_access.3072865776 Mar 12 02:24:31 PM PDT 24 Mar 12 02:24:38 PM PDT 24 727209883 ps
T309 /workspace/coverage/default/38.sram_ctrl_stress_all.28586288 Mar 12 02:28:08 PM PDT 24 Mar 12 02:51:51 PM PDT 24 46809125967 ps
T310 /workspace/coverage/default/24.sram_ctrl_max_throughput.3906256873 Mar 12 02:23:55 PM PDT 24 Mar 12 02:24:02 PM PDT 24 1404210772 ps
T311 /workspace/coverage/default/35.sram_ctrl_max_throughput.4210310707 Mar 12 02:27:13 PM PDT 24 Mar 12 02:28:02 PM PDT 24 3226292772 ps
T312 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.2360763885 Mar 12 02:31:10 PM PDT 24 Mar 12 02:39:38 PM PDT 24 23671192887 ps
T313 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1143981847 Mar 12 02:16:58 PM PDT 24 Mar 12 02:18:06 PM PDT 24 2827645192 ps
T314 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2719514683 Mar 12 02:28:58 PM PDT 24 Mar 12 02:31:04 PM PDT 24 6202996552 ps
T315 /workspace/coverage/default/38.sram_ctrl_smoke.498448778 Mar 12 02:28:35 PM PDT 24 Mar 12 02:28:44 PM PDT 24 3302749937 ps
T316 /workspace/coverage/default/10.sram_ctrl_multiple_keys.365089322 Mar 12 02:18:56 PM PDT 24 Mar 12 02:38:52 PM PDT 24 20161981931 ps
T317 /workspace/coverage/default/3.sram_ctrl_stress_all.622155736 Mar 12 02:16:03 PM PDT 24 Mar 12 04:21:52 PM PDT 24 973584564735 ps
T318 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3191583612 Mar 12 02:26:20 PM PDT 24 Mar 12 02:30:43 PM PDT 24 8385094494 ps
T319 /workspace/coverage/default/22.sram_ctrl_smoke.1183560845 Mar 12 02:23:39 PM PDT 24 Mar 12 02:23:46 PM PDT 24 3020770331 ps
T320 /workspace/coverage/default/32.sram_ctrl_ram_cfg.2288278157 Mar 12 02:26:25 PM PDT 24 Mar 12 02:26:29 PM PDT 24 721689757 ps
T321 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.1565678841 Mar 12 02:29:11 PM PDT 24 Mar 12 02:48:22 PM PDT 24 78155865598 ps
T322 /workspace/coverage/default/43.sram_ctrl_partial_access.183074415 Mar 12 02:29:34 PM PDT 24 Mar 12 02:29:46 PM PDT 24 1926856058 ps
T323 /workspace/coverage/default/17.sram_ctrl_stress_all.581485492 Mar 12 02:21:37 PM PDT 24 Mar 12 03:12:07 PM PDT 24 47480108109 ps
T324 /workspace/coverage/default/2.sram_ctrl_stress_all.281846901 Mar 12 02:15:51 PM PDT 24 Mar 12 03:08:36 PM PDT 24 107378892798 ps
T325 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.3770172689 Mar 12 02:27:48 PM PDT 24 Mar 12 02:49:12 PM PDT 24 49141224158 ps
T326 /workspace/coverage/default/46.sram_ctrl_ram_cfg.3554683825 Mar 12 02:30:49 PM PDT 24 Mar 12 02:30:54 PM PDT 24 1305824672 ps
T327 /workspace/coverage/default/27.sram_ctrl_max_throughput.4033727158 Mar 12 02:24:44 PM PDT 24 Mar 12 02:26:20 PM PDT 24 3146106978 ps
T328 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.227382622 Mar 12 02:21:21 PM PDT 24 Mar 12 02:27:16 PM PDT 24 58667306478 ps
T329 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.176060752 Mar 12 02:22:50 PM PDT 24 Mar 12 02:23:23 PM PDT 24 2236878513 ps
T330 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.701819024 Mar 12 02:24:09 PM PDT 24 Mar 12 02:26:53 PM PDT 24 12934817483 ps
T331 /workspace/coverage/default/11.sram_ctrl_lc_escalation.532168471 Mar 12 02:19:32 PM PDT 24 Mar 12 02:20:37 PM PDT 24 10563224164 ps
T332 /workspace/coverage/default/30.sram_ctrl_executable.135720775 Mar 12 02:25:56 PM PDT 24 Mar 12 02:44:01 PM PDT 24 32112093218 ps
T333 /workspace/coverage/default/41.sram_ctrl_ram_cfg.835956411 Mar 12 02:29:18 PM PDT 24 Mar 12 02:29:22 PM PDT 24 685237611 ps
T334 /workspace/coverage/default/2.sram_ctrl_executable.125519147 Mar 12 02:15:30 PM PDT 24 Mar 12 02:34:38 PM PDT 24 26003605176 ps
T335 /workspace/coverage/default/36.sram_ctrl_executable.2701630855 Mar 12 02:27:31 PM PDT 24 Mar 12 02:30:08 PM PDT 24 10502746324 ps
T336 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1170389907 Mar 12 02:17:08 PM PDT 24 Mar 12 02:17:29 PM PDT 24 779404945 ps
T337 /workspace/coverage/default/14.sram_ctrl_partial_access.1904002406 Mar 12 02:20:34 PM PDT 24 Mar 12 02:21:01 PM PDT 24 879693370 ps
T338 /workspace/coverage/default/25.sram_ctrl_smoke.2620310477 Mar 12 02:24:01 PM PDT 24 Mar 12 02:24:33 PM PDT 24 1858513768 ps
T339 /workspace/coverage/default/15.sram_ctrl_ram_cfg.3040292916 Mar 12 02:21:11 PM PDT 24 Mar 12 02:21:14 PM PDT 24 708045674 ps
T340 /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2504995131 Mar 12 02:26:25 PM PDT 24 Mar 12 02:27:33 PM PDT 24 2108384945 ps
T109 /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.561668665 Mar 12 02:22:06 PM PDT 24 Mar 12 02:23:40 PM PDT 24 3729960773 ps
T341 /workspace/coverage/default/15.sram_ctrl_mem_walk.3741978428 Mar 12 02:21:10 PM PDT 24 Mar 12 02:26:17 PM PDT 24 42156827194 ps
T342 /workspace/coverage/default/20.sram_ctrl_max_throughput.3869289861 Mar 12 02:22:34 PM PDT 24 Mar 12 02:22:50 PM PDT 24 2165334398 ps
T343 /workspace/coverage/default/31.sram_ctrl_ram_cfg.684400387 Mar 12 02:26:11 PM PDT 24 Mar 12 02:26:14 PM PDT 24 349854585 ps
T344 /workspace/coverage/default/26.sram_ctrl_executable.2166276295 Mar 12 02:24:43 PM PDT 24 Mar 12 02:36:34 PM PDT 24 7889966727 ps
T345 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4247268120 Mar 12 02:30:07 PM PDT 24 Mar 12 02:31:27 PM PDT 24 1533922691 ps
T346 /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3498300741 Mar 12 02:28:39 PM PDT 24 Mar 12 02:31:19 PM PDT 24 15619587717 ps
T347 /workspace/coverage/default/16.sram_ctrl_ram_cfg.97771172 Mar 12 02:21:20 PM PDT 24 Mar 12 02:21:23 PM PDT 24 2249102634 ps
T348 /workspace/coverage/default/40.sram_ctrl_executable.1085792110 Mar 12 02:28:56 PM PDT 24 Mar 12 02:39:06 PM PDT 24 6276022064 ps
T349 /workspace/coverage/default/19.sram_ctrl_alert_test.1666921445 Mar 12 02:22:31 PM PDT 24 Mar 12 02:22:32 PM PDT 24 24867951 ps
T350 /workspace/coverage/default/10.sram_ctrl_partial_access.3835884258 Mar 12 02:19:07 PM PDT 24 Mar 12 02:19:57 PM PDT 24 810251755 ps
T351 /workspace/coverage/default/15.sram_ctrl_max_throughput.969777527 Mar 12 02:21:00 PM PDT 24 Mar 12 02:22:34 PM PDT 24 1570238561 ps
T352 /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3791330833 Mar 12 02:28:29 PM PDT 24 Mar 12 02:28:54 PM PDT 24 4147910269 ps
T353 /workspace/coverage/default/16.sram_ctrl_alert_test.3370252113 Mar 12 02:21:29 PM PDT 24 Mar 12 02:21:31 PM PDT 24 33876879 ps
T354 /workspace/coverage/default/7.sram_ctrl_lc_escalation.1330801257 Mar 12 02:17:58 PM PDT 24 Mar 12 02:18:40 PM PDT 24 24758808333 ps
T355 /workspace/coverage/default/31.sram_ctrl_alert_test.1011305956 Mar 12 02:26:21 PM PDT 24 Mar 12 02:26:23 PM PDT 24 14059802 ps
T356 /workspace/coverage/default/31.sram_ctrl_lc_escalation.2999929403 Mar 12 02:26:02 PM PDT 24 Mar 12 02:26:53 PM PDT 24 17191445067 ps
T357 /workspace/coverage/default/32.sram_ctrl_multiple_keys.1280839390 Mar 12 02:26:21 PM PDT 24 Mar 12 02:47:08 PM PDT 24 76792094890 ps
T358 /workspace/coverage/default/8.sram_ctrl_stress_all.2612358645 Mar 12 02:18:35 PM PDT 24 Mar 12 02:51:17 PM PDT 24 209163729355 ps
T359 /workspace/coverage/default/9.sram_ctrl_partial_access.4063659347 Mar 12 02:18:37 PM PDT 24 Mar 12 02:19:02 PM PDT 24 6039038032 ps
T360 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.199614935 Mar 12 02:24:01 PM PDT 24 Mar 12 02:24:49 PM PDT 24 5563370562 ps
T361 /workspace/coverage/default/16.sram_ctrl_multiple_keys.2734018772 Mar 12 02:21:12 PM PDT 24 Mar 12 02:26:33 PM PDT 24 5674264325 ps
T362 /workspace/coverage/default/37.sram_ctrl_ram_cfg.2982866495 Mar 12 02:27:50 PM PDT 24 Mar 12 02:27:54 PM PDT 24 1403762405 ps
T363 /workspace/coverage/default/27.sram_ctrl_bijection.2684785336 Mar 12 02:24:39 PM PDT 24 Mar 12 03:12:42 PM PDT 24 662010129214 ps
T364 /workspace/coverage/default/30.sram_ctrl_access_during_key_req.177195710 Mar 12 02:25:48 PM PDT 24 Mar 12 02:36:21 PM PDT 24 46672260175 ps
T365 /workspace/coverage/default/14.sram_ctrl_ram_cfg.3322739125 Mar 12 02:20:46 PM PDT 24 Mar 12 02:20:49 PM PDT 24 690545622 ps
T366 /workspace/coverage/default/21.sram_ctrl_bijection.242684289 Mar 12 02:22:41 PM PDT 24 Mar 12 02:33:22 PM PDT 24 92958328161 ps
T367 /workspace/coverage/default/23.sram_ctrl_lc_escalation.1122108850 Mar 12 02:23:41 PM PDT 24 Mar 12 02:24:24 PM PDT 24 14422637444 ps
T368 /workspace/coverage/default/2.sram_ctrl_bijection.2920885623 Mar 12 02:15:22 PM PDT 24 Mar 12 02:36:12 PM PDT 24 76074493009 ps
T369 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1751089898 Mar 12 02:29:22 PM PDT 24 Mar 12 02:51:04 PM PDT 24 58889077387 ps
T370 /workspace/coverage/default/39.sram_ctrl_max_throughput.1812029685 Mar 12 02:28:17 PM PDT 24 Mar 12 02:29:03 PM PDT 24 14383571042 ps
T371 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2955900901 Mar 12 02:23:55 PM PDT 24 Mar 12 02:48:33 PM PDT 24 30996371973 ps
T372 /workspace/coverage/default/38.sram_ctrl_alert_test.721669887 Mar 12 02:29:09 PM PDT 24 Mar 12 02:29:10 PM PDT 24 20668546 ps
T373 /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.870787590 Mar 12 02:24:19 PM PDT 24 Mar 12 02:25:43 PM PDT 24 3422792495 ps
T374 /workspace/coverage/default/36.sram_ctrl_alert_test.265904134 Mar 12 02:27:45 PM PDT 24 Mar 12 02:27:46 PM PDT 24 72429425 ps
T375 /workspace/coverage/default/5.sram_ctrl_regwen.1933543421 Mar 12 02:17:07 PM PDT 24 Mar 12 02:34:19 PM PDT 24 15927542818 ps
T376 /workspace/coverage/default/49.sram_ctrl_alert_test.3192362441 Mar 12 02:31:47 PM PDT 24 Mar 12 02:31:48 PM PDT 24 29314393 ps
T377 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.1585353255 Mar 12 02:26:53 PM PDT 24 Mar 12 02:31:56 PM PDT 24 16977697488 ps
T110 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.119269177 Mar 12 02:31:19 PM PDT 24 Mar 12 02:31:29 PM PDT 24 816008807 ps
T378 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1122597071 Mar 12 02:20:10 PM PDT 24 Mar 12 02:21:31 PM PDT 24 5755322957 ps
T379 /workspace/coverage/default/17.sram_ctrl_mem_partial_access.344369577 Mar 12 02:21:37 PM PDT 24 Mar 12 02:22:41 PM PDT 24 2005230220 ps
T380 /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.845157136 Mar 12 02:23:17 PM PDT 24 Mar 12 02:23:39 PM PDT 24 4199737034 ps
T381 /workspace/coverage/default/3.sram_ctrl_bijection.3179013754 Mar 12 02:15:57 PM PDT 24 Mar 12 03:02:40 PM PDT 24 230051945266 ps
T382 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1245689832 Mar 12 02:27:30 PM PDT 24 Mar 12 02:32:02 PM PDT 24 67764876904 ps
T383 /workspace/coverage/default/12.sram_ctrl_ram_cfg.3552656080 Mar 12 02:20:00 PM PDT 24 Mar 12 02:20:04 PM PDT 24 1399794891 ps
T384 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2497447475 Mar 12 02:26:03 PM PDT 24 Mar 12 02:31:40 PM PDT 24 5642847957 ps
T111 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1091329655 Mar 12 02:26:29 PM PDT 24 Mar 12 02:26:38 PM PDT 24 231330654 ps
T385 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3883297311 Mar 12 02:31:11 PM PDT 24 Mar 12 02:31:18 PM PDT 24 2693517116 ps
T386 /workspace/coverage/default/0.sram_ctrl_max_throughput.801197263 Mar 12 02:14:30 PM PDT 24 Mar 12 02:14:39 PM PDT 24 772704812 ps
T387 /workspace/coverage/default/27.sram_ctrl_executable.2361996698 Mar 12 02:24:47 PM PDT 24 Mar 12 02:35:47 PM PDT 24 8423537820 ps
T388 /workspace/coverage/default/26.sram_ctrl_regwen.714127069 Mar 12 02:24:38 PM PDT 24 Mar 12 02:44:43 PM PDT 24 14814147299 ps
T389 /workspace/coverage/default/43.sram_ctrl_stress_all.569831717 Mar 12 02:29:48 PM PDT 24 Mar 12 03:10:18 PM PDT 24 160554088392 ps
T390 /workspace/coverage/default/4.sram_ctrl_ram_cfg.2727869219 Mar 12 02:16:29 PM PDT 24 Mar 12 02:16:33 PM PDT 24 347429803 ps
T391 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3481579925 Mar 12 02:29:22 PM PDT 24 Mar 12 02:30:51 PM PDT 24 4033706877 ps
T392 /workspace/coverage/default/18.sram_ctrl_mem_walk.3406440239 Mar 12 02:21:59 PM PDT 24 Mar 12 02:24:32 PM PDT 24 6966106854 ps
T393 /workspace/coverage/default/43.sram_ctrl_mem_walk.2676601450 Mar 12 02:29:41 PM PDT 24 Mar 12 02:34:53 PM PDT 24 43994695226 ps
T394 /workspace/coverage/default/7.sram_ctrl_alert_test.4036325129 Mar 12 02:18:13 PM PDT 24 Mar 12 02:18:13 PM PDT 24 42291413 ps
T395 /workspace/coverage/default/49.sram_ctrl_max_throughput.2661905797 Mar 12 02:31:35 PM PDT 24 Mar 12 02:31:43 PM PDT 24 2939516698 ps
T396 /workspace/coverage/default/41.sram_ctrl_bijection.4002480908 Mar 12 02:29:07 PM PDT 24 Mar 12 02:54:58 PM PDT 24 44418013541 ps
T397 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3692409350 Mar 12 02:22:45 PM PDT 24 Mar 12 02:24:08 PM PDT 24 5222986586 ps
T112 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2640713442 Mar 12 02:15:51 PM PDT 24 Mar 12 02:16:16 PM PDT 24 3984549213 ps
T398 /workspace/coverage/default/18.sram_ctrl_partial_access.2373279403 Mar 12 02:21:52 PM PDT 24 Mar 12 02:22:00 PM PDT 24 8574169303 ps
T399 /workspace/coverage/default/34.sram_ctrl_alert_test.1495370700 Mar 12 02:27:05 PM PDT 24 Mar 12 02:27:06 PM PDT 24 14790292 ps
T400 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2817931023 Mar 12 02:18:29 PM PDT 24 Mar 12 02:20:56 PM PDT 24 18924179286 ps
T401 /workspace/coverage/default/0.sram_ctrl_alert_test.579878818 Mar 12 02:14:45 PM PDT 24 Mar 12 02:14:46 PM PDT 24 45905442 ps
T402 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.809878770 Mar 12 02:30:41 PM PDT 24 Mar 12 02:30:57 PM PDT 24 1455598350 ps
T403 /workspace/coverage/default/10.sram_ctrl_bijection.258121641 Mar 12 02:18:57 PM PDT 24 Mar 12 03:05:18 PM PDT 24 718954596434 ps
T404 /workspace/coverage/default/42.sram_ctrl_max_throughput.4240135208 Mar 12 02:29:22 PM PDT 24 Mar 12 02:30:52 PM PDT 24 1571969197 ps
T405 /workspace/coverage/default/45.sram_ctrl_multiple_keys.3303197095 Mar 12 02:30:20 PM PDT 24 Mar 12 02:50:05 PM PDT 24 13645503448 ps
T406 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.1993279708 Mar 12 02:21:24 PM PDT 24 Mar 12 02:23:39 PM PDT 24 8658208124 ps
T407 /workspace/coverage/default/27.sram_ctrl_regwen.661638355 Mar 12 02:24:46 PM PDT 24 Mar 12 02:33:59 PM PDT 24 52138058114 ps
T408 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3157443079 Mar 12 02:28:11 PM PDT 24 Mar 12 02:28:21 PM PDT 24 637931946 ps
T409 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2663985058 Mar 12 02:28:12 PM PDT 24 Mar 12 02:29:43 PM PDT 24 2612907208 ps
T410 /workspace/coverage/default/20.sram_ctrl_bijection.4285965442 Mar 12 02:22:36 PM PDT 24 Mar 12 02:40:34 PM PDT 24 46665291259 ps
T411 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.326313177 Mar 12 02:15:22 PM PDT 24 Mar 12 02:22:14 PM PDT 24 15355909481 ps
T412 /workspace/coverage/default/29.sram_ctrl_mem_walk.1915969366 Mar 12 02:25:31 PM PDT 24 Mar 12 02:28:05 PM PDT 24 28688983141 ps
T413 /workspace/coverage/default/21.sram_ctrl_max_throughput.1955562982 Mar 12 02:22:49 PM PDT 24 Mar 12 02:23:18 PM PDT 24 3081147021 ps
T414 /workspace/coverage/default/33.sram_ctrl_alert_test.2095076951 Mar 12 02:26:51 PM PDT 24 Mar 12 02:26:52 PM PDT 24 31291930 ps
T415 /workspace/coverage/default/6.sram_ctrl_max_throughput.2800978229 Mar 12 02:17:24 PM PDT 24 Mar 12 02:19:47 PM PDT 24 1601859045 ps
T416 /workspace/coverage/default/20.sram_ctrl_smoke.843092408 Mar 12 02:22:25 PM PDT 24 Mar 12 02:22:39 PM PDT 24 1544289369 ps
T417 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3092776370 Mar 12 02:30:36 PM PDT 24 Mar 12 02:35:59 PM PDT 24 23699244349 ps
T418 /workspace/coverage/default/25.sram_ctrl_lc_escalation.2691853527 Mar 12 02:24:17 PM PDT 24 Mar 12 02:24:27 PM PDT 24 4941713562 ps
T419 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3787260565 Mar 12 02:23:48 PM PDT 24 Mar 12 02:24:18 PM PDT 24 1132024591 ps
T420 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4083326992 Mar 12 02:29:19 PM PDT 24 Mar 12 02:30:37 PM PDT 24 3239385170 ps
T421 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.827903310 Mar 12 02:29:20 PM PDT 24 Mar 12 02:34:18 PM PDT 24 8495821362 ps
T422 /workspace/coverage/default/0.sram_ctrl_bijection.4113113542 Mar 12 02:14:23 PM PDT 24 Mar 12 02:26:13 PM PDT 24 83415636618 ps
T423 /workspace/coverage/default/40.sram_ctrl_lc_escalation.2574951261 Mar 12 02:29:17 PM PDT 24 Mar 12 02:31:17 PM PDT 24 85537862152 ps
T424 /workspace/coverage/default/21.sram_ctrl_partial_access.1907194138 Mar 12 02:22:48 PM PDT 24 Mar 12 02:24:13 PM PDT 24 1236948860 ps
T425 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2386702698 Mar 12 02:27:58 PM PDT 24 Mar 12 02:29:15 PM PDT 24 15652223234 ps
T426 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2263948705 Mar 12 02:17:41 PM PDT 24 Mar 12 02:20:35 PM PDT 24 8746628167 ps
T427 /workspace/coverage/default/21.sram_ctrl_executable.651654738 Mar 12 02:22:59 PM PDT 24 Mar 12 02:45:57 PM PDT 24 9831890666 ps
T428 /workspace/coverage/default/9.sram_ctrl_max_throughput.2803200048 Mar 12 02:18:36 PM PDT 24 Mar 12 02:18:43 PM PDT 24 1393357868 ps
T429 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3223093868 Mar 12 02:17:58 PM PDT 24 Mar 12 02:25:12 PM PDT 24 66214904724 ps
T430 /workspace/coverage/default/12.sram_ctrl_bijection.11449724 Mar 12 02:19:42 PM PDT 24 Mar 12 02:43:19 PM PDT 24 79987233113 ps
T431 /workspace/coverage/default/3.sram_ctrl_smoke.4149486141 Mar 12 02:15:50 PM PDT 24 Mar 12 02:15:58 PM PDT 24 606874070 ps
T432 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.210180688 Mar 12 02:25:27 PM PDT 24 Mar 12 02:33:24 PM PDT 24 27894827107 ps
T433 /workspace/coverage/default/5.sram_ctrl_executable.3657091492 Mar 12 02:16:56 PM PDT 24 Mar 12 02:23:26 PM PDT 24 19591140953 ps
T434 /workspace/coverage/default/22.sram_ctrl_regwen.4224712698 Mar 12 02:23:17 PM PDT 24 Mar 12 02:40:58 PM PDT 24 11568027729 ps
T435 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1870370757 Mar 12 02:19:51 PM PDT 24 Mar 12 02:34:11 PM PDT 24 34461561339 ps
T436 /workspace/coverage/default/28.sram_ctrl_max_throughput.1189260735 Mar 12 02:25:04 PM PDT 24 Mar 12 02:26:24 PM PDT 24 805962821 ps
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T500 /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3929459862 Mar 12 02:26:45 PM PDT 24 Mar 12 02:27:09 PM PDT 24 1011838854 ps
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T523 /workspace/coverage/default/7.sram_ctrl_regwen.2966776202 Mar 12 02:18:04 PM PDT 24 Mar 12 02:40:46 PM PDT 24 6368268365 ps
T524 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2295834585 Mar 12 02:18:45 PM PDT 24 Mar 12 02:48:00 PM PDT 24 179852486532 ps
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T527 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1049278652 Mar 12 02:14:37 PM PDT 24 Mar 12 02:15:56 PM PDT 24 4943952102 ps
T528 /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3623667300 Mar 12 02:16:38 PM PDT 24 Mar 12 02:18:10 PM PDT 24 10632717464 ps
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T530 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.900240663 Mar 12 02:19:49 PM PDT 24 Mar 12 02:28:43 PM PDT 24 98209103364 ps
T531 /workspace/coverage/default/29.sram_ctrl_lc_escalation.4036005837 Mar 12 02:25:29 PM PDT 24 Mar 12 02:26:45 PM PDT 24 47283302821 ps
T532 /workspace/coverage/default/45.sram_ctrl_lc_escalation.2153807154 Mar 12 02:30:23 PM PDT 24 Mar 12 02:31:18 PM PDT 24 18725458857 ps
T533 /workspace/coverage/default/3.sram_ctrl_regwen.2374403706 Mar 12 02:16:05 PM PDT 24 Mar 12 02:35:57 PM PDT 24 15536632217 ps
T534 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.904443306 Mar 12 02:31:04 PM PDT 24 Mar 12 02:57:59 PM PDT 24 14606542133 ps
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T536 /workspace/coverage/default/1.sram_ctrl_mem_walk.2297618774 Mar 12 02:15:11 PM PDT 24 Mar 12 02:17:39 PM PDT 24 27560532583 ps
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T538 /workspace/coverage/default/33.sram_ctrl_max_throughput.2502287604 Mar 12 02:26:37 PM PDT 24 Mar 12 02:26:45 PM PDT 24 691503834 ps
T539 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3114939298 Mar 12 02:30:47 PM PDT 24 Mar 12 02:32:05 PM PDT 24 3308446547 ps
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