| T789 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3553130939 |
|
|
Mar 12 02:35:57 PM PDT 24 |
Mar 12 02:41:08 PM PDT 24 |
21095826889 ps |
| T790 |
/workspace/coverage/default/36.sram_ctrl_regwen.3194056948 |
|
|
Mar 12 02:27:30 PM PDT 24 |
Mar 12 02:44:05 PM PDT 24 |
38671727283 ps |
| T791 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.23521397 |
|
|
Mar 12 02:22:34 PM PDT 24 |
Mar 12 02:36:25 PM PDT 24 |
13979212279 ps |
| T792 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2657012144 |
|
|
Mar 12 02:24:23 PM PDT 24 |
Mar 12 02:24:24 PM PDT 24 |
23382861 ps |
| T793 |
/workspace/coverage/default/47.sram_ctrl_regwen.2524095904 |
|
|
Mar 12 02:31:04 PM PDT 24 |
Mar 12 02:31:35 PM PDT 24 |
6966576880 ps |
| T794 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.369460622 |
|
|
Mar 12 02:22:58 PM PDT 24 |
Mar 12 02:23:57 PM PDT 24 |
2048508797 ps |
| T795 |
/workspace/coverage/default/37.sram_ctrl_executable.1595722791 |
|
|
Mar 12 02:28:00 PM PDT 24 |
Mar 12 02:50:24 PM PDT 24 |
180723452048 ps |
| T796 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2099861482 |
|
|
Mar 12 02:21:54 PM PDT 24 |
Mar 12 02:22:31 PM PDT 24 |
722529704 ps |
| T797 |
/workspace/coverage/default/9.sram_ctrl_regwen.1549662183 |
|
|
Mar 12 02:18:44 PM PDT 24 |
Mar 12 02:49:52 PM PDT 24 |
40362126403 ps |
| T798 |
/workspace/coverage/default/35.sram_ctrl_bijection.850515450 |
|
|
Mar 12 02:27:12 PM PDT 24 |
Mar 12 03:02:53 PM PDT 24 |
30404439311 ps |
| T799 |
/workspace/coverage/default/8.sram_ctrl_smoke.1484767852 |
|
|
Mar 12 02:18:12 PM PDT 24 |
Mar 12 02:18:19 PM PDT 24 |
492371570 ps |
| T800 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3519038620 |
|
|
Mar 12 02:24:47 PM PDT 24 |
Mar 12 02:24:50 PM PDT 24 |
1464493831 ps |
| T801 |
/workspace/coverage/default/13.sram_ctrl_executable.860773996 |
|
|
Mar 12 02:20:24 PM PDT 24 |
Mar 12 02:26:40 PM PDT 24 |
38573768694 ps |
| T802 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2846246068 |
|
|
Mar 12 02:18:29 PM PDT 24 |
Mar 12 02:18:33 PM PDT 24 |
1407261745 ps |
| T803 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3369054134 |
|
|
Mar 12 02:16:56 PM PDT 24 |
Mar 12 02:31:08 PM PDT 24 |
85314723993 ps |
| T804 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.424752300 |
|
|
Mar 12 02:24:44 PM PDT 24 |
Mar 12 02:27:25 PM PDT 24 |
3005296028 ps |
| T805 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.2917854798 |
|
|
Mar 12 02:25:48 PM PDT 24 |
Mar 12 02:26:03 PM PDT 24 |
3129786712 ps |
| T806 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2919146951 |
|
|
Mar 12 02:23:47 PM PDT 24 |
Mar 12 02:25:14 PM PDT 24 |
2585872703 ps |
| T807 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3274890228 |
|
|
Mar 12 02:21:58 PM PDT 24 |
Mar 12 02:22:01 PM PDT 24 |
799937377 ps |
| T808 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.4147099587 |
|
|
Mar 12 02:27:32 PM PDT 24 |
Mar 12 02:28:58 PM PDT 24 |
14188272192 ps |
| T809 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3817660547 |
|
|
Mar 12 02:19:59 PM PDT 24 |
Mar 12 02:22:17 PM PDT 24 |
9698412902 ps |
| T810 |
/workspace/coverage/default/32.sram_ctrl_regwen.3164438397 |
|
|
Mar 12 02:26:21 PM PDT 24 |
Mar 12 02:35:53 PM PDT 24 |
69081273813 ps |
| T811 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1193198478 |
|
|
Mar 12 02:18:05 PM PDT 24 |
Mar 12 02:19:29 PM PDT 24 |
10427770174 ps |
| T812 |
/workspace/coverage/default/44.sram_ctrl_executable.42405663 |
|
|
Mar 12 02:30:05 PM PDT 24 |
Mar 12 02:35:54 PM PDT 24 |
12815681592 ps |
| T813 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.1671681638 |
|
|
Mar 12 02:26:05 PM PDT 24 |
Mar 12 02:39:23 PM PDT 24 |
58964584451 ps |
| T814 |
/workspace/coverage/default/15.sram_ctrl_bijection.617692123 |
|
|
Mar 12 02:20:51 PM PDT 24 |
Mar 12 02:39:48 PM PDT 24 |
37811956675 ps |
| T815 |
/workspace/coverage/default/45.sram_ctrl_executable.1573797786 |
|
|
Mar 12 02:30:27 PM PDT 24 |
Mar 12 02:46:39 PM PDT 24 |
9618405274 ps |
| T816 |
/workspace/coverage/default/7.sram_ctrl_executable.2661366320 |
|
|
Mar 12 02:18:06 PM PDT 24 |
Mar 12 02:29:59 PM PDT 24 |
12227232636 ps |
| T817 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3092308010 |
|
|
Mar 12 02:14:29 PM PDT 24 |
Mar 12 02:21:53 PM PDT 24 |
32934820635 ps |
| T818 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.2004605732 |
|
|
Mar 12 02:29:09 PM PDT 24 |
Mar 12 02:30:02 PM PDT 24 |
8813920724 ps |
| T819 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3923420898 |
|
|
Mar 12 02:19:50 PM PDT 24 |
Mar 12 02:20:33 PM PDT 24 |
3160759275 ps |
| T820 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3865254228 |
|
|
Mar 12 02:27:31 PM PDT 24 |
Mar 12 02:29:53 PM PDT 24 |
18121698611 ps |
| T821 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2101776194 |
|
|
Mar 12 02:15:58 PM PDT 24 |
Mar 12 02:17:07 PM PDT 24 |
4848964662 ps |
| T822 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2174755672 |
|
|
Mar 12 02:23:47 PM PDT 24 |
Mar 12 02:23:50 PM PDT 24 |
361163778 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_regwen.1738830086 |
|
|
Mar 12 02:30:24 PM PDT 24 |
Mar 12 02:44:21 PM PDT 24 |
37600777262 ps |
| T824 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3825268266 |
|
|
Mar 12 02:20:44 PM PDT 24 |
Mar 12 02:21:32 PM PDT 24 |
1607526068 ps |
| T825 |
/workspace/coverage/default/35.sram_ctrl_alert_test.275580912 |
|
|
Mar 12 02:27:24 PM PDT 24 |
Mar 12 02:27:25 PM PDT 24 |
13048828 ps |
| T826 |
/workspace/coverage/default/49.sram_ctrl_regwen.818463987 |
|
|
Mar 12 02:31:35 PM PDT 24 |
Mar 12 02:48:44 PM PDT 24 |
54721659866 ps |
| T827 |
/workspace/coverage/default/48.sram_ctrl_bijection.560725669 |
|
|
Mar 12 02:31:10 PM PDT 24 |
Mar 12 03:14:20 PM PDT 24 |
309701038146 ps |
| T828 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2645062448 |
|
|
Mar 12 02:23:56 PM PDT 24 |
Mar 12 02:28:39 PM PDT 24 |
54732698174 ps |
| T829 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.468187228 |
|
|
Mar 12 02:22:34 PM PDT 24 |
Mar 12 02:23:56 PM PDT 24 |
26875711751 ps |
| T830 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1963440937 |
|
|
Mar 12 02:23:55 PM PDT 24 |
Mar 12 02:26:54 PM PDT 24 |
2504826051 ps |
| T831 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2820619225 |
|
|
Mar 12 02:18:36 PM PDT 24 |
Mar 12 02:23:34 PM PDT 24 |
14502086544 ps |
| T832 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3292649645 |
|
|
Mar 12 02:21:58 PM PDT 24 |
Mar 12 02:23:57 PM PDT 24 |
79734090327 ps |
| T833 |
/workspace/coverage/default/35.sram_ctrl_smoke.639494490 |
|
|
Mar 12 02:27:06 PM PDT 24 |
Mar 12 02:27:17 PM PDT 24 |
2990998818 ps |
| T834 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.4138891274 |
|
|
Mar 12 02:17:49 PM PDT 24 |
Mar 12 02:40:08 PM PDT 24 |
30881715328 ps |
| T835 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3963920584 |
|
|
Mar 12 02:16:38 PM PDT 24 |
Mar 12 02:21:57 PM PDT 24 |
21506742019 ps |
| T836 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.751734127 |
|
|
Mar 12 02:21:52 PM PDT 24 |
Mar 12 02:22:27 PM PDT 24 |
794325884 ps |
| T837 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2142372111 |
|
|
Mar 12 02:18:45 PM PDT 24 |
Mar 12 02:20:07 PM PDT 24 |
93239967603 ps |
| T838 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.857040674 |
|
|
Mar 12 02:25:58 PM PDT 24 |
Mar 12 02:31:45 PM PDT 24 |
82623119752 ps |
| T839 |
/workspace/coverage/default/6.sram_ctrl_executable.3925077106 |
|
|
Mar 12 02:17:33 PM PDT 24 |
Mar 12 02:34:41 PM PDT 24 |
20983735566 ps |
| T840 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3108300257 |
|
|
Mar 12 02:21:22 PM PDT 24 |
Mar 12 02:33:47 PM PDT 24 |
84572059382 ps |
| T841 |
/workspace/coverage/default/13.sram_ctrl_stress_all.561391921 |
|
|
Mar 12 02:20:31 PM PDT 24 |
Mar 12 02:54:05 PM PDT 24 |
117357104770 ps |
| T842 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.711231182 |
|
|
Mar 12 02:17:34 PM PDT 24 |
Mar 12 02:17:37 PM PDT 24 |
677122213 ps |
| T843 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1347458737 |
|
|
Mar 12 02:29:27 PM PDT 24 |
Mar 12 02:29:31 PM PDT 24 |
344277784 ps |
| T844 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.344665095 |
|
|
Mar 12 02:30:19 PM PDT 24 |
Mar 12 02:30:23 PM PDT 24 |
600319799 ps |
| T845 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.277009506 |
|
|
Mar 12 02:22:33 PM PDT 24 |
Mar 12 02:43:12 PM PDT 24 |
213510540156 ps |
| T846 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2923382885 |
|
|
Mar 12 02:31:14 PM PDT 24 |
Mar 12 02:32:33 PM PDT 24 |
1518873031 ps |
| T847 |
/workspace/coverage/default/37.sram_ctrl_smoke.890388530 |
|
|
Mar 12 02:27:36 PM PDT 24 |
Mar 12 02:27:43 PM PDT 24 |
1779045817 ps |
| T848 |
/workspace/coverage/default/22.sram_ctrl_executable.4265818892 |
|
|
Mar 12 02:23:17 PM PDT 24 |
Mar 12 02:32:16 PM PDT 24 |
49735453784 ps |
| T849 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.682754136 |
|
|
Mar 12 02:24:01 PM PDT 24 |
Mar 12 02:28:34 PM PDT 24 |
8212449380 ps |
| T850 |
/workspace/coverage/default/0.sram_ctrl_smoke.242114014 |
|
|
Mar 12 02:14:23 PM PDT 24 |
Mar 12 02:14:39 PM PDT 24 |
1132616225 ps |
| T851 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.4050690322 |
|
|
Mar 12 02:19:32 PM PDT 24 |
Mar 12 02:23:12 PM PDT 24 |
9469971443 ps |
| T852 |
/workspace/coverage/default/17.sram_ctrl_executable.4167312026 |
|
|
Mar 12 02:21:37 PM PDT 24 |
Mar 12 02:34:17 PM PDT 24 |
31237949543 ps |
| T853 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1172161758 |
|
|
Mar 12 02:26:27 PM PDT 24 |
Mar 12 03:48:03 PM PDT 24 |
2841898089084 ps |
| T854 |
/workspace/coverage/default/40.sram_ctrl_bijection.2375376346 |
|
|
Mar 12 02:28:38 PM PDT 24 |
Mar 12 03:09:13 PM PDT 24 |
158161867918 ps |
| T855 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3522663477 |
|
|
Mar 12 02:15:23 PM PDT 24 |
Mar 12 02:18:38 PM PDT 24 |
22701962890 ps |
| T856 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3559550141 |
|
|
Mar 12 02:26:02 PM PDT 24 |
Mar 12 02:27:40 PM PDT 24 |
3582283406 ps |
| T857 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1220274851 |
|
|
Mar 12 02:21:41 PM PDT 24 |
Mar 12 02:28:47 PM PDT 24 |
298321163502 ps |
| T858 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.17199253 |
|
|
Mar 12 02:24:30 PM PDT 24 |
Mar 12 02:43:12 PM PDT 24 |
13870290616 ps |
| T859 |
/workspace/coverage/default/49.sram_ctrl_partial_access.741488182 |
|
|
Mar 12 02:31:25 PM PDT 24 |
Mar 12 02:31:29 PM PDT 24 |
1432669429 ps |
| T860 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.2594254833 |
|
|
Mar 12 02:22:08 PM PDT 24 |
Mar 12 02:34:26 PM PDT 24 |
76511390006 ps |
| T861 |
/workspace/coverage/default/31.sram_ctrl_partial_access.3901853207 |
|
|
Mar 12 02:26:03 PM PDT 24 |
Mar 12 02:26:28 PM PDT 24 |
1637422669 ps |
| T862 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1622083335 |
|
|
Mar 12 02:17:49 PM PDT 24 |
Mar 12 02:23:37 PM PDT 24 |
10866919630 ps |
| T863 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.2963821246 |
|
|
Mar 12 02:29:09 PM PDT 24 |
Mar 12 02:30:42 PM PDT 24 |
780946189 ps |
| T864 |
/workspace/coverage/default/16.sram_ctrl_smoke.823657523 |
|
|
Mar 12 02:21:13 PM PDT 24 |
Mar 12 02:21:23 PM PDT 24 |
742363813 ps |
| T865 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1797939449 |
|
|
Mar 12 02:21:12 PM PDT 24 |
Mar 12 02:21:13 PM PDT 24 |
36871521 ps |
| T866 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.3361292839 |
|
|
Mar 12 02:21:45 PM PDT 24 |
Mar 12 02:52:58 PM PDT 24 |
66335114953 ps |
| T867 |
/workspace/coverage/default/30.sram_ctrl_regwen.471604662 |
|
|
Mar 12 02:25:56 PM PDT 24 |
Mar 12 02:45:25 PM PDT 24 |
28970755157 ps |
| T868 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.955003615 |
|
|
Mar 12 02:29:22 PM PDT 24 |
Mar 12 02:44:43 PM PDT 24 |
8244458542 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_alert_test.4010046326 |
|
|
Mar 12 02:31:21 PM PDT 24 |
Mar 12 02:31:22 PM PDT 24 |
71029761 ps |
| T870 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3378365954 |
|
|
Mar 12 02:16:01 PM PDT 24 |
Mar 12 02:16:25 PM PDT 24 |
13981299061 ps |
| T871 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.1222328414 |
|
|
Mar 12 02:16:29 PM PDT 24 |
Mar 12 02:39:14 PM PDT 24 |
16104867262 ps |
| T872 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2117431684 |
|
|
Mar 12 02:20:15 PM PDT 24 |
Mar 12 02:25:17 PM PDT 24 |
25468699378 ps |
| T873 |
/workspace/coverage/default/32.sram_ctrl_bijection.2873163560 |
|
|
Mar 12 02:26:22 PM PDT 24 |
Mar 12 02:52:55 PM PDT 24 |
24444492320 ps |
| T874 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1940283856 |
|
|
Mar 12 02:22:15 PM PDT 24 |
Mar 12 02:23:04 PM PDT 24 |
2573284485 ps |
| T875 |
/workspace/coverage/default/19.sram_ctrl_partial_access.460402918 |
|
|
Mar 12 02:22:21 PM PDT 24 |
Mar 12 02:22:26 PM PDT 24 |
1411319861 ps |
| T876 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3006588061 |
|
|
Mar 12 02:24:18 PM PDT 24 |
Mar 12 02:37:27 PM PDT 24 |
7468230516 ps |
| T877 |
/workspace/coverage/default/35.sram_ctrl_partial_access.336027003 |
|
|
Mar 12 02:27:15 PM PDT 24 |
Mar 12 02:27:40 PM PDT 24 |
944326673 ps |
| T878 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.2980065926 |
|
|
Mar 12 02:16:57 PM PDT 24 |
Mar 12 02:17:42 PM PDT 24 |
7943203257 ps |
| T879 |
/workspace/coverage/default/27.sram_ctrl_smoke.2656741753 |
|
|
Mar 12 02:24:39 PM PDT 24 |
Mar 12 02:24:57 PM PDT 24 |
850364389 ps |
| T880 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3365687335 |
|
|
Mar 12 02:29:24 PM PDT 24 |
Mar 12 02:37:56 PM PDT 24 |
12702131515 ps |
| T881 |
/workspace/coverage/default/21.sram_ctrl_regwen.2511406246 |
|
|
Mar 12 02:23:02 PM PDT 24 |
Mar 12 02:24:01 PM PDT 24 |
4643912515 ps |
| T882 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2345170160 |
|
|
Mar 12 02:20:10 PM PDT 24 |
Mar 12 02:49:13 PM PDT 24 |
16040129715 ps |
| T883 |
/workspace/coverage/default/20.sram_ctrl_stress_all.478568832 |
|
|
Mar 12 02:22:42 PM PDT 24 |
Mar 12 03:45:18 PM PDT 24 |
258080820551 ps |
| T884 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.4138474484 |
|
|
Mar 12 02:22:08 PM PDT 24 |
Mar 12 02:27:10 PM PDT 24 |
10928750989 ps |
| T885 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1257557717 |
|
|
Mar 12 02:23:05 PM PDT 24 |
Mar 12 02:23:06 PM PDT 24 |
58354529 ps |
| T886 |
/workspace/coverage/default/45.sram_ctrl_bijection.1008382611 |
|
|
Mar 12 02:30:21 PM PDT 24 |
Mar 12 02:52:44 PM PDT 24 |
169860182437 ps |
| T887 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2466713184 |
|
|
Mar 12 02:17:15 PM PDT 24 |
Mar 12 03:12:00 PM PDT 24 |
75732278618 ps |
| T888 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.765160119 |
|
|
Mar 12 02:21:52 PM PDT 24 |
Mar 12 02:25:54 PM PDT 24 |
2906355323 ps |
| T889 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2192796016 |
|
|
Mar 12 02:14:28 PM PDT 24 |
Mar 12 02:14:57 PM PDT 24 |
4738875095 ps |
| T890 |
/workspace/coverage/default/14.sram_ctrl_executable.3435814795 |
|
|
Mar 12 02:20:45 PM PDT 24 |
Mar 12 02:38:33 PM PDT 24 |
68275467293 ps |
| T891 |
/workspace/coverage/default/33.sram_ctrl_regwen.517188768 |
|
|
Mar 12 02:26:43 PM PDT 24 |
Mar 12 02:32:36 PM PDT 24 |
1747970629 ps |
| T892 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2741825 |
|
|
Mar 12 02:22:40 PM PDT 24 |
Mar 12 02:38:09 PM PDT 24 |
19732387028 ps |
| T893 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2038943529 |
|
|
Mar 12 02:26:28 PM PDT 24 |
Mar 12 02:26:29 PM PDT 24 |
20062245 ps |
| T894 |
/workspace/coverage/default/27.sram_ctrl_partial_access.3515597186 |
|
|
Mar 12 02:24:43 PM PDT 24 |
Mar 12 02:25:00 PM PDT 24 |
1698427840 ps |
| T895 |
/workspace/coverage/default/19.sram_ctrl_bijection.2186332570 |
|
|
Mar 12 02:22:06 PM PDT 24 |
Mar 12 02:46:18 PM PDT 24 |
585302780096 ps |
| T896 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.604471650 |
|
|
Mar 12 02:26:10 PM PDT 24 |
Mar 12 02:26:25 PM PDT 24 |
650077877 ps |
| T897 |
/workspace/coverage/default/11.sram_ctrl_partial_access.4131399503 |
|
|
Mar 12 02:19:32 PM PDT 24 |
Mar 12 02:19:36 PM PDT 24 |
1340895822 ps |
| T898 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.164835187 |
|
|
Mar 12 02:18:57 PM PDT 24 |
Mar 12 02:20:27 PM PDT 24 |
14735758323 ps |
| T899 |
/workspace/coverage/default/39.sram_ctrl_alert_test.3259229730 |
|
|
Mar 12 02:28:33 PM PDT 24 |
Mar 12 02:28:34 PM PDT 24 |
20117723 ps |
| T900 |
/workspace/coverage/default/11.sram_ctrl_regwen.444902077 |
|
|
Mar 12 02:19:41 PM PDT 24 |
Mar 12 02:38:32 PM PDT 24 |
4427817194 ps |
| T901 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3952533551 |
|
|
Mar 12 02:18:56 PM PDT 24 |
Mar 12 02:19:20 PM PDT 24 |
6373095757 ps |
| T902 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3043711670 |
|
|
Mar 12 02:24:08 PM PDT 24 |
Mar 12 02:32:49 PM PDT 24 |
24601140189 ps |
| T903 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3908032592 |
|
|
Mar 12 02:29:38 PM PDT 24 |
Mar 12 02:30:28 PM PDT 24 |
3176891137 ps |
| T904 |
/workspace/coverage/default/43.sram_ctrl_regwen.3657322480 |
|
|
Mar 12 02:29:49 PM PDT 24 |
Mar 12 02:37:06 PM PDT 24 |
11795152672 ps |
| T905 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3916155571 |
|
|
Mar 12 02:22:49 PM PDT 24 |
Mar 12 02:25:41 PM PDT 24 |
9922904350 ps |
| T906 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4270975085 |
|
|
Mar 12 02:16:59 PM PDT 24 |
Mar 12 02:20:54 PM PDT 24 |
14676295953 ps |
| T907 |
/workspace/coverage/default/42.sram_ctrl_executable.3405571926 |
|
|
Mar 12 02:29:22 PM PDT 24 |
Mar 12 02:39:18 PM PDT 24 |
14326257741 ps |
| T908 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3774446061 |
|
|
Mar 12 02:22:24 PM PDT 24 |
Mar 12 03:46:28 PM PDT 24 |
106177172778 ps |
| T909 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2925729819 |
|
|
Mar 12 02:23:54 PM PDT 24 |
Mar 12 02:24:01 PM PDT 24 |
2486633178 ps |
| T910 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1048420645 |
|
|
Mar 12 02:25:40 PM PDT 24 |
Mar 12 02:25:48 PM PDT 24 |
440496861 ps |
| T911 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1655163534 |
|
|
Mar 12 02:27:39 PM PDT 24 |
Mar 12 02:42:18 PM PDT 24 |
49162302219 ps |
| T912 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3505097004 |
|
|
Mar 12 02:25:29 PM PDT 24 |
Mar 12 02:25:32 PM PDT 24 |
1203973695 ps |
| T913 |
/workspace/coverage/default/5.sram_ctrl_alert_test.364480879 |
|
|
Mar 12 02:17:18 PM PDT 24 |
Mar 12 02:17:18 PM PDT 24 |
32028326 ps |
| T914 |
/workspace/coverage/default/26.sram_ctrl_bijection.4097614893 |
|
|
Mar 12 02:24:23 PM PDT 24 |
Mar 12 02:45:24 PM PDT 24 |
263766159763 ps |
| T915 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.821422302 |
|
|
Mar 12 02:15:22 PM PDT 24 |
Mar 12 02:31:30 PM PDT 24 |
18910741877 ps |
| T916 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2879132518 |
|
|
Mar 12 02:22:33 PM PDT 24 |
Mar 12 02:22:38 PM PDT 24 |
456452542 ps |
| T917 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3998084799 |
|
|
Mar 12 02:30:48 PM PDT 24 |
Mar 12 02:31:24 PM PDT 24 |
5442958322 ps |
| T918 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3421393400 |
|
|
Mar 12 02:26:46 PM PDT 24 |
Mar 12 02:27:53 PM PDT 24 |
10292980936 ps |
| T919 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3989163258 |
|
|
Mar 12 02:30:07 PM PDT 24 |
Mar 12 03:25:33 PM PDT 24 |
7802595489 ps |
| T920 |
/workspace/coverage/default/33.sram_ctrl_smoke.1295720550 |
|
|
Mar 12 02:26:29 PM PDT 24 |
Mar 12 02:26:48 PM PDT 24 |
5507766999 ps |
| T921 |
/workspace/coverage/default/35.sram_ctrl_regwen.2728748637 |
|
|
Mar 12 02:27:22 PM PDT 24 |
Mar 12 03:01:24 PM PDT 24 |
60195493707 ps |
| T922 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2666975286 |
|
|
Mar 12 02:21:46 PM PDT 24 |
Mar 12 02:21:47 PM PDT 24 |
15463884 ps |
| T923 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.258362401 |
|
|
Mar 12 02:26:21 PM PDT 24 |
Mar 12 02:26:46 PM PDT 24 |
2612300292 ps |
| T924 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3698803103 |
|
|
Mar 12 02:26:04 PM PDT 24 |
Mar 12 02:30:28 PM PDT 24 |
11910896016 ps |
| T925 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.3677383680 |
|
|
Mar 12 02:27:51 PM PDT 24 |
Mar 12 02:28:39 PM PDT 24 |
51182319764 ps |
| T926 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.657317110 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
82354471 ps |
| T58 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.595905723 |
|
|
Mar 12 12:59:55 PM PDT 24 |
Mar 12 12:59:55 PM PDT 24 |
12974773 ps |
| T59 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2408049922 |
|
|
Mar 12 12:59:52 PM PDT 24 |
Mar 12 12:59:54 PM PDT 24 |
28869009 ps |
| T60 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3236877215 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:00 PM PDT 24 |
81126242 ps |
| T927 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.840141092 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
148005997 ps |
| T928 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1979361817 |
|
|
Mar 12 01:00:07 PM PDT 24 |
Mar 12 01:00:10 PM PDT 24 |
351097748 ps |
| T61 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2300707599 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:57 PM PDT 24 |
14660418703 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.125389413 |
|
|
Mar 12 12:59:56 PM PDT 24 |
Mar 12 12:59:57 PM PDT 24 |
31259927 ps |
| T102 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2023842522 |
|
|
Mar 12 12:59:50 PM PDT 24 |
Mar 12 12:59:51 PM PDT 24 |
55014490 ps |
| T62 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.55898235 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:47 PM PDT 24 |
7055212169 ps |
| T63 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1929277226 |
|
|
Mar 12 12:59:46 PM PDT 24 |
Mar 12 12:59:47 PM PDT 24 |
46026972 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3099622719 |
|
|
Mar 12 12:59:54 PM PDT 24 |
Mar 12 12:59:55 PM PDT 24 |
28696413 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1348420122 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
252726924 ps |
| T929 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1299686583 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
70909755 ps |
| T930 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3976638285 |
|
|
Mar 12 01:00:07 PM PDT 24 |
Mar 12 01:00:10 PM PDT 24 |
303583433 ps |
| T65 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4205271553 |
|
|
Mar 12 12:59:49 PM PDT 24 |
Mar 12 12:59:51 PM PDT 24 |
14053784 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2329108194 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
18214321 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1132936150 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
364433963 ps |
| T105 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2964506474 |
|
|
Mar 12 12:59:50 PM PDT 24 |
Mar 12 12:59:53 PM PDT 24 |
276924196 ps |
| T931 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3076922923 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
75640783 ps |
| T118 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4098925293 |
|
|
Mar 12 12:59:50 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
625198321 ps |
| T932 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.559040788 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:06 PM PDT 24 |
131755282 ps |
| T117 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2182273553 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
171699767 ps |
| T933 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2841761659 |
|
|
Mar 12 12:59:51 PM PDT 24 |
Mar 12 12:59:55 PM PDT 24 |
1704542923 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3753210954 |
|
|
Mar 12 12:59:52 PM PDT 24 |
Mar 12 12:59:54 PM PDT 24 |
95749353 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3132972716 |
|
|
Mar 12 12:59:37 PM PDT 24 |
Mar 12 12:59:38 PM PDT 24 |
15618389 ps |
| T67 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1693493816 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:53 PM PDT 24 |
28159441157 ps |
| T68 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4163599108 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:48 PM PDT 24 |
7421793528 ps |
| T69 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4126650769 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:53 PM PDT 24 |
7067253203 ps |
| T119 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3245664119 |
|
|
Mar 12 12:59:58 PM PDT 24 |
Mar 12 01:00:00 PM PDT 24 |
245609851 ps |
| T934 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.732663454 |
|
|
Mar 12 12:59:47 PM PDT 24 |
Mar 12 12:59:49 PM PDT 24 |
44225709 ps |
| T935 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4079086587 |
|
|
Mar 12 12:59:53 PM PDT 24 |
Mar 12 12:59:54 PM PDT 24 |
27246429 ps |
| T936 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3653959251 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:06 PM PDT 24 |
1020843692 ps |
| T937 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.552676775 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
366418889 ps |
| T70 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.601605227 |
|
|
Mar 12 01:00:11 PM PDT 24 |
Mar 12 01:01:05 PM PDT 24 |
13834601580 ps |
| T71 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3644193988 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:29 PM PDT 24 |
14759569224 ps |
| T938 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.933094029 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:06 PM PDT 24 |
1398989711 ps |
| T939 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2007509104 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
157442199 ps |
| T93 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3691585258 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:00 PM PDT 24 |
17032908 ps |
| T940 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.547291395 |
|
|
Mar 12 12:59:43 PM PDT 24 |
Mar 12 12:59:44 PM PDT 24 |
31519409 ps |
| T941 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1114461843 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
83472722 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1879527861 |
|
|
Mar 12 01:00:07 PM PDT 24 |
Mar 12 01:00:08 PM PDT 24 |
52347715 ps |
| T943 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.328523829 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
39096533 ps |
| T944 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2995145307 |
|
|
Mar 12 01:00:04 PM PDT 24 |
Mar 12 01:00:07 PM PDT 24 |
1432196889 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3914119720 |
|
|
Mar 12 12:59:56 PM PDT 24 |
Mar 12 12:59:57 PM PDT 24 |
21431880 ps |
| T946 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.606654711 |
|
|
Mar 12 01:00:21 PM PDT 24 |
Mar 12 01:00:23 PM PDT 24 |
37935182 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2201348742 |
|
|
Mar 12 12:59:51 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
14212563 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2442428491 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
1455720364 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2588631110 |
|
|
Mar 12 12:59:57 PM PDT 24 |
Mar 12 12:59:58 PM PDT 24 |
68577310 ps |
| T72 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2530533000 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:23 PM PDT 24 |
7608815519 ps |
| T950 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3381403327 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:06 PM PDT 24 |
1431860335 ps |
| T951 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2069839213 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:03 PM PDT 24 |
105489458 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3511825272 |
|
|
Mar 12 12:59:57 PM PDT 24 |
Mar 12 12:59:58 PM PDT 24 |
13736038 ps |
| T953 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1270307446 |
|
|
Mar 12 12:59:58 PM PDT 24 |
Mar 12 01:00:03 PM PDT 24 |
1451355418 ps |
| T123 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3662506487 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
483227420 ps |
| T954 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3364811288 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
687642036 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.223279032 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:03 PM PDT 24 |
22137236 ps |
| T125 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1528081942 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
130975524 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.255523260 |
|
|
Mar 12 12:59:55 PM PDT 24 |
Mar 12 12:59:59 PM PDT 24 |
355743006 ps |
| T82 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2011935212 |
|
|
Mar 12 12:59:47 PM PDT 24 |
Mar 12 01:00:14 PM PDT 24 |
8013088024 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2191735654 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
92466273 ps |
| T80 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3070394372 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:27 PM PDT 24 |
15758791643 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1959223865 |
|
|
Mar 12 12:59:53 PM PDT 24 |
Mar 12 12:59:55 PM PDT 24 |
34647303 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1151907391 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
76080012 ps |
| T81 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3478232715 |
|
|
Mar 12 12:59:52 PM PDT 24 |
Mar 12 01:00:20 PM PDT 24 |
3851460774 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1136407256 |
|
|
Mar 12 12:59:46 PM PDT 24 |
Mar 12 12:59:51 PM PDT 24 |
1499007547 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2707608698 |
|
|
Mar 12 12:59:57 PM PDT 24 |
Mar 12 12:59:58 PM PDT 24 |
53822162 ps |
| T962 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4176549948 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
44855594 ps |
| T963 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.113730553 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:49 PM PDT 24 |
14437622064 ps |
| T964 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3931049705 |
|
|
Mar 12 12:59:57 PM PDT 24 |
Mar 12 12:59:58 PM PDT 24 |
15096074 ps |
| T965 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3733355292 |
|
|
Mar 12 12:59:57 PM PDT 24 |
Mar 12 12:59:58 PM PDT 24 |
76170459 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1255882116 |
|
|
Mar 12 12:59:56 PM PDT 24 |
Mar 12 01:01:10 PM PDT 24 |
78338562624 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1438467193 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:06 PM PDT 24 |
436836261 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.526635516 |
|
|
Mar 12 12:59:57 PM PDT 24 |
Mar 12 12:59:58 PM PDT 24 |
12753016 ps |
| T126 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.46710993 |
|
|
Mar 12 01:00:06 PM PDT 24 |
Mar 12 01:00:08 PM PDT 24 |
861868284 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1099065169 |
|
|
Mar 12 12:59:55 PM PDT 24 |
Mar 12 12:59:59 PM PDT 24 |
352837980 ps |
| T970 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2038311822 |
|
|
Mar 12 12:59:56 PM PDT 24 |
Mar 12 12:59:56 PM PDT 24 |
28464845 ps |
| T971 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2383118354 |
|
|
Mar 12 12:59:56 PM PDT 24 |
Mar 12 12:59:57 PM PDT 24 |
11996300 ps |
| T972 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2101092299 |
|
|
Mar 12 01:00:02 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
218138649 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.139948985 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
1390301589 ps |
| T974 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2429957661 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:00 PM PDT 24 |
18320088 ps |
| T975 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.761134950 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
95459224 ps |
| T976 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2697189005 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
358551669 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1790190872 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:03 PM PDT 24 |
131443927 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3028949587 |
|
|
Mar 12 12:59:51 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
40228857 ps |
| T120 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.685601956 |
|
|
Mar 12 12:59:50 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
549995385 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.541728920 |
|
|
Mar 12 12:59:50 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
25077489 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2034007781 |
|
|
Mar 12 01:00:05 PM PDT 24 |
Mar 12 01:00:06 PM PDT 24 |
19077981 ps |
| T981 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2486227846 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:24 PM PDT 24 |
3778146475 ps |
| T982 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3333295613 |
|
|
Mar 12 12:59:49 PM PDT 24 |
Mar 12 12:59:53 PM PDT 24 |
361984296 ps |
| T121 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.536226170 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
640566817 ps |
| T983 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2877478553 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:04 PM PDT 24 |
1560529238 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1407409600 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:03 PM PDT 24 |
14507731 ps |
| T985 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.726730864 |
|
|
Mar 12 12:59:56 PM PDT 24 |
Mar 12 12:59:57 PM PDT 24 |
43676592 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1084626822 |
|
|
Mar 12 12:59:59 PM PDT 24 |
Mar 12 01:00:00 PM PDT 24 |
15226480 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3990607937 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:07 PM PDT 24 |
1413881743 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2451732109 |
|
|
Mar 12 12:59:47 PM PDT 24 |
Mar 12 12:59:48 PM PDT 24 |
52324643 ps |
| T989 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1073993552 |
|
|
Mar 12 12:59:46 PM PDT 24 |
Mar 12 12:59:50 PM PDT 24 |
39249469 ps |
| T990 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1165230069 |
|
|
Mar 12 12:59:58 PM PDT 24 |
Mar 12 12:59:59 PM PDT 24 |
33668621 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1255166173 |
|
|
Mar 12 12:59:58 PM PDT 24 |
Mar 12 12:59:59 PM PDT 24 |
83638155 ps |
| T992 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.4104562528 |
|
|
Mar 12 01:00:00 PM PDT 24 |
Mar 12 01:00:24 PM PDT 24 |
3822481495 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.793543880 |
|
|
Mar 12 12:59:57 PM PDT 24 |
Mar 12 01:00:47 PM PDT 24 |
15985221088 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.429598158 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:03 PM PDT 24 |
41619272 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1603011012 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:05 PM PDT 24 |
722003575 ps |
| T996 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3648545735 |
|
|
Mar 12 12:59:58 PM PDT 24 |
Mar 12 12:59:59 PM PDT 24 |
55826941 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3317888183 |
|
|
Mar 12 12:59:47 PM PDT 24 |
Mar 12 12:59:48 PM PDT 24 |
16815951 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.502406795 |
|
|
Mar 12 12:59:55 PM PDT 24 |
Mar 12 12:59:56 PM PDT 24 |
43143491 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1935535117 |
|
|
Mar 12 12:59:35 PM PDT 24 |
Mar 12 01:00:07 PM PDT 24 |
15406719912 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.687931228 |
|
|
Mar 12 12:59:54 PM PDT 24 |
Mar 12 12:59:58 PM PDT 24 |
147990272 ps |
| T124 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2728648148 |
|
|
Mar 12 01:00:03 PM PDT 24 |
Mar 12 01:00:06 PM PDT 24 |
1067346800 ps |
| T1001 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1989080012 |
|
|
Mar 12 01:00:01 PM PDT 24 |
Mar 12 01:00:02 PM PDT 24 |
31122040 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1157922882 |
|
|
Mar 12 12:59:49 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
478170617 ps |
| T1002 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3884932591 |
|
|
Mar 12 01:00:07 PM PDT 24 |
Mar 12 01:01:05 PM PDT 24 |
28214009358 ps |