Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15865102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153619540

1

T1

487084

T2

142849

T3

47717

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83512169	1			T1	267489		T2	78617		T3	130562
values[0x0]	41413209	1			T1	129054		T2	37669		T3	44227
values[0x1]	44559264	1			T1	138944		T2	40770		T3	86650

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8062107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161422535

1

T1

511333

T2

150019

T3

155255

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1247967	1			T1	2062		T2	615		T3	1034
valid_sources[0x01]	549678	1			T1	2180		T2	589		T3	983
valid_sources[0x02]	630275	1			T1	2092		T2	661		T3	1062
valid_sources[0x03]	524207	1			T1	2061		T2	663		T3	1010
valid_sources[0x04]	549585	1			T1	2088		T2	639		T3	1043
valid_sources[0x05]	571417	1			T1	2059		T2	648		T3	976
valid_sources[0x06]	511763	1			T1	2123		T2	621		T3	968
valid_sources[0x07]	523150	1			T1	2046		T2	597		T3	1000
valid_sources[0x08]	522939	1			T1	2111		T2	606		T3	1063
valid_sources[0x09]	597398	1			T1	2155		T2	538		T3	969
valid_sources[0x0a]	568480	1			T1	2061		T2	642		T3	1015
valid_sources[0x0b]	783382	1			T1	2136		T2	612		T3	1021
valid_sources[0x0c]	570489	1			T1	2146		T2	614		T3	1128
valid_sources[0x0d]	546302	1			T1	2157		T2	565		T3	1079
valid_sources[0x0e]	577372	1			T1	2115		T2	637		T3	1120
valid_sources[0x0f]	508492	1			T1	2035		T2	626		T3	988
valid_sources[0x10]	536149	1			T1	2126		T2	658		T3	1039
valid_sources[0x11]	1578419	1			T1	2072		T2	602		T3	974
valid_sources[0x12]	551766	1			T1	2035		T2	642		T3	1009
valid_sources[0x13]	531007	1			T1	2081		T2	616		T3	1017
valid_sources[0x14]	2342104	1			T1	2057		T2	579		T3	1025
valid_sources[0x15]	512003	1			T1	2131		T2	621		T3	1039
valid_sources[0x16]	580045	1			T1	1994		T2	658		T3	969
valid_sources[0x17]	2150380	1			T1	2095		T2	599		T3	1113
valid_sources[0x18]	539168	1			T1	2086		T2	581		T3	990
valid_sources[0x19]	532423	1			T1	2024		T2	592		T3	1007
valid_sources[0x1a]	568113	1			T1	2120		T2	628		T3	1002
valid_sources[0x1b]	575767	1			T1	2106		T2	598		T3	978
valid_sources[0x1c]	531648	1			T1	2101		T2	614		T3	1049
valid_sources[0x1d]	512006	1			T1	2108		T2	625		T3	1021
valid_sources[0x1e]	561476	1			T1	2034		T2	598		T3	1030
valid_sources[0x1f]	1566842	1			T1	2097		T2	600		T3	1034
valid_sources[0x20]	923638	1			T1	2082		T2	608		T3	1082
valid_sources[0x21]	577707	1			T1	2062		T2	587		T3	995
valid_sources[0x22]	605002	1			T1	1997		T2	594		T3	1011
valid_sources[0x23]	506189	1			T1	2091		T2	625		T3	992
valid_sources[0x24]	593039	1			T1	2152		T2	670		T3	1011
valid_sources[0x25]	554292	1			T1	2064		T2	648		T3	980
valid_sources[0x26]	555072	1			T1	2083		T2	634		T3	1002
valid_sources[0x27]	526431	1			T1	2110		T2	597		T3	1030
valid_sources[0x28]	522568	1			T1	2076		T2	608		T3	1062
valid_sources[0x29]	2086613	1			T1	2154		T2	646		T3	1071
valid_sources[0x2a]	511562	1			T1	2066		T2	644		T3	1036
valid_sources[0x2b]	581715	1			T1	2045		T2	634		T3	1018
valid_sources[0x2c]	563575	1			T1	2101		T2	634		T3	1042
valid_sources[0x2d]	538141	1			T1	2060		T2	604		T3	1004
valid_sources[0x2e]	575201	1			T1	2099		T2	609		T3	1011
valid_sources[0x2f]	525367	1			T1	2107		T2	634		T3	993
valid_sources[0x30]	588048	1			T1	2114		T2	600		T3	1033
valid_sources[0x31]	566055	1			T1	2051		T2	574		T3	996
valid_sources[0x32]	536699	1			T1	2110		T2	660		T3	1107
valid_sources[0x33]	606573	1			T1	2104		T2	627		T3	958
valid_sources[0x34]	533638	1			T1	2123		T2	596		T3	1017
valid_sources[0x35]	522310	1			T1	2051		T2	577		T3	1004
valid_sources[0x36]	511443	1			T1	2100		T2	623		T3	1085
valid_sources[0x37]	554995	1			T1	2035		T2	619		T3	1059
valid_sources[0x38]	533554	1			T1	2047		T2	596		T3	1035
valid_sources[0x39]	518674	1			T1	2058		T2	572		T3	1024
valid_sources[0x3a]	539623	1			T1	2052		T2	569		T3	941
valid_sources[0x3b]	536832	1			T1	2106		T2	641		T3	950
valid_sources[0x3c]	512353	1			T1	2076		T2	596		T3	1050
valid_sources[0x3d]	584420	1			T1	2019		T2	598		T3	1009
valid_sources[0x3e]	515506	1			T1	2049		T2	649		T3	1048
valid_sources[0x3f]	531826	1			T1	2084		T2	598		T3	961
valid_sources[0x40]	579545	1			T1	2076		T2	634		T3	983
valid_sources[0x41]	549194	1			T1	2116		T2	581		T3	1030
valid_sources[0x42]	534022	1			T1	2072		T2	583		T3	1089
valid_sources[0x43]	708202	1			T1	2112		T2	601		T3	1014
valid_sources[0x44]	672938	1			T1	2063		T2	608		T3	998
valid_sources[0x45]	563815	1			T1	2039		T2	579		T3	1062
valid_sources[0x46]	587190	1			T1	2037		T2	610		T3	995
valid_sources[0x47]	511389	1			T1	2078		T2	577		T3	1010
valid_sources[0x48]	525581	1			T1	2054		T2	582		T3	1062
valid_sources[0x49]	649631	1			T1	2163		T2	586		T3	1024
valid_sources[0x4a]	723846	1			T1	2080		T2	612		T3	1051
valid_sources[0x4b]	529548	1			T1	2033		T2	628		T3	1027
valid_sources[0x4c]	572791	1			T1	2067		T2	603		T3	916
valid_sources[0x4d]	558081	1			T1	2075		T2	608		T3	1027
valid_sources[0x4e]	547886	1			T1	2173		T2	520		T3	952
valid_sources[0x4f]	520656	1			T1	2116		T2	598		T3	992
valid_sources[0x50]	552184	1			T1	2153		T2	643		T3	1015
valid_sources[0x51]	523823	1			T1	2124		T2	581		T3	1018
valid_sources[0x52]	520772	1			T1	2115		T2	608		T3	957
valid_sources[0x53]	534036	1			T1	2100		T2	599		T3	988
valid_sources[0x54]	628066	1			T1	2069		T2	642		T3	1021
valid_sources[0x55]	507157	1			T1	2058		T2	593		T3	1035
valid_sources[0x56]	689238	1			T1	2112		T2	584		T3	1014
valid_sources[0x57]	559406	1			T1	2153		T2	601		T3	1019
valid_sources[0x58]	616497	1			T1	2105		T2	660		T3	968
valid_sources[0x59]	529116	1			T1	2102		T2	581		T3	979
valid_sources[0x5a]	526438	1			T1	1977		T2	554		T3	1056
valid_sources[0x5b]	564870	1			T1	2038		T2	630		T3	1020
valid_sources[0x5c]	540779	1			T1	2134		T2	581		T3	1058
valid_sources[0x5d]	532381	1			T1	2066		T2	637		T3	1061
valid_sources[0x5e]	566950	1			T1	2106		T2	634		T3	1016
valid_sources[0x5f]	542643	1			T1	2016		T2	634		T3	1038
valid_sources[0x60]	579778	1			T1	2109		T2	602		T3	998
valid_sources[0x61]	537178	1			T1	2093		T2	598		T3	1034
valid_sources[0x62]	577886	1			T1	2096		T2	640		T3	1032
valid_sources[0x63]	531422	1			T1	2146		T2	615		T3	981
valid_sources[0x64]	574285	1			T1	1977		T2	620		T3	1043
valid_sources[0x65]	558598	1			T1	2095		T2	621		T3	1040
valid_sources[0x66]	568662	1			T1	2079		T2	603		T3	964
valid_sources[0x67]	637583	1			T1	2029		T2	560		T3	968
valid_sources[0x68]	535207	1			T1	2079		T2	714		T3	1042
valid_sources[0x69]	597785	1			T1	2074		T2	617		T3	1085
valid_sources[0x6a]	531401	1			T1	2131		T2	651		T3	1061
valid_sources[0x6b]	518675	1			T1	2127		T2	654		T3	935
valid_sources[0x6c]	3446192	1			T1	2005		T2	602		T3	1062
valid_sources[0x6d]	524801	1			T1	2072		T2	578		T3	1023
valid_sources[0x6e]	538970	1			T1	2130		T2	577		T3	1016
valid_sources[0x6f]	561030	1			T1	2083		T2	549		T3	1028
valid_sources[0x70]	560794	1			T1	2058		T2	638		T3	1008
valid_sources[0x71]	583008	1			T1	2075		T2	625		T3	1052
valid_sources[0x72]	543744	1			T1	2166		T2	628		T3	1030
valid_sources[0x73]	650603	1			T1	2030		T2	667		T3	1069
valid_sources[0x74]	668747	1			T1	2134		T2	616		T3	1046
valid_sources[0x75]	601064	1			T1	2091		T2	605		T3	1016
valid_sources[0x76]	539557	1			T1	2062		T2	613		T3	1038
valid_sources[0x77]	1071960	1			T1	2128		T2	631		T3	1011
valid_sources[0x78]	524107	1			T1	2167		T2	602		T3	1014
valid_sources[0x79]	581379	1			T1	2115		T2	599		T3	1044
valid_sources[0x7a]	523540	1			T1	2039		T2	594		T3	995
valid_sources[0x7b]	530898	1			T1	2065		T2	656		T3	1082
valid_sources[0x7c]	546409	1			T1	2078		T2	609		T3	1038
valid_sources[0x7d]	547314	1			T1	2115		T2	588		T3	1007
valid_sources[0x7e]	530761	1			T1	2097		T2	541		T3	962
valid_sources[0x7f]	555691	1			T1	2139		T2	615		T3	1019
valid_sources[0x80]	506301	1			T1	2119		T2	598		T3	996

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75540671

1

T1

243346

T2

71561

T3

23848

values[0x0]

all_enables

biggest_size

39045750

1

T1

121688

T2

35571

T3

11986

values[0x1]

all_enables

biggest_size

39033119

1

T1

122050

T2

35717

T3

11883

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162331

1

T1

37

T2

25

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58018	1			T1	17		T2	22		T5	21
values[0x0]	67734	1			T1	49		T2	42		T3	2
values[0x1]	72840	1			T1	50		T2	42		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

171281

1

T1

42

T2

36

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1129	1			T5	46		T18	2		T30	2
valid_sources[0x01]	924	1			T2	1		T30	5		T58	1
valid_sources[0x02]	611	1			T1	1		T2	1		T30	10
valid_sources[0x03]	652	1			T1	1		T2	1		T30	1
valid_sources[0x04]	555	1			T2	2		T30	1		T31	2
valid_sources[0x05]	573	1			T1	1		T15	1		T31	2
valid_sources[0x06]	1053	1			T2	2		T30	9		T31	15
valid_sources[0x07]	657	1			T31	1		T26	2		T32	6
valid_sources[0x08]	624	1			T2	1		T31	6		T32	6
valid_sources[0x09]	1002	1			T30	8		T31	4		T32	4
valid_sources[0x0a]	853	1			T30	11		T31	1		T32	10
valid_sources[0x0b]	699	1			T30	5		T31	3		T32	6
valid_sources[0x0c]	700	1			T18	1		T30	1		T15	2
valid_sources[0x0d]	1055	1			T1	1		T30	1		T31	2
valid_sources[0x0e]	759	1			T30	3		T31	6		T32	7
valid_sources[0x0f]	737	1			T2	1		T30	1		T31	13
valid_sources[0x10]	571	1			T30	4		T31	3		T26	1
valid_sources[0x11]	676	1			T1	1		T2	1		T30	3
valid_sources[0x12]	668	1			T30	1		T31	11		T32	8
valid_sources[0x13]	707	1			T1	1		T30	1		T25	3
valid_sources[0x14]	732	1			T30	4		T31	9		T32	11
valid_sources[0x15]	739	1			T30	3		T32	4		T6	4
valid_sources[0x16]	960	1			T31	1		T32	7		T50	24
valid_sources[0x17]	712	1			T2	1		T30	5		T58	1
valid_sources[0x18]	625	1			T30	1		T32	8		T79	1
valid_sources[0x19]	784	1			T30	2		T31	9		T32	6
valid_sources[0x1a]	543	1			T30	7		T31	1		T26	2
valid_sources[0x1b]	680	1			T1	2		T31	19		T32	3
valid_sources[0x1c]	585	1			T30	4		T31	13		T32	9
valid_sources[0x1d]	567	1			T2	1		T30	7		T15	1
valid_sources[0x1e]	582	1			T1	2		T30	1		T31	6
valid_sources[0x1f]	919	1			T30	3		T31	22		T32	4
valid_sources[0x20]	889	1			T30	5		T32	6		T50	11
valid_sources[0x21]	624	1			T30	3		T31	8		T32	4
valid_sources[0x22]	749	1			T2	1		T30	5		T31	3
valid_sources[0x23]	722	1			T25	6		T26	1		T32	7
valid_sources[0x24]	529	1			T31	10		T32	3		T50	7
valid_sources[0x25]	1071	1			T2	1		T30	12		T31	7
valid_sources[0x26]	1035	1			T30	2		T31	5		T26	1
valid_sources[0x27]	858	1			T1	1		T30	2		T31	3
valid_sources[0x28]	609	1			T1	2		T31	5		T26	1
valid_sources[0x29]	818	1			T2	1		T30	6		T15	1
valid_sources[0x2a]	927	1			T1	1		T30	8		T31	7
valid_sources[0x2b]	570	1			T2	1		T31	1		T26	1
valid_sources[0x2c]	730	1			T2	1		T30	9		T31	2
valid_sources[0x2d]	761	1			T31	5		T32	4		T50	12
valid_sources[0x2e]	709	1			T1	1		T2	1		T18	1
valid_sources[0x2f]	856	1			T1	2		T30	4		T32	7
valid_sources[0x30]	712	1			T1	1		T2	1		T30	1
valid_sources[0x31]	514	1			T12	1		T30	5		T25	1
valid_sources[0x32]	731	1			T1	2		T2	1		T30	3
valid_sources[0x33]	1099	1			T2	1		T30	1		T31	2
valid_sources[0x34]	914	1			T1	1		T2	1		T11	3
valid_sources[0x35]	649	1			T1	1		T2	2		T30	2
valid_sources[0x36]	495	1			T30	3		T31	4		T32	6
valid_sources[0x37]	720	1			T31	4		T26	1		T16	13
valid_sources[0x38]	603	1			T1	1		T2	1		T30	3
valid_sources[0x39]	866	1			T2	1		T30	1		T31	5
valid_sources[0x3a]	826	1			T2	1		T9	1		T30	4
valid_sources[0x3b]	790	1			T2	1		T30	5		T31	2
valid_sources[0x3c]	852	1			T30	6		T31	6		T32	6
valid_sources[0x3d]	771	1			T1	7		T30	7		T31	11
valid_sources[0x3e]	786	1			T2	2		T30	12		T31	1
valid_sources[0x3f]	536	1			T1	1		T30	17		T25	1
valid_sources[0x40]	599	1			T1	2		T30	2		T57	4
valid_sources[0x41]	697	1			T18	1		T31	6		T32	2
valid_sources[0x42]	990	1			T30	7		T31	10		T32	5
valid_sources[0x43]	839	1			T1	1		T2	1		T30	8
valid_sources[0x44]	712	1			T1	1		T2	1		T31	4
valid_sources[0x45]	678	1			T1	1		T30	5		T31	7
valid_sources[0x46]	865	1			T30	4		T31	2		T26	1
valid_sources[0x47]	853	1			T31	6		T32	5		T50	13
valid_sources[0x48]	682	1			T2	1		T30	4		T31	3
valid_sources[0x49]	678	1			T30	9		T31	1		T26	1
valid_sources[0x4a]	793	1			T30	7		T31	5		T26	1
valid_sources[0x4b]	908	1			T18	1		T30	2		T15	1
valid_sources[0x4c]	904	1			T2	1		T30	4		T31	6
valid_sources[0x4d]	842	1			T2	3		T14	3		T30	1
valid_sources[0x4e]	588	1			T1	3		T2	1		T31	1
valid_sources[0x4f]	519	1			T30	1		T31	1		T32	6
valid_sources[0x50]	1028	1			T31	7		T16	16		T32	4
valid_sources[0x51]	894	1			T30	4		T31	4		T26	3
valid_sources[0x52]	655	1			T30	5		T31	1		T26	1
valid_sources[0x53]	732	1			T2	1		T30	10		T31	7
valid_sources[0x54]	916	1			T30	3		T31	5		T13	1
valid_sources[0x55]	1086	1			T1	2		T30	8		T32	2
valid_sources[0x56]	642	1			T30	2		T31	9		T32	10
valid_sources[0x57]	864	1			T2	2		T30	1		T31	3
valid_sources[0x58]	606	1			T18	4		T30	16		T31	5
valid_sources[0x59]	592	1			T18	1		T15	1		T31	2
valid_sources[0x5a]	788	1			T1	2		T30	1		T32	5
valid_sources[0x5b]	1012	1			T18	1		T31	7		T32	7
valid_sources[0x5c]	821	1			T2	3		T30	4		T31	3
valid_sources[0x5d]	867	1			T2	1		T30	5		T31	3
valid_sources[0x5e]	553	1			T30	9		T31	5		T26	1
valid_sources[0x5f]	733	1			T31	6		T32	5		T6	2
valid_sources[0x60]	619	1			T30	4		T31	4		T26	2
valid_sources[0x61]	649	1			T2	1		T3	1		T31	12
valid_sources[0x62]	627	1			T30	8		T25	3		T32	6
valid_sources[0x63]	583	1			T1	1		T2	2		T30	8
valid_sources[0x64]	1138	1			T2	1		T30	1		T15	2
valid_sources[0x65]	1002	1			T2	2		T30	2		T26	1
valid_sources[0x66]	979	1			T1	1		T31	7		T32	7
valid_sources[0x67]	666	1			T1	2		T30	1		T31	6
valid_sources[0x68]	837	1			T1	1		T2	1		T30	19
valid_sources[0x69]	733	1			T2	1		T4	1		T31	10
valid_sources[0x6a]	824	1			T1	2		T3	1		T30	3
valid_sources[0x6b]	1002	1			T1	6		T2	1		T30	4
valid_sources[0x6c]	804	1			T1	3		T30	1		T31	11
valid_sources[0x6d]	745	1			T30	5		T31	3		T32	6
valid_sources[0x6e]	610	1			T18	1		T30	3		T31	1
valid_sources[0x6f]	1048	1			T30	5		T31	17		T32	5
valid_sources[0x70]	568	1			T2	3		T30	9		T31	6
valid_sources[0x71]	621	1			T2	1		T3	1		T18	2
valid_sources[0x72]	676	1			T2	1		T30	7		T31	6
valid_sources[0x73]	619	1			T30	1		T31	5		T13	1
valid_sources[0x74]	693	1			T30	2		T31	5		T32	8
valid_sources[0x75]	1090	1			T30	2		T31	1		T32	5
valid_sources[0x76]	1161	1			T2	1		T31	1		T32	10
valid_sources[0x77]	669	1			T2	1		T30	7		T31	9
valid_sources[0x78]	751	1			T30	3		T31	5		T32	5
valid_sources[0x79]	634	1			T30	4		T31	5		T32	8
valid_sources[0x7a]	785	1			T1	2		T31	11		T26	2
valid_sources[0x7b]	670	1			T30	5		T31	4		T26	1
valid_sources[0x7c]	675	1			T2	1		T30	6		T25	2
valid_sources[0x7d]	646	1			T15	1		T31	12		T26	1
valid_sources[0x7e]	666	1			T1	1		T30	5		T31	3
valid_sources[0x7f]	750	1			T30	2		T31	11		T32	1
valid_sources[0x80]	643	1			T1	1		T31	3		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44480

1

T1

8

T2

9

T5

10

values[0x0]

all_enables

biggest_size

59753

1

T1

21

T2

10

T3

1

values[0x1]

all_enables

biggest_size

58098

1

T1

8

T2

6

T5

2