Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15822302

1

T1

44611

T2

11760

T3

213722

full_word

150735827

1

T1

449522

T2

118691

T3

47717

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	166557769	1			T1	494133		T2	130451		T3	261439
auto[TlIntgErrCmd]	121	1			T105	6		T106	1		T107	7
auto[TlIntgErrData]	116	1			T105	6		T106	5		T107	7
auto[TlIntgErrBoth]	123	1			T105	8		T106	4		T107	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80477238

1

T1

226135

T2

52012

T3

130562

auto[1]

86080891

1

T1

267998

T2

78439

T3

130877

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7740024	1			T1	20351		T2	4609		T3	106714
auto[TlIntgErrNone]	partial	auto[1]	8081944	1			T1	24260		T2	7151		T3	107008
auto[TlIntgErrNone]	full_word	auto[0]	72737036	1			T1	205784		T2	47403		T3	23848
auto[TlIntgErrNone]	full_word	auto[1]	77998765	1			T1	243738		T2	71288		T3	23869
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T105	3		T107	3		T120	4
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T105	3		T106	1		T107	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T107	1		T128	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T120	1		T130	2		T131	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T105	4		T106	4		T107	5
auto[TlIntgErrData]	partial	auto[1]	45	1			T105	2		T106	1		T107	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T107	1		T127	2		T122	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T122	1		T130	1		T121	2
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T105	4		T106	1		T107	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T105	3		T106	3		T107	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T105	1		T126	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T127	1		T125	1		T126	1