Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	668341	1			T4	2163		T12	141		T13	13448
auto[1]	11037055	1			T1	67809		T2	600		T3	13610
auto[2]	523461	1			T4	2151		T12	98		T13	12304
auto[3]	10786444	1			T1	66403		T2	523		T3	13523

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14759697	1			T1	112398		T2	782		T3	357
auto[1]	2108129	1			T1	10371		T2	168		T3	3169
auto[2]	2134728	1			T1	10396		T2	144		T3	3070
auto[3]	4012747	1			T1	1047		T2	29		T3	20537

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9466095

1

T1

134204

T2

1123

T3

7

auto[1]

13549206

1

T1

8

T3

27126

T9

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	274334	1			T12	5		T13	11105		T47	2103
auto[0]	auto[0]	auto[1]	28531	1			T4	26		T12	14		T13	1120
auto[0]	auto[0]	auto[2]	28894	1			T4	23		T12	15		T13	1122
auto[0]	auto[0]	auto[3]	69254	1			T4	2114		T12	107		T13	100
auto[0]	auto[1]	auto[0]	3285307	1			T1	56734		T2	421		T8	68
auto[0]	auto[1]	auto[1]	349253	1			T1	4989		T2	125		T8	246
auto[0]	auto[1]	auto[2]	366072	1			T1	5564		T2	36		T8	306
auto[0]	auto[1]	auto[3]	475327	1			T1	520		T2	18		T3	3
auto[0]	auto[2]	auto[0]	207822	1			T4	3		T12	4		T13	10145
auto[0]	auto[2]	auto[1]	25815	1			T4	119		T12	17		T13	1041
auto[0]	auto[2]	auto[2]	20964	1			T4	19		T12	7		T13	1016
auto[0]	auto[2]	auto[3]	53410	1			T4	2010		T12	70		T13	101
auto[0]	auto[3]	auto[0]	3134755	1			T1	55657		T2	361		T8	53
auto[0]	auto[3]	auto[1]	345642	1			T1	5381		T2	43		T8	269
auto[0]	auto[3]	auto[2]	364875	1			T1	4832		T2	108		T3	2
auto[0]	auto[3]	auto[3]	435840	1			T1	527		T2	11		T3	2
auto[1]	auto[0]	auto[0]	8850	1			T13	1		T139	909		T140	253
auto[1]	auto[0]	auto[1]	39894	1			T139	4053		T140	1327		T141	4929
auto[1]	auto[0]	auto[2]	39799	1			T139	4023		T140	1310		T141	4902
auto[1]	auto[0]	auto[3]	178785	1			T139	18133		T140	5554		T141	21677
auto[1]	auto[1]	auto[0]	3923262	1			T1	2		T3	175		T11	1658
auto[1]	auto[1]	auto[1]	659841	1			T3	2322		T11	6652		T57	3215
auto[1]	auto[1]	auto[2]	630914	1			T3	778		T11	7372		T57	1169
auto[1]	auto[1]	auto[3]	1347079	1			T3	10332		T9	1		T11	30002
auto[1]	auto[2]	auto[0]	7593	1			T139	799		T140	156		T141	990
auto[1]	auto[2]	auto[1]	34696	1			T13	1		T139	3801		T140	705
auto[1]	auto[2]	auto[2]	31436	1			T139	2668		T140	1370		T141	4254
auto[1]	auto[2]	auto[3]	141725	1			T139	12290		T140	6270		T141	18613
auto[1]	auto[3]	auto[0]	3917774	1			T1	5		T3	182		T11	1654
auto[1]	auto[3]	auto[1]	624457	1			T1	1		T3	847		T11	7395
auto[1]	auto[3]	auto[2]	651774	1			T3	2290		T11	6704		T57	3268
auto[1]	auto[3]	auto[3]	1311327	1			T3	10200		T9	2		T11	29963